blob: 93d51fe66239091d8ee98afe911e0b6679aae016 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7a3b5eb2016-12-09 15:23:08 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Dan Handley9df48042015-03-19 18:58:55 +00007#include <arch_helpers.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +01008#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +01009#include <cassert.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010010#include <css_pm.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <debug.h>
12#include <errno.h>
13#include <plat_arm.h>
14#include <platform.h>
15#include <platform_def.h>
Soby Mathew200fffd2016-10-21 11:34:59 +010016#include "../drivers/scp/css_scp.h"
Soby Mathew12012dd2015-10-26 14:01:53 +000017
Soby Mathewfeac8fc2015-09-29 15:47:16 +010018/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
19#pragma weak plat_arm_psci_pm_ops
Soby Mathewfec4eb72015-07-01 16:16:20 +010020
Soby Mathew7799cf72015-04-16 14:49:09 +010021#if ARM_RECOM_STATE_ID_ENC
22/*
23 * The table storing the valid idle power states. Ensure that the
24 * array entries are populated in ascending order of state-id to
25 * enable us to use binary search during power state validation.
26 * The table must be terminated by a NULL entry.
27 */
28const unsigned int arm_pm_idle_states[] = {
Soby Mathewa869de12015-05-08 10:18:59 +010029 /* State-id - 0x001 */
30 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
31 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
32 /* State-id - 0x002 */
33 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
34 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
35 /* State-id - 0x022 */
36 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
37 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
38#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
39 /* State-id - 0x222 */
40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
42#endif
Soby Mathew7799cf72015-04-16 14:49:09 +010043 0,
44};
Soby Mathewa869de12015-05-08 10:18:59 +010045#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew7799cf72015-04-16 14:49:09 +010046
Soby Mathew61e8d0b2015-10-12 17:32:29 +010047/*
48 * All the power management helpers in this file assume at least cluster power
49 * level is supported.
50 */
51CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
52 assert_max_pwr_lvl_supported_mismatch);
53
Soby Mathew7a3b5eb2016-12-09 15:23:08 +000054/*
55 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
56 * assumed by the CSS layer.
57 */
58CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
59 assert_max_pwr_lvl_higher_than_css_sys_lvl);
60
Dan Handley9df48042015-03-19 18:58:55 +000061/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010062 * Handler called when a power domain is about to be turned on. The
Dan Handley9df48042015-03-19 18:58:55 +000063 * level and mpidr determine the affinity instance.
64 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010065int css_pwr_domain_on(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000066{
Soby Mathew200fffd2016-10-21 11:34:59 +010067 css_scp_on(mpidr);
Dan Handley9df48042015-03-19 18:58:55 +000068
69 return PSCI_E_SUCCESS;
70}
71
Soby Mathew12012dd2015-10-26 14:01:53 +000072static void css_pwr_domain_on_finisher_common(
73 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +000074{
Soby Mathew12012dd2015-10-26 14:01:53 +000075 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010076
Dan Handley9df48042015-03-19 18:58:55 +000077 /*
78 * Perform the common cluster specific operations i.e enable coherency
79 * if this cluster was off.
80 */
Soby Mathew12012dd2015-10-26 14:01:53 +000081 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +000082 plat_arm_interconnect_enter_coherency();
Soby Mathew12012dd2015-10-26 14:01:53 +000083}
Dan Handley9df48042015-03-19 18:58:55 +000084
Soby Mathew12012dd2015-10-26 14:01:53 +000085/*******************************************************************************
86 * Handler called when a power level has just been powered on after
87 * being turned off earlier. The target_state encodes the low power state that
88 * each level has woken up from. This handler would never be invoked with
89 * the system power domain uninitialized as either the primary would have taken
90 * care of it as part of cold boot or the first core awakened from system
91 * suspend would have already initialized it.
92 ******************************************************************************/
93void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
94{
95 /* Assert that the system power domain need not be initialized */
96 assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010097
Soby Mathew12012dd2015-10-26 14:01:53 +000098 css_pwr_domain_on_finisher_common(target_state);
Soby Mathew61e8d0b2015-10-12 17:32:29 +010099
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000100 /* Program the gic per-cpu distributor or re-distributor interface */
101 plat_arm_gic_pcpu_init();
102
Dan Handley9df48042015-03-19 18:58:55 +0000103 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000104 plat_arm_gic_cpuif_enable();
Dan Handley9df48042015-03-19 18:58:55 +0000105}
106
107/*******************************************************************************
108 * Common function called while turning a cpu off or suspending it. It is called
109 * from css_off() or css_suspend() when these functions in turn are called for
Soby Mathewfec4eb72015-07-01 16:16:20 +0100110 * power domain at the highest power level which will be powered down. It
111 * performs the actions common to the OFF and SUSPEND calls.
Dan Handley9df48042015-03-19 18:58:55 +0000112 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100113static void css_power_down_common(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000114{
Dan Handley9df48042015-03-19 18:58:55 +0000115 /* Prevent interrupts from spuriously waking up this cpu */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000116 plat_arm_gic_cpuif_disable();
Dan Handley9df48042015-03-19 18:58:55 +0000117
118 /* Cluster is to be turned off, so disable coherency */
Soby Mathew200fffd2016-10-21 11:34:59 +0100119 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000120 plat_arm_interconnect_exit_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000121}
122
123/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100124 * Handler called when a power domain is about to be turned off. The
125 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000126 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100127void css_pwr_domain_off(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000128{
Soby Mathew12012dd2015-10-26 14:01:53 +0000129 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100130 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100131 css_scp_off(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000132}
133
134/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100135 * Handler called when a power domain is about to be suspended. The
136 * target_state encodes the power state that each level should transition to.
Dan Handley9df48042015-03-19 18:58:55 +0000137 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100138void css_pwr_domain_suspend(const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000139{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100140 /*
Soby Mathew12012dd2015-10-26 14:01:53 +0000141 * CSS currently supports retention only at cpu level. Just return
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142 * as nothing is to be done for retention.
143 */
Soby Mathew12012dd2015-10-26 14:01:53 +0000144 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Dan Handley9df48042015-03-19 18:58:55 +0000145 return;
146
Soby Mathew12012dd2015-10-26 14:01:53 +0000147 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100148 css_power_down_common(target_state);
Soby Mathew200fffd2016-10-21 11:34:59 +0100149 css_scp_suspend(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000150}
151
152/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100153 * Handler called when a power domain has just been powered on after
154 * having been suspended earlier. The target_state encodes the low power state
155 * that each level has woken up from.
Dan Handley9df48042015-03-19 18:58:55 +0000156 * TODO: At the moment we reuse the on finisher and reinitialize the secure
157 * context. Need to implement a separate suspend finisher.
158 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100159void css_pwr_domain_suspend_finish(
Soby Mathewfec4eb72015-07-01 16:16:20 +0100160 const psci_power_state_t *target_state)
Dan Handley9df48042015-03-19 18:58:55 +0000161{
Soby Mathew12012dd2015-10-26 14:01:53 +0000162 /* Return as nothing is to be done on waking up from retention. */
163 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
Soby Mathewfec4eb72015-07-01 16:16:20 +0100164 return;
165
Soby Mathew12012dd2015-10-26 14:01:53 +0000166 /* Perform system domain restore if woken up from system suspend */
167 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
168 arm_system_pwr_domain_resume();
169 else
170 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000171 plat_arm_gic_cpuif_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000172
173 css_pwr_domain_on_finisher_common(target_state);
Dan Handley9df48042015-03-19 18:58:55 +0000174}
175
176/*******************************************************************************
177 * Handlers to shutdown/reboot the system
178 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100179void __dead2 css_system_off(void)
Dan Handley9df48042015-03-19 18:58:55 +0000180{
Soby Mathew200fffd2016-10-21 11:34:59 +0100181 css_scp_sys_shutdown();
Dan Handley9df48042015-03-19 18:58:55 +0000182}
183
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100184void __dead2 css_system_reset(void)
Dan Handley9df48042015-03-19 18:58:55 +0000185{
Soby Mathew200fffd2016-10-21 11:34:59 +0100186 css_scp_sys_reboot();
Dan Handley9df48042015-03-19 18:58:55 +0000187}
188
189/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100190 * Handler called when the CPU power domain is about to enter standby.
Dan Handley9df48042015-03-19 18:58:55 +0000191 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100192void css_cpu_standby(plat_local_state_t cpu_state)
Dan Handley9df48042015-03-19 18:58:55 +0000193{
194 unsigned int scr;
195
Soby Mathewfec4eb72015-07-01 16:16:20 +0100196 assert(cpu_state == ARM_LOCAL_STATE_RET);
197
Dan Handley9df48042015-03-19 18:58:55 +0000198 scr = read_scr_el3();
David Wangc1d9cfb2016-06-07 09:22:40 +0800199 /*
200 * Enable the Non secure interrupt to wake the CPU.
201 * In GICv3 affinity routing mode, the non secure group1 interrupts use
202 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
203 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
204 * routing mode.
205 */
206 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
Dan Handley9df48042015-03-19 18:58:55 +0000207 isb();
208 dsb();
209 wfi();
210
211 /*
212 * Restore SCR to the original value, synchronisation of scr_el3 is
213 * done by eret while el3_exit to save some execution cycles.
214 */
215 write_scr_el3(scr);
216}
217
218/*******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100219 * Handler called to return the 'req_state' for system suspend.
220 ******************************************************************************/
221void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
222{
223 unsigned int i;
224
225 /*
226 * System Suspend is supported only if the system power domain node
227 * is implemented.
228 */
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000229 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100230
231 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
232 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
233}
234
235/*******************************************************************************
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100236 * Handler to query CPU/cluster power states from SCP
237 ******************************************************************************/
238int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
239{
Soby Mathew200fffd2016-10-21 11:34:59 +0100240 return css_scp_get_power_state(mpidr, power_level);
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100241}
242
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000243/*
244 * The system power domain suspend is only supported only via
245 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
246 * will be downgraded to the lower level.
247 */
248static int css_validate_power_state(unsigned int power_state,
249 psci_power_state_t *req_state)
250{
251 int rc;
252 rc = arm_validate_power_state(power_state, req_state);
253
254 /*
255 * Ensure that the system power domain level is never suspended
256 * via PSCI CPU SUSPEND API. Currently system suspend is only
257 * supported via PSCI SYSTEM SUSPEND API.
258 */
259 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = ARM_LOCAL_STATE_RUN;
260 return rc;
261}
262
263/*
264 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
265 * `css_validate_power_state`, we do not downgrade the system power
266 * domain level request in `power_state` as it will be used to query the
267 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
268 */
269static int css_translate_power_state_by_mpidr(u_register_t mpidr,
270 unsigned int power_state,
271 psci_power_state_t *output_state)
272{
273 return arm_validate_power_state(power_state, output_state);
274}
275
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100276/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100277 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
278 * platform will take care of registering the handlers with PSCI.
Dan Handley9df48042015-03-19 18:58:55 +0000279 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100280plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100281 .pwr_domain_on = css_pwr_domain_on,
282 .pwr_domain_on_finish = css_pwr_domain_on_finish,
283 .pwr_domain_off = css_pwr_domain_off,
284 .cpu_standby = css_cpu_standby,
285 .pwr_domain_suspend = css_pwr_domain_suspend,
286 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
Dan Handley9df48042015-03-19 18:58:55 +0000287 .system_off = css_system_off,
288 .system_reset = css_system_reset,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000289 .validate_power_state = css_validate_power_state,
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100290 .validate_ns_entrypoint = arm_validate_ns_entrypoint,
Soby Mathew7a3b5eb2016-12-09 15:23:08 +0000291 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
292 .get_node_hw_state = css_node_hw_state,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100293 .get_sys_suspend_power_state = css_get_sys_suspend_power_state,
294/*
295 * mem_protect is not supported in RESET_TO_BL31 and RESET_TO_SP_MIN,
296 * as that would require mapping in all of NS DRAM into BL31 or BL32.
297 */
298#if defined(PLAT_ARM_MEM_PROT_ADDR) && !RESET_TO_BL31 && !RESET_TO_SP_MIN
299 .mem_protect_chk = arm_psci_mem_protect_chk,
300 .read_mem_protect = arm_psci_read_mem_protect,
301 .write_mem_protect = arm_nor_psci_write_mem_protect,
302#endif
Dan Handley9df48042015-03-19 18:58:55 +0000303};