Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
Lionel Debieve | bc2d88d | 2019-11-04 14:31:38 +0100 | [diff] [blame] | 2 | * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP_COMMON_H |
| 8 | #define STM32MP_COMMON_H |
| 9 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 10 | #include <stdbool.h> |
| 11 | |
Yann Gautier | e97b663 | 2019-04-19 10:48:36 +0200 | [diff] [blame] | 12 | #include <platform_def.h> |
| 13 | |
Yann Gautier | ed6515d | 2021-03-08 15:03:35 +0100 | [diff] [blame] | 14 | #define JEDEC_ST_BKID U(0x0) |
| 15 | #define JEDEC_ST_MFID U(0x20) |
| 16 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 17 | /* Functions to save and get boot context address given by ROM code */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 18 | void stm32mp_save_boot_ctx_address(uintptr_t address); |
| 19 | uintptr_t stm32mp_get_boot_ctx_address(void); |
Yann Gautier | cf1360d | 2020-08-27 18:28:57 +0200 | [diff] [blame] | 20 | uint16_t stm32mp_get_boot_itf_selected(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 21 | |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 22 | bool stm32mp_is_single_core(void); |
Lionel Debieve | 0e73d73 | 2019-09-16 12:17:09 +0200 | [diff] [blame] | 23 | bool stm32mp_is_closed_device(void); |
Lionel Debieve | 06bc62d | 2019-12-06 12:42:20 +0100 | [diff] [blame] | 24 | bool stm32mp_is_auth_supported(void); |
Yann Gautier | af19ff9 | 2019-06-04 18:23:10 +0200 | [diff] [blame] | 25 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 26 | /* Return the base address of the DDR controller */ |
| 27 | uintptr_t stm32mp_ddrctrl_base(void); |
| 28 | |
| 29 | /* Return the base address of the DDR PHY */ |
| 30 | uintptr_t stm32mp_ddrphyc_base(void); |
| 31 | |
| 32 | /* Return the base address of the PWR peripheral */ |
| 33 | uintptr_t stm32mp_pwr_base(void); |
| 34 | |
| 35 | /* Return the base address of the RCC peripheral */ |
| 36 | uintptr_t stm32mp_rcc_base(void); |
| 37 | |
Yann Gautier | f540a59 | 2019-05-22 19:13:51 +0200 | [diff] [blame] | 38 | /* Check MMU status to allow spinlock use */ |
| 39 | bool stm32mp_lock_available(void); |
| 40 | |
Lionel Debieve | bc2d88d | 2019-11-04 14:31:38 +0100 | [diff] [blame] | 41 | int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, |
| 42 | uint32_t *otp_len); |
| 43 | int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val); |
| 44 | int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val); |
| 45 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 46 | /* Get IWDG platform instance ID from peripheral IO memory base address */ |
| 47 | uint32_t stm32_iwdg_get_instance(uintptr_t base); |
| 48 | |
| 49 | /* Return bitflag mask for expected IWDG configuration from OTP content */ |
| 50 | uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); |
| 51 | |
| 52 | #if defined(IMAGE_BL2) |
| 53 | /* Update OTP shadow registers with IWDG configuration from device tree */ |
| 54 | uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); |
| 55 | #endif |
| 56 | |
Yann Gautier | 3d8497c | 2021-10-18 16:06:22 +0200 | [diff] [blame] | 57 | #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) |
Patrick Delaunay | e50571b | 2021-10-28 13:48:52 +0200 | [diff] [blame] | 58 | /* Get the UART address from its instance number */ |
| 59 | uintptr_t get_uart_address(uint32_t instance_nb); |
| 60 | #endif |
| 61 | |
Yann Gautier | 7a81912 | 2021-10-18 15:26:33 +0200 | [diff] [blame] | 62 | /* Setup the UART console */ |
| 63 | int stm32mp_uart_console_setup(void); |
| 64 | |
Yann Gautier | d143574 | 2021-10-18 10:55:23 +0200 | [diff] [blame] | 65 | #if STM32MP_EARLY_CONSOLE |
| 66 | void stm32mp_setup_early_console(void); |
| 67 | #else |
| 68 | static inline void stm32mp_setup_early_console(void) |
| 69 | { |
| 70 | } |
| 71 | #endif |
| 72 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 73 | /* |
| 74 | * Platform util functions for the GPIO driver |
| 75 | * @bank: Target GPIO bank ID as per DT bindings |
| 76 | * |
| 77 | * Platform shall implement these functions to provide to stm32_gpio |
| 78 | * driver the resource reference for a target GPIO bank. That are |
| 79 | * memory mapped interface base address, interface offset (see below) |
| 80 | * and clock identifier. |
| 81 | * |
| 82 | * stm32_get_gpio_bank_offset() returns a bank offset that is used to |
| 83 | * check DT configuration matches platform implementation of the banks |
| 84 | * description. |
| 85 | */ |
| 86 | uintptr_t stm32_get_gpio_bank_base(unsigned int bank); |
| 87 | unsigned long stm32_get_gpio_bank_clock(unsigned int bank); |
| 88 | uint32_t stm32_get_gpio_bank_offset(unsigned int bank); |
Yann Gautier | 2b79c37 | 2021-06-11 10:54:56 +0200 | [diff] [blame] | 89 | bool stm32_gpio_is_secure_at_reset(unsigned int bank); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 90 | |
Etienne Carriere | d81dadf | 2020-04-25 11:14:45 +0200 | [diff] [blame] | 91 | /* Return node offset for target GPIO bank ID @bank or a FDT error code */ |
| 92 | int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); |
| 93 | |
Yann Gautier | a0a6ff6 | 2021-05-10 16:05:18 +0200 | [diff] [blame] | 94 | /* Get the chip revision */ |
| 95 | uint32_t stm32mp_get_chip_version(void); |
| 96 | /* Get the chip device ID */ |
| 97 | uint32_t stm32mp_get_chip_dev_id(void); |
| 98 | |
| 99 | /* Get SOC name */ |
| 100 | #define STM32_SOC_NAME_SIZE 20 |
| 101 | void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); |
| 102 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 103 | /* Print CPU information */ |
| 104 | void stm32mp_print_cpuinfo(void); |
| 105 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 106 | /* Print board information */ |
| 107 | void stm32mp_print_boardinfo(void); |
| 108 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 109 | /* Initialise the IO layer and register platform IO devices */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 110 | void stm32mp_io_setup(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 111 | |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 112 | /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ |
| 113 | int stm32mp_map_ddr_non_cacheable(void); |
| 114 | int stm32mp_unmap_ddr(void); |
| 115 | |
Yann Gautier | aaee061 | 2020-12-16 12:04:06 +0100 | [diff] [blame] | 116 | /* Functions to save and get boot peripheral info */ |
Yann Gautier | 6eef525 | 2021-12-10 17:04:40 +0100 | [diff] [blame] | 117 | void stm32_save_boot_interface(uint32_t interface, uint32_t instance); |
Yann Gautier | aaee061 | 2020-12-16 12:04:06 +0100 | [diff] [blame] | 118 | void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance); |
Yann Gautier | 6eef525 | 2021-12-10 17:04:40 +0100 | [diff] [blame] | 119 | |
Igor Opaniuk | f07e8f3 | 2022-06-23 21:19:26 +0300 | [diff] [blame] | 120 | /* Functions to save and get boot authentication status and partition used */ |
| 121 | void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition); |
| 122 | |
Yann Gautier | 5d2eb55 | 2022-11-14 14:14:48 +0100 | [diff] [blame] | 123 | #if PSA_FWU_SUPPORT |
Sughosh Ganu | 03e2f80 | 2021-12-01 15:56:27 +0530 | [diff] [blame] | 124 | void stm32mp1_fwu_set_boot_idx(void); |
Nicolas Toromanoff | 5a937cd | 2022-02-07 10:12:04 +0100 | [diff] [blame] | 125 | uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void); |
| 126 | void stm32_set_max_fwu_trial_boot_cnt(void); |
Yann Gautier | 5d2eb55 | 2022-11-14 14:14:48 +0100 | [diff] [blame] | 127 | #endif /* PSA_FWU_SUPPORT */ |
Sughosh Ganu | 03e2f80 | 2021-12-01 15:56:27 +0530 | [diff] [blame] | 128 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 129 | #endif /* STM32MP_COMMON_H */ |