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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
Lionel Debievebc2d88d2019-11-04 14:31:38 +01002 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
Yann Gautieree8f5422019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP_COMMON_H
8#define STM32MP_COMMON_H
9
Yann Gautiera2e2a302019-02-14 11:13:39 +010010#include <stdbool.h>
11
Yann Gautiere97b6632019-04-19 10:48:36 +020012#include <platform_def.h>
13
Yann Gautiered6515d2021-03-08 15:03:35 +010014#define JEDEC_ST_BKID U(0x0)
15#define JEDEC_ST_MFID U(0x20)
16
Yann Gautieree8f5422019-02-14 11:13:25 +010017/* Functions to save and get boot context address given by ROM code */
Yann Gautiera2e2a302019-02-14 11:13:39 +010018void stm32mp_save_boot_ctx_address(uintptr_t address);
19uintptr_t stm32mp_get_boot_ctx_address(void);
Yann Gautiercf1360d2020-08-27 18:28:57 +020020uint16_t stm32mp_get_boot_itf_selected(void);
Yann Gautieree8f5422019-02-14 11:13:25 +010021
Yann Gautieraf19ff92019-06-04 18:23:10 +020022bool stm32mp_is_single_core(void);
Lionel Debieve0e73d732019-09-16 12:17:09 +020023bool stm32mp_is_closed_device(void);
Lionel Debieve06bc62d2019-12-06 12:42:20 +010024bool stm32mp_is_auth_supported(void);
Yann Gautieraf19ff92019-06-04 18:23:10 +020025
Yann Gautier3d78a2e2019-02-14 11:01:20 +010026/* Return the base address of the DDR controller */
27uintptr_t stm32mp_ddrctrl_base(void);
28
29/* Return the base address of the DDR PHY */
30uintptr_t stm32mp_ddrphyc_base(void);
31
32/* Return the base address of the PWR peripheral */
33uintptr_t stm32mp_pwr_base(void);
34
35/* Return the base address of the RCC peripheral */
36uintptr_t stm32mp_rcc_base(void);
37
Yann Gautierf540a592019-05-22 19:13:51 +020038/* Check MMU status to allow spinlock use */
39bool stm32mp_lock_available(void);
40
Lionel Debievebc2d88d2019-11-04 14:31:38 +010041int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
42 uint32_t *otp_len);
43int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val);
44int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val);
45
Yann Gautier091eab52019-06-04 18:06:34 +020046/* Get IWDG platform instance ID from peripheral IO memory base address */
47uint32_t stm32_iwdg_get_instance(uintptr_t base);
48
49/* Return bitflag mask for expected IWDG configuration from OTP content */
50uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
51
52#if defined(IMAGE_BL2)
53/* Update OTP shadow registers with IWDG configuration from device tree */
54uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
55#endif
56
Yann Gautier3d8497c2021-10-18 16:06:22 +020057#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
Patrick Delaunaye50571b2021-10-28 13:48:52 +020058/* Get the UART address from its instance number */
59uintptr_t get_uart_address(uint32_t instance_nb);
60#endif
61
Yann Gautier7a819122021-10-18 15:26:33 +020062/* Setup the UART console */
63int stm32mp_uart_console_setup(void);
64
Yann Gautierd1435742021-10-18 10:55:23 +020065#if STM32MP_EARLY_CONSOLE
66void stm32mp_setup_early_console(void);
67#else
68static inline void stm32mp_setup_early_console(void)
69{
70}
71#endif
72
Yann Gautieree8f5422019-02-14 11:13:25 +010073/*
74 * Platform util functions for the GPIO driver
75 * @bank: Target GPIO bank ID as per DT bindings
76 *
77 * Platform shall implement these functions to provide to stm32_gpio
78 * driver the resource reference for a target GPIO bank. That are
79 * memory mapped interface base address, interface offset (see below)
80 * and clock identifier.
81 *
82 * stm32_get_gpio_bank_offset() returns a bank offset that is used to
83 * check DT configuration matches platform implementation of the banks
84 * description.
85 */
86uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
87unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
88uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
Yann Gautier2b79c372021-06-11 10:54:56 +020089bool stm32_gpio_is_secure_at_reset(unsigned int bank);
Yann Gautieree8f5422019-02-14 11:13:25 +010090
Etienne Carriered81dadf2020-04-25 11:14:45 +020091/* Return node offset for target GPIO bank ID @bank or a FDT error code */
92int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
93
Yann Gautiera0a6ff62021-05-10 16:05:18 +020094/* Get the chip revision */
95uint32_t stm32mp_get_chip_version(void);
96/* Get the chip device ID */
97uint32_t stm32mp_get_chip_dev_id(void);
98
99/* Get SOC name */
100#define STM32_SOC_NAME_SIZE 20
101void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
102
Yann Gautierc7374052019-06-04 18:02:37 +0200103/* Print CPU information */
104void stm32mp_print_cpuinfo(void);
105
Yann Gautier35dc0772019-05-13 18:34:48 +0200106/* Print board information */
107void stm32mp_print_boardinfo(void);
108
Yann Gautieree8f5422019-02-14 11:13:25 +0100109/* Initialise the IO layer and register platform IO devices */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100110void stm32mp_io_setup(void);
Yann Gautieree8f5422019-02-14 11:13:25 +0100111
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200112#if STM32MP_USE_STM32IMAGE
Yann Gautiere97b6632019-04-19 10:48:36 +0200113/*
114 * Check that the STM32 header of a .stm32 binary image is valid
115 * @param header: pointer to the stm32 image header
116 * @param buffer: address of the binary image (payload)
117 * @return: 0 on success, negative value in case of error
118 */
119int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200120#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautiere97b6632019-04-19 10:48:36 +0200121
Yann Gautiera55169b2020-01-10 18:18:59 +0100122/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
123int stm32mp_map_ddr_non_cacheable(void);
124int stm32mp_unmap_ddr(void);
125
Yann Gautieraaee0612020-12-16 12:04:06 +0100126/* Functions to save and get boot peripheral info */
Yann Gautier6eef5252021-12-10 17:04:40 +0100127void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
Yann Gautieraaee0612020-12-16 12:04:06 +0100128void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
Yann Gautier6eef5252021-12-10 17:04:40 +0100129
Sughosh Ganu03e2f802021-12-01 15:56:27 +0530130#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
131void stm32mp1_fwu_set_boot_idx(void);
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100132uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void);
133void stm32_set_max_fwu_trial_boot_cnt(void);
Sughosh Ganu03e2f802021-12-01 15:56:27 +0530134#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
135
Yann Gautieree8f5422019-02-14 11:13:25 +0100136#endif /* STM32MP_COMMON_H */