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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Douglas Raillarda8954fc2017-01-26 15:54:44 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Dimitris Papastamose08005a2017-10-12 13:02:29 +01007#include <amu.h>
Achin Gupta27b895e2014-05-04 18:38:28 +01008#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +00009#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <assert.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000011#include <bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <context.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000013#include <context_mgmt.h>
Achin Gupta191e86e2014-05-09 10:03:15 +010014#include <interrupt_mgmt.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010016#include <platform_def.h>
Dimitris Papastamosa7921b92017-10-13 15:27:58 +010017#include <pubsub_events.h>
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010018#include <smcc_helpers.h>
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010019#include <spe.h>
Andrew Thoelke4e126072014-06-04 21:10:52 +010020#include <string.h>
David Cunadoce88eee2017-10-20 11:30:57 +010021#include <sve.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000022#include <utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000023
Achin Gupta7aea9082014-02-01 07:51:28 +000024
25/*******************************************************************************
26 * Context management library initialisation routine. This library is used by
27 * runtime services to share pointers to 'cpu_context' structures for the secure
28 * and non-secure states. Management of the structures and their associated
29 * memory is not done by the context management library e.g. the PSCI service
30 * manages the cpu context used for entry from and exit to the non-secure state.
31 * The Secure payload dispatcher service manages the context(s) corresponding to
32 * the secure state. It also uses this library to get access to the non-secure
33 * state cpu context pointers.
34 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
35 * which will used for programming an entry into a lower EL. The same context
36 * will used to save state upon exception entry from that EL.
37 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +010038void cm_init(void)
Achin Gupta7aea9082014-02-01 07:51:28 +000039{
40 /*
41 * The context management library has only global data to intialize, but
42 * that will be done when the BSS is zeroed out
43 */
44}
45
46/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +010047 * The following function initializes the cpu_context 'ctx' for
Andrew Thoelke4e126072014-06-04 21:10:52 +010048 * first use, and sets the initial entrypoint state as specified by the
49 * entry_point_info structure.
50 *
51 * The security state to initialize is determined by the SECURE attribute
52 * of the entry_point_info. The function returns a pointer to the initialized
53 * context and sets this as the next context to return to.
54 *
55 * The EE and ST attributes are used to configure the endianess and secure
Soby Mathewb0082d22015-04-09 13:40:55 +010056 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +010057 *
58 * To prepare the register state for entry call cm_prepare_el3_exit() and
59 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
60 * cm_e1_sysreg_context_restore().
61 ******************************************************************************/
Soby Mathewb0082d22015-04-09 13:40:55 +010062static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +010063{
Soby Mathewb0082d22015-04-09 13:40:55 +010064 unsigned int security_state;
David Cunado4168f2f2017-10-02 17:41:39 +010065 uint32_t scr_el3, pmcr_el0;
Andrew Thoelke4e126072014-06-04 21:10:52 +010066 el3_state_t *state;
67 gp_regs_t *gp_regs;
68 unsigned long sctlr_elx;
69
Andrew Thoelke4e126072014-06-04 21:10:52 +010070 assert(ctx);
71
Soby Mathewb0082d22015-04-09 13:40:55 +010072 security_state = GET_SECURITY_STATE(ep->h.attr);
73
Andrew Thoelke4e126072014-06-04 21:10:52 +010074 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000075 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +010076
77 /*
David Cunadofee86532017-04-13 22:38:29 +010078 * SCR_EL3 was initialised during reset sequence in macro
79 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
80 * affect the next EL.
81 *
82 * The following fields are initially set to zero and then updated to
83 * the required value depending on the state of the SPSR_EL3 and the
84 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +010085 */
86 scr_el3 = read_scr();
87 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
88 SCR_ST_BIT | SCR_HCE_BIT);
David Cunadofee86532017-04-13 22:38:29 +010089 /*
90 * SCR_NS: Set the security state of the next EL.
91 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010092 if (security_state != SECURE)
93 scr_el3 |= SCR_NS_BIT;
David Cunadofee86532017-04-13 22:38:29 +010094 /*
95 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
96 * Exception level as specified by SPSR.
97 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010098 if (GET_RW(ep->spsr) == MODE_RW_64)
99 scr_el3 |= SCR_RW_BIT;
David Cunadofee86532017-04-13 22:38:29 +0100100 /*
101 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
102 * Secure timer registers to EL3, from AArch64 state only, if specified
103 * by the entrypoint attributes.
104 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100105 if (EP_GET_ST(ep->h.attr))
106 scr_el3 |= SCR_ST_BIT;
107
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100108#ifndef HANDLE_EA_EL3_FIRST
David Cunadofee86532017-04-13 22:38:29 +0100109 /*
110 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
111 * to EL3 when executing at a lower EL. When executing at EL3, External
112 * Aborts are taken to EL3.
113 */
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100114 scr_el3 &= ~SCR_EA_BIT;
115#endif
116
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900117#ifdef IMAGE_BL31
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100118 /*
David Cunadofee86532017-04-13 22:38:29 +0100119 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as
120 * indicated by the interrupt routing model for BL31.
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100121 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100122 scr_el3 |= get_scr_el3_from_routing_model(security_state);
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100123#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100124
125 /*
David Cunadofee86532017-04-13 22:38:29 +0100126 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
127 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
128 * next mode is Hyp.
129 */
130 if ((GET_RW(ep->spsr) == MODE_RW_64
131 && GET_EL(ep->spsr) == MODE_EL2)
132 || (GET_RW(ep->spsr) != MODE_RW_64
133 && GET_M32(ep->spsr) == MODE32_hyp)) {
134 scr_el3 |= SCR_HCE_BIT;
135 }
136
137 /*
138 * Initialise SCTLR_EL1 to the reset value corresponding to the target
139 * execution state setting all fields rather than relying of the hw.
140 * Some fields have architecturally UNKNOWN reset values and these are
141 * set to zero.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100142 *
David Cunadofee86532017-04-13 22:38:29 +0100143 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100144 *
David Cunadofee86532017-04-13 22:38:29 +0100145 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
146 * required by PSCI specification)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100147 */
148 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200149 if (GET_RW(ep->spsr) == MODE_RW_64)
150 sctlr_elx |= SCTLR_EL1_RES1;
Soby Mathewa993c422016-09-29 14:15:57 +0100151 else {
Soby Mathewa993c422016-09-29 14:15:57 +0100152 /*
David Cunadofee86532017-04-13 22:38:29 +0100153 * If the target execution state is AArch32 then the following
154 * fields need to be set.
155 *
156 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
157 * instructions are not trapped to EL1.
158 *
159 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
160 * instructions are not trapped to EL1.
161 *
162 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
163 * CP15DMB, CP15DSB, and CP15ISB instructions.
Soby Mathewa993c422016-09-29 14:15:57 +0100164 */
David Cunadofee86532017-04-13 22:38:29 +0100165 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
166 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
Soby Mathewa993c422016-09-29 14:15:57 +0100167 }
168
David Cunadofee86532017-04-13 22:38:29 +0100169 /*
170 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
David Cunado4168f2f2017-10-02 17:41:39 +0100171 * and other EL2 registers are set up by cm_preapre_ns_entry() as they
David Cunadofee86532017-04-13 22:38:29 +0100172 * are not part of the stored cpu_context.
173 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100174 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
175
David Cunado4168f2f2017-10-02 17:41:39 +0100176 if (security_state == SECURE) {
177 /*
178 * Initialise PMCR_EL0 for secure context only, setting all
179 * fields rather than relying on hw. Some fields are
180 * architecturally UNKNOWN on reset.
181 *
182 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
183 * is recorded in PMOVSCLR_EL0[31], occurs on the increment
184 * that changes PMCCNTR_EL0[63] from 1 to 0.
185 *
186 * PMCR_EL0.DP: Set to one so that the cycle counter,
187 * PMCCNTR_EL0 does not count when event counting is prohibited.
188 *
189 * PMCR_EL0.X: Set to zero to disable export of events.
190 *
191 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
192 * counts on every clock cycle.
193 */
194 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT
195 | PMCR_EL0_DP_BIT)
196 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT));
197 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0);
198 }
199
Andrew Thoelke4e126072014-06-04 21:10:52 +0100200 /* Populate EL3 state so that we've the right context before doing ERET */
201 state = get_el3state_ctx(ctx);
202 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
203 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
204 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
205
206 /*
207 * Store the X0-X7 value from the entrypoint into the context
208 * Use memcpy as we are in control of the layout of the structures
209 */
210 gp_regs = get_gpregs_ctx(ctx);
211 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
212}
213
214/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000215 * Enable architecture extensions on first entry to Non-secure world.
216 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
217 * it is zero.
218 ******************************************************************************/
219static void enable_extensions_nonsecure(int el2_unused)
220{
221#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100222#if ENABLE_SPE_FOR_LOWER_ELS
223 spe_enable(el2_unused);
224#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100225
226#if ENABLE_AMU
227 amu_enable(el2_unused);
228#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100229
230#if ENABLE_SVE_FOR_NS
231 sve_enable(el2_unused);
232#endif
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000233#endif
234}
235
236/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100237 * The following function initializes the cpu_context for a CPU specified by
238 * its `cpu_idx` for first use, and sets the initial entrypoint state as
239 * specified by the entry_point_info structure.
240 ******************************************************************************/
241void cm_init_context_by_index(unsigned int cpu_idx,
242 const entry_point_info_t *ep)
243{
244 cpu_context_t *ctx;
245 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
246 cm_init_context_common(ctx, ep);
247}
248
249/*******************************************************************************
250 * The following function initializes the cpu_context for the current CPU
251 * for first use, and sets the initial entrypoint state as specified by the
252 * entry_point_info structure.
253 ******************************************************************************/
254void cm_init_my_context(const entry_point_info_t *ep)
255{
256 cpu_context_t *ctx;
257 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
258 cm_init_context_common(ctx, ep);
259}
260
261/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100262 * Prepare the CPU system registers for first entry into secure or normal world
263 *
264 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
265 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
266 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
267 * For all entries, the EL1 registers are initialized from the cpu_context
268 ******************************************************************************/
269void cm_prepare_el3_exit(uint32_t security_state)
270{
dp-armee3457b2017-05-23 09:32:49 +0100271 uint32_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100272 cpu_context_t *ctx = cm_get_context(security_state);
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000273 int el2_unused = 0;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100274
275 assert(ctx);
276
277 if (security_state == NON_SECURE) {
278 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
279 if (scr_el3 & SCR_HCE_BIT) {
280 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
281 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
282 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800283 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100284 sctlr_elx |= SCTLR_EL2_RES1;
285 write_sctlr_el2(sctlr_elx);
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000286 } else if (EL_IMPLEMENTED(2)) {
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000287 el2_unused = 1;
288
David Cunadofee86532017-04-13 22:38:29 +0100289 /*
290 * EL2 present but unused, need to disable safely.
291 * SCTLR_EL2 can be ignored in this case.
292 *
293 * Initialise all fields in HCR_EL2, except HCR_EL2.RW,
294 * to zero so that Non-secure operations do not trap to
295 * EL2.
296 *
297 * HCR_EL2.RW: Set this field to match SCR_EL3.RW
298 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100299 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0);
300
David Cunadofee86532017-04-13 22:38:29 +0100301 /*
302 * Initialise CPTR_EL2 setting all fields rather than
303 * relying on the hw. All fields have architecturally
304 * UNKNOWN reset values.
305 *
306 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
307 * accesses to the CPACR_EL1 or CPACR from both
308 * Execution states do not trap to EL2.
309 *
310 * CPTR_EL2.TTA: Set to zero so that Non-secure System
311 * register accesses to the trace registers from both
312 * Execution states do not trap to EL2.
313 *
314 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
315 * to SIMD and floating-point functionality from both
316 * Execution states do not trap to EL2.
317 */
318 write_cptr_el2(CPTR_EL2_RESET_VAL &
319 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
320 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100321
David Cunadofee86532017-04-13 22:38:29 +0100322 /*
323 * Initiliase CNTHCTL_EL2. All fields are
324 * architecturally UNKNOWN on reset and are set to zero
325 * except for field(s) listed below.
326 *
327 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
328 * Hyp mode of Non-secure EL0 and EL1 accesses to the
329 * physical timer registers.
330 *
331 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
332 * Hyp mode of Non-secure EL0 and EL1 accesses to the
333 * physical counter registers.
334 */
335 write_cnthctl_el2(CNTHCTL_RESET_VAL |
336 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100337
David Cunadofee86532017-04-13 22:38:29 +0100338 /*
339 * Initialise CNTVOFF_EL2 to zero as it resets to an
340 * architecturally UNKNOWN value.
341 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100342 write_cntvoff_el2(0);
343
David Cunadofee86532017-04-13 22:38:29 +0100344 /*
345 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
346 * MPIDR_EL1 respectively.
347 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100348 write_vpidr_el2(read_midr_el1());
349 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000350
351 /*
David Cunadofee86532017-04-13 22:38:29 +0100352 * Initialise VTTBR_EL2. All fields are architecturally
353 * UNKNOWN on reset.
354 *
355 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
356 * 2 address translation is disabled, cache maintenance
357 * operations depend on the VMID.
358 *
359 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
360 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000361 */
David Cunadofee86532017-04-13 22:38:29 +0100362 write_vttbr_el2(VTTBR_RESET_VAL &
363 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
364 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
365
David Cunado5f55e282016-10-31 17:37:34 +0000366 /*
David Cunadofee86532017-04-13 22:38:29 +0100367 * Initialise MDCR_EL2, setting all fields rather than
368 * relying on hw. Some fields are architecturally
369 * UNKNOWN on reset.
370 *
371 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
372 * EL1 System register accesses to the Debug ROM
373 * registers are not trapped to EL2.
374 *
375 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
376 * System register accesses to the powerdown debug
377 * registers are not trapped to EL2.
378 *
379 * MDCR_EL2.TDA: Set to zero so that System register
380 * accesses to the debug registers do not trap to EL2.
381 *
382 * MDCR_EL2.TDE: Set to zero so that debug exceptions
383 * are not routed to EL2.
384 *
385 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
386 * Monitors.
387 *
388 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
389 * EL1 accesses to all Performance Monitors registers
390 * are not trapped to EL2.
391 *
392 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
393 * and EL1 accesses to the PMCR_EL0 or PMCR are not
394 * trapped to EL2.
395 *
396 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
397 * architecturally-defined reset value.
David Cunado5f55e282016-10-31 17:37:34 +0000398 */
dp-armee3457b2017-05-23 09:32:49 +0100399 mdcr_el2 = ((MDCR_EL2_RESET_VAL |
David Cunadofee86532017-04-13 22:38:29 +0100400 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
401 >> PMCR_EL0_N_SHIFT)) &
402 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT
403 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT
404 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT
405 | MDCR_EL2_TPMCR_BIT));
dp-armee3457b2017-05-23 09:32:49 +0100406
dp-armee3457b2017-05-23 09:32:49 +0100407 write_mdcr_el2(mdcr_el2);
408
David Cunadoc14b08e2016-11-25 00:21:59 +0000409 /*
David Cunadofee86532017-04-13 22:38:29 +0100410 * Initialise HSTR_EL2. All fields are architecturally
411 * UNKNOWN on reset.
412 *
413 * HSTR_EL2.T<n>: Set all these fields to zero so that
414 * Non-secure EL0 or EL1 accesses to System registers
415 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000416 */
David Cunadofee86532017-04-13 22:38:29 +0100417 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000418 /*
David Cunadofee86532017-04-13 22:38:29 +0100419 * Initialise CNTHP_CTL_EL2. All fields are
420 * architecturally UNKNOWN on reset.
421 *
422 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
423 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000424 */
David Cunadofee86532017-04-13 22:38:29 +0100425 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
426 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100427 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000428 enable_extensions_nonsecure(el2_unused);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100429 }
430
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100431 cm_el1_sysregs_context_restore(security_state);
432 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100433}
434
435/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +0100436 * The next four functions are used by runtime services to save and restore
437 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000438 * state.
439 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000440void cm_el1_sysregs_context_save(uint32_t security_state)
441{
Dan Handleye2712bc2014-04-10 15:37:22 +0100442 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000443
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100444 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000445 assert(ctx);
446
447 el1_sysregs_context_save(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100448
449#if IMAGE_BL31
450 if (security_state == SECURE)
451 PUBLISH_EVENT(cm_exited_secure_world);
452 else
453 PUBLISH_EVENT(cm_exited_normal_world);
454#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000455}
456
457void cm_el1_sysregs_context_restore(uint32_t security_state)
458{
Dan Handleye2712bc2014-04-10 15:37:22 +0100459 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000460
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100461 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000462 assert(ctx);
463
464 el1_sysregs_context_restore(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100465
466#if IMAGE_BL31
467 if (security_state == SECURE)
468 PUBLISH_EVENT(cm_entering_secure_world);
469 else
470 PUBLISH_EVENT(cm_entering_normal_world);
471#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000472}
473
474/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100475 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
476 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000477 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100478void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000479{
Dan Handleye2712bc2014-04-10 15:37:22 +0100480 cpu_context_t *ctx;
481 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000482
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100483 ctx = cm_get_context(security_state);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000484 assert(ctx);
485
Andrew Thoelke4e126072014-06-04 21:10:52 +0100486 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000487 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000488 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000489}
490
491/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100492 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
493 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +0000494 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +0100495void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100496 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +0000497{
Dan Handleye2712bc2014-04-10 15:37:22 +0100498 cpu_context_t *ctx;
499 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000500
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100501 ctx = cm_get_context(security_state);
Achin Gupta607084e2014-02-09 18:24:19 +0000502 assert(ctx);
503
504 /* Populate EL3 state so that ERET jumps to the correct entry */
505 state = get_el3state_ctx(ctx);
506 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100507 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +0000508}
509
510/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +0100511 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
512 * pertaining to the given security state using the value and bit position
513 * specified in the parameters. It preserves all other bits.
514 ******************************************************************************/
515void cm_write_scr_el3_bit(uint32_t security_state,
516 uint32_t bit_pos,
517 uint32_t value)
518{
519 cpu_context_t *ctx;
520 el3_state_t *state;
521 uint32_t scr_el3;
522
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100523 ctx = cm_get_context(security_state);
Achin Gupta27b895e2014-05-04 18:38:28 +0100524 assert(ctx);
525
526 /* Ensure that the bit position is a valid one */
527 assert((1 << bit_pos) & SCR_VALID_BIT_MASK);
528
529 /* Ensure that the 'value' is only a bit wide */
530 assert(value <= 1);
531
532 /*
533 * Get the SCR_EL3 value from the cpu context, clear the desired bit
534 * and set it to its new value.
535 */
536 state = get_el3state_ctx(ctx);
537 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
538 scr_el3 &= ~(1 << bit_pos);
539 scr_el3 |= value << bit_pos;
540 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
541}
542
543/*******************************************************************************
544 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
545 * given security state.
546 ******************************************************************************/
547uint32_t cm_get_scr_el3(uint32_t security_state)
548{
549 cpu_context_t *ctx;
550 el3_state_t *state;
551
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100552 ctx = cm_get_context(security_state);
Achin Gupta27b895e2014-05-04 18:38:28 +0100553 assert(ctx);
554
555 /* Populate EL3 state so that ERET jumps to the correct entry */
556 state = get_el3state_ctx(ctx);
557 return read_ctx_reg(state, CTX_SCR_EL3);
558}
559
560/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000561 * This function is used to program the context that's used for exception
562 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
563 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000564 ******************************************************************************/
565void cm_set_next_eret_context(uint32_t security_state)
566{
Dan Handleye2712bc2014-04-10 15:37:22 +0100567 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000568
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100569 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000570 assert(ctx);
571
Andrew Thoelke4e126072014-06-04 21:10:52 +0100572 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000573}