blob: bb1595a3a7920e4752fbd16d7fb1a3de909d4f37 [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar4edc17c2017-11-20 17:14:47 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl31/bl31.h>
10#include <common/bl_common.h>
11#include <common/interrupt_props.h>
12#include <drivers/console.h>
13#include <context.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <cortex_a57.h>
16#include <common/debug.h>
17#include <denver.h>
18#include <drivers/arm/gic_common.h>
19#include <drivers/arm/gicv2.h>
20#include <bl31/interrupt_mgmt.h>
21#include <mce.h>
Dilan Lee4e7a63c2017-08-10 16:01:42 +080022#include <mce_private.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070023#include <plat/common/platform.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070024#include <spe.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070025#include <tegra_def.h>
Varun Wadekar128f46a2019-10-24 16:06:12 -070026#include <tegra_mc_def.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070027#include <tegra_platform.h>
28#include <tegra_private.h>
29#include <lib/xlat_tables/xlat_tables_v2.h>
30
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070031/* ID for spe-console */
32#define TEGRA_CONSOLE_SPE_ID 0xFE
33
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070034/*******************************************************************************
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -070035 * Structure to store the SCR addresses and its expected settings.
36 *******************************************************************************
37 */
38typedef struct {
39 uint32_t scr_addr;
40 uint32_t scr_val;
41} scr_settings_t;
42
43static const scr_settings_t t194_scr_settings[] = {
44 { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
45 { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
46 { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
47 { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
48 { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
49 { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
50 { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
51 { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
52 { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
53};
54
55/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070056 * The Tegra power domain tree has a single system level power domain i.e. a
57 * single root node. The first entry in the power domain descriptor specifies
58 * the number of power domains at the highest power level.
59 *******************************************************************************
60 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080061static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070062 /* No of root nodes */
63 1,
64 /* No of clusters */
65 PLATFORM_CLUSTER_COUNT,
66 /* No of CPU cores - cluster0 */
67 PLATFORM_MAX_CPUS_PER_CLUSTER,
68 /* No of CPU cores - cluster1 */
Varun Wadekara07d1c72017-08-23 14:59:09 -070069 PLATFORM_MAX_CPUS_PER_CLUSTER,
70 /* No of CPU cores - cluster2 */
71 PLATFORM_MAX_CPUS_PER_CLUSTER,
72 /* No of CPU cores - cluster3 */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070073 PLATFORM_MAX_CPUS_PER_CLUSTER
74};
75
Varun Wadekara7265be2017-04-28 08:45:53 -070076/*******************************************************************************
77 * This function returns the Tegra default topology tree information.
78 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080079const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekara7265be2017-04-28 08:45:53 -070080{
81 return tegra_power_domain_tree_desc;
82}
83
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070084/*
85 * Table of regions to map using the MMU.
86 */
87static const mmap_region_t tegra_mmap[] = {
Varun Wadekar03aa0142018-01-23 14:51:40 -080088 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080089 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
90 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
91 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar602cf7e2018-04-03 13:10:48 -070092 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
93 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080094 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080095 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080096 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080097 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070098#if !ENABLE_CONSOLE_SPE
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080099 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
100 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
101 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
103 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700105#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -0800106 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800107 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800108 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800109 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800110 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800111 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800112 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -0800113 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800114 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800115 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800116 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
117 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
118 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800119 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700120#if ENABLE_CONSOLE_SPE
Varun Wadekar03aa0142018-01-23 14:51:40 -0800121 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700122 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
123#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -0800124 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -0800125 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800126 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800127 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800128 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800129 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800130 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800131 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800132 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800133 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800134 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800135 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800136 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800137 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700138 {0}
139};
140
141/*******************************************************************************
142 * Set up the pagetables as per the platform memory map & initialize the MMU
143 ******************************************************************************/
144const mmap_region_t *plat_get_mmio_map(void)
145{
146 /* MMIO space */
147 return tegra_mmap;
148}
149
150/*******************************************************************************
151 * Handler to get the System Counter Frequency
152 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800153uint32_t plat_get_syscnt_freq2(void)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700154{
155 return 31250000;
156}
157
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700158#if !ENABLE_CONSOLE_SPE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700159/*******************************************************************************
160 * Maximum supported UART controllers
161 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800162#define TEGRA194_MAX_UART_PORTS 7
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700163
164/*******************************************************************************
165 * This variable holds the UART port base addresses
166 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800167static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700168 0, /* undefined - treated as an error case */
169 TEGRA_UARTA_BASE,
170 TEGRA_UARTB_BASE,
171 TEGRA_UARTC_BASE,
172 TEGRA_UARTD_BASE,
173 TEGRA_UARTE_BASE,
174 TEGRA_UARTF_BASE,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800175 TEGRA_UARTG_BASE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700176};
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700177#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700178
179/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700180 * Enable console corresponding to the console ID
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700181 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700182void plat_enable_console(int32_t id)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700183{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700184 uint32_t console_clock = 0U;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700185
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700186#if ENABLE_CONSOLE_SPE
Andre Przywaraabe890f2020-01-25 00:58:35 +0000187 static console_t spe_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700188
189 if (id == TEGRA_CONSOLE_SPE_ID) {
190 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
191 console_clock,
192 TEGRA_CONSOLE_BAUDRATE,
193 &spe_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000194 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700195 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800196 }
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700197#else
Andre Przywara98b5a112020-01-25 00:58:35 +0000198 static console_t uart_console;
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800199
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700200 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
201 /*
202 * Reference clock used by the FPGAs is a lot slower.
203 */
204 if (tegra_platform_is_fpga()) {
205 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
206 } else {
207 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
208 }
209
210 (void)console_16550_register(tegra194_uart_addresses[id],
211 console_clock,
212 TEGRA_CONSOLE_BAUDRATE,
213 &uart_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000214 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700215 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
216 }
217#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700218}
219
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700220/*******************************************************************************
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -0700221 * Verify SCR settings
222 ******************************************************************************/
223static inline bool tegra194_is_scr_valid(void)
224{
225 uint32_t scr_val;
226 bool ret = true;
227
228 for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
229 scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
230 if (scr_val != t194_scr_settings[i].scr_val) {
231 ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
232 ret = false;
233 }
234 }
235 return ret;
236}
237
238/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700239 * Handler for early platform setup
240 ******************************************************************************/
241void plat_early_platform_setup(void)
242{
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700243 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
244 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
245 uint64_t actlr_elx;
246
kalyanic0a2cc612019-09-13 14:49:39 -0700247 /* Verify chip id is t194 */
248 assert(tegra_chipid_is_t194());
249
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -0700250 /* Verify SCR settings */
251 if (tegra_platform_is_silicon()) {
252 assert(tegra194_is_scr_valid());
253 }
254
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700255 /* sanity check MCE firmware compatibility */
256 mce_verify_firmware_version();
257
David Pu70f65972019-03-18 15:14:49 -0700258#if RAS_EXTENSION
259 /* Enable Uncorrectable RAS error */
260 tegra194_ras_enable();
261#endif
262
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800263 /*
264 * Program XUSB STREAMIDs
265 * ======================
266 * T19x XUSB has support for XUSB virtualization. It will have one
Ajay Gupta81621092017-08-01 15:53:04 -0700267 * physical function (PF) and four Virtual function (VF)
268 *
269 * There were below two SIDs for XUSB until T186.
270 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
271 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
272 *
273 * We have below four new SIDs added for VF(s)
274 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
275 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
276 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
277 * 6) #define TEGRA_SID_XUSB_VF3 0x60U
278 *
279 * When virtualization is enabled then we have to disable SID override
280 * and program above SIDs in below newly added SID registers in XUSB
281 * PADCTL MMIO space. These registers are TZ protected and so need to
282 * be done in ATF.
283 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
284 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
285 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
286 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
287 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
288 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
289 *
290 * This change disables SID override and programs XUSB SIDs in
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800291 * above registers to support both virtualization and
292 * non-virtualization platforms
Ajay Gupta81621092017-08-01 15:53:04 -0700293 */
Varun Wadekara2eb6632018-03-23 10:44:40 -0700294 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
295
296 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
297 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
298 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
299 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
300 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
301 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
302 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
303 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
304 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
305 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
306 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
307 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
308 }
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700309
310 /*
311 * Enable dual execution optimized translations for all ELx.
312 */
313 if (enable_ccplex_lock_step != 0U) {
314 actlr_elx = read_actlr_el3();
315 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
316 write_actlr_el3(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800317 /* check if the bit is actually set */
318 assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700319
320 actlr_elx = read_actlr_el2();
321 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
322 write_actlr_el2(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800323 /* check if the bit is actually set */
324 assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700325
326 actlr_elx = read_actlr_el1();
327 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
328 write_actlr_el1(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800329 /* check if the bit is actually set */
330 assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700331 }
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700332}
333
Varun Wadekar362a6b22017-11-10 11:04:42 -0800334/* Secure IRQs for Tegra194 */
335static const interrupt_prop_t tegra194_interrupt_props[] = {
Varun Wadekarbef02f02020-04-17 19:09:21 -0700336 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
337 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700338 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar362a6b22017-11-10 11:04:42 -0800339 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700340};
341
342/*******************************************************************************
343 * Initialize the GIC and SGIs
344 ******************************************************************************/
345void plat_gic_setup(void)
346{
Varun Wadekar362a6b22017-11-10 11:04:42 -0800347 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
348 tegra_gic_init();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700349
350 /*
Varun Wadekar362a6b22017-11-10 11:04:42 -0800351 * Initialize the FIQ handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700352 */
Varun Wadekar362a6b22017-11-10 11:04:42 -0800353 tegra_fiq_handler_setup();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700354}
355
356/*******************************************************************************
357 * Return pointer to the BL31 params from previous bootloader
358 ******************************************************************************/
359struct tegra_bl31_params *plat_get_bl31_params(void)
360{
Steven Kao08ac2732018-02-09 21:35:20 +0800361 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700362
Steven Kao08ac2732018-02-09 21:35:20 +0800363 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
364 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
365 val <<= 32;
366 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700367
368 return (struct tegra_bl31_params *)(uintptr_t)val;
369}
370
371/*******************************************************************************
372 * Return pointer to the BL31 platform params from previous bootloader
373 ******************************************************************************/
374plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
375{
Steven Kao08ac2732018-02-09 21:35:20 +0800376 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700377
Steven Kao08ac2732018-02-09 21:35:20 +0800378 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
379 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
380 val <<= 32;
381 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700382
383 return (plat_params_from_bl2_t *)(uintptr_t)val;
384}
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800385
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700386/*******************************************************************************
387 * Handler for late platform setup
388 ******************************************************************************/
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800389void plat_late_platform_setup(void)
390{
Steven Kao8f4f1022017-12-13 06:39:15 +0800391#if ENABLE_STRICT_CHECKING_MODE
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800392 /*
393 * Enable strict checking after programming the GSC for
394 * enabling TZSRAM and TZDRAM
395 */
396 mce_enable_strict_checking();
Steven Kao8f4f1022017-12-13 06:39:15 +0800397#endif
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800398}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700399
400/*******************************************************************************
401 * Handler to indicate support for System Suspend
402 ******************************************************************************/
403bool plat_supports_system_suspend(void)
404{
405 return true;
406}