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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM Trusted Firmware Design
2===========================
3
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10The ARM Trusted Firmware implements a subset of the Trusted Board Boot
Douglas Raillard30d7b362017-06-28 16:14:55 +010011Requirements (TBBR) Platform Design Document (PDD) [1]_ for ARM reference
Douglas Raillardd7c21b72017-06-28 15:23:03 +010012platforms. The TBB sequence starts when the platform is powered on and runs up
13to the stage where it hands-off control to firmware running in the normal
14world in DRAM. This is the cold boot path.
15
16The ARM Trusted Firmware also implements the Power State Coordination Interface
Douglas Raillard30d7b362017-06-28 16:14:55 +010017PDD [2]_ as a runtime service. PSCI is the interface from normal world software
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018to firmware implementing power management use-cases (for example, secondary CPU
19boot, hotplug and idle). Normal world software can access ARM Trusted Firmware
20runtime services via the ARM SMC (Secure Monitor Call) instruction. The SMC
Douglas Raillard30d7b362017-06-28 16:14:55 +010021instruction must be used as mandated by the SMC Calling Convention [3]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
23The ARM Trusted Firmware implements a framework for configuring and managing
24interrupts generated in either security state. The details of the interrupt
25management framework and its design can be found in ARM Trusted Firmware
Douglas Raillard30d7b362017-06-28 16:14:55 +010026Interrupt Management Design guide [4]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010027
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010028The ARM Trusted Firmware also implements a library for setting up and managing
29the translation tables. The details of this library can be found in
30`Xlat_tables design`_.
31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010032The ARM Trusted Firmware can be built to support either AArch64 or AArch32
33execution state.
34
35Cold boot
36---------
37
38The cold boot path starts when the platform is physically turned on. If
39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
41CPU is chosen through platform-specific means. The cold boot path is mainly
42executed by the primary CPU, other than essential CPU initialization executed by
43all CPUs. The secondary CPUs are kept in a safe platform-specific state until
44the primary CPU has performed enough initialization to boot them.
45
46Refer to the `Reset Design`_ for more information on the effect of the
47``COLD_BOOT_SINGLE_CPU`` platform build option.
48
49The cold boot path in this implementation of the ARM Trusted Firmware,
50depends on the execution state.
51For AArch64, it is divided into five steps (in order of execution):
52
53- Boot Loader stage 1 (BL1) *AP Trusted ROM*
54- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
55- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
56- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
58
59For AArch32, it is divided into four steps (in order of execution):
60
61- Boot Loader stage 1 (BL1) *AP Trusted ROM*
62- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
63- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
64- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
65
66ARM development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
67combination of the following types of memory regions. Each bootloader stage uses
68one or more of these memory regions.
69
70- Regions accessible from both non-secure and secure states. For example,
71 non-trusted SRAM, ROM and DRAM.
72- Regions accessible from only the secure state. For example, trusted SRAM and
73 ROM. The FVPs also implement the trusted DRAM which is statically
74 configured. Additionally, the Base FVPs and Juno development platform
75 configure the TrustZone Controller (TZC) to create a region in the DRAM
76 which is accessible only from the secure state.
77
78The sections below provide the following details:
79
80- initialization and execution of the first three stages during cold boot
81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
82 AArch32) entrypoint requirements for use by alternative Trusted Boot
83 Firmware in place of the provided BL1 and BL2
84
85BL1
86~~~
87
88This stage begins execution from the platform's reset vector at EL3. The reset
89address is platform dependent but it is usually located in a Trusted ROM area.
90The BL1 data section is copied to trusted SRAM at runtime.
91
92On the ARM development platforms, BL1 code starts execution from the reset
93vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
94to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
95
96The functionality implemented by this stage is as follows.
97
98Determination of boot path
99^^^^^^^^^^^^^^^^^^^^^^^^^^
100
101Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
102boot and a cold boot. This is done using platform-specific mechanisms (see the
103``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a
104warm boot, a CPU is expected to continue execution from a separate
105entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
106platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
107the `Porting Guide`_) while the primary CPU executes the remaining cold boot path
108as described in the following sections.
109
110This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
111`Reset Design`_ for more information on the effect of the
112``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
113
114Architectural initialization
115^^^^^^^^^^^^^^^^^^^^^^^^^^^^
116
117BL1 performs minimal architectural initialization as follows.
118
119- Exception vectors
120
121 BL1 sets up simple exception vectors for both synchronous and asynchronous
122 exceptions. The default behavior upon receiving an exception is to populate
123 a status code in the general purpose register ``X0/R0`` and call the
124 ``plat_report_exception()`` function (see the `Porting Guide`_). The status
125 code is one of:
126
127 For AArch64:
128
129 ::
130
131 0x0 : Synchronous exception from Current EL with SP_EL0
132 0x1 : IRQ exception from Current EL with SP_EL0
133 0x2 : FIQ exception from Current EL with SP_EL0
134 0x3 : System Error exception from Current EL with SP_EL0
135 0x4 : Synchronous exception from Current EL with SP_ELx
136 0x5 : IRQ exception from Current EL with SP_ELx
137 0x6 : FIQ exception from Current EL with SP_ELx
138 0x7 : System Error exception from Current EL with SP_ELx
139 0x8 : Synchronous exception from Lower EL using aarch64
140 0x9 : IRQ exception from Lower EL using aarch64
141 0xa : FIQ exception from Lower EL using aarch64
142 0xb : System Error exception from Lower EL using aarch64
143 0xc : Synchronous exception from Lower EL using aarch32
144 0xd : IRQ exception from Lower EL using aarch32
145 0xe : FIQ exception from Lower EL using aarch32
146 0xf : System Error exception from Lower EL using aarch32
147
148 For AArch32:
149
150 ::
151
152 0x10 : User mode
153 0x11 : FIQ mode
154 0x12 : IRQ mode
155 0x13 : SVC mode
156 0x16 : Monitor mode
157 0x17 : Abort mode
158 0x1a : Hypervisor mode
159 0x1b : Undefined mode
160 0x1f : System mode
161
162 The ``plat_report_exception()`` implementation on the ARM FVP port programs
163 the Versatile Express System LED register in the following format to
164 indicate the occurence of an unexpected exception:
165
166 ::
167
168 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
169 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
170 For AArch32 it is always 0x0
171 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
172 of the status code
173
174 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
175 CLCD window of the FVP.
176
177 BL1 does not expect to receive any exceptions other than the SMC exception.
178 For the latter, BL1 installs a simple stub. The stub expects to receive a
179 limited set of SMC types (determined by their function IDs in the general
180 purpose register ``X0/R0``):
181
182 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
183 to EL3 Runtime Software.
184 - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_
185 Design Guide are supported for AArch64 only. These SMCs are currently
186 not supported when BL1 is built for AArch32.
187
188 Any other SMC leads to an assertion failure.
189
190- CPU initialization
191
192 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
193 specific reset handler function (see the section: "CPU specific operations
194 framework").
195
196- Control register setup (for AArch64)
197
198 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
199 bit. Alignment and stack alignment checking is enabled by setting the
200 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
201 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
202
203 - ``SCR_EL3``. The register width of the next lower exception level is set
204 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
205 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
206 also set to disable instruction fetches from Non-secure memory when in
207 secure state.
208
209 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
210 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
211 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
212 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
213 Instructions that access the registers associated with Floating Point
214 and Advanced SIMD execution are configured to not trap to EL3 by
215 clearing the ``CPTR_EL3.TFP`` bit.
216
217 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
218 mask bit.
219
220 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
221 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
222 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
223 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
224 disable AArch32 Secure self-hosted privileged debug from S-EL1.
225
226- Control register setup (for AArch32)
227
228 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
229 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
230 Exception endianness is set to little-endian by clearing the
231 ``SCTLR.EE`` bit.
232
233 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
234 Non-secure memory when in secure state.
235
236 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
237 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
238 is configured not to trap to undefined mode by clearing the
239 ``CPACR.TRCDIS`` bit.
240
241 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
242 system register access to implemented trace registers.
243
244 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
245 functionality from all Exception levels.
246
247 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
248 the Asynchronous data abort interrupt mask bit.
249
250 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
251 self-hosted privileged debug.
252
253Platform initialization
254^^^^^^^^^^^^^^^^^^^^^^^
255
256On ARM platforms, BL1 performs the following platform initializations:
257
258- Enable the Trusted Watchdog.
259- Initialize the console.
260- Configure the Interconnect to enable hardware coherency.
261- Enable the MMU and map the memory it needs to access.
262- Configure any required platform storage to load the next bootloader image
263 (BL2).
264
265Firmware Update detection and execution
266^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
267
268After performing platform setup, BL1 common code calls
269``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or
270to proceed with the normal boot process. If the platform code returns
271``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the
272next section, else BL1 assumes that `Firmware Update`_ is required and execution
273passes to the first image in the `Firmware Update`_ process. In either case, BL1
274retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``.
275The image descriptor contains an ``entry_point_info_t`` structure, which BL1
276uses to initialize the execution state of the next image.
277
278BL2 image load and execution
279^^^^^^^^^^^^^^^^^^^^^^^^^^^^
280
281In the normal boot flow, BL1 execution continues as follows:
282
283#. BL1 prints the following string from the primary CPU to indicate successful
284 execution of the BL1 stage:
285
286 ::
287
288 "Booting Trusted Firmware"
289
290#. BL1 determines the amount of free trusted SRAM memory available by
291 calculating the extent of its own data section, which also resides in
292 trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a
293 platform-specific base address. If the BL2 image file is not present or if
294 there is not enough free trusted SRAM the following error message is
295 printed:
296
297 ::
298
299 "Failed to load BL2 firmware."
300
301 BL1 calculates the amount of Trusted SRAM that can be used by the BL2
302 image. The exact load location of the image is provided as a base address
303 in the platform header. Further description of the memory layout can be
304 found later in this document.
305
306#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
307 Secure SVC mode (for AArch32), starting from its load address.
308
309#. BL1 also passes information about the amount of trusted SRAM used and
310 available for use. This information is populated at a platform-specific
311 memory address.
312
313BL2
314~~~
315
316BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
317SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
318base address (more information can be found later in this document).
319The functionality implemented by BL2 is as follows.
320
321Architectural initialization
322^^^^^^^^^^^^^^^^^^^^^^^^^^^^
323
324For AArch64, BL2 performs the minimal architectural initialization required
325for subsequent stages of the ARM Trusted Firmware and normal world software.
326EL1 and EL0 are given access to Floating Point and Advanced SIMD registers
327by clearing the ``CPACR.FPEN`` bits.
328
329For AArch32, the minimal architectural initialization required for subsequent
330stages of the ARM Trusted Firmware and normal world software is taken care of
331in BL1 as both BL1 and BL2 execute at PL1.
332
333Platform initialization
334^^^^^^^^^^^^^^^^^^^^^^^
335
336On ARM platforms, BL2 performs the following platform initializations:
337
338- Initialize the console.
339- Configure any required platform storage to allow loading further bootloader
340 images.
341- Enable the MMU and map the memory it needs to access.
342- Perform platform security setup to allow access to controlled components.
343- Reserve some memory for passing information to the next bootloader image
344 EL3 Runtime Software and populate it.
345- Define the extents of memory available for loading each subsequent
346 bootloader image.
347
348Image loading in BL2
349^^^^^^^^^^^^^^^^^^^^
350
351Image loading scheme in BL2 depends on ``LOAD_IMAGE_V2`` build option. If the
352flag is disabled, the BLxx images are loaded, by calling the respective
353load\_blxx() function from BL2 generic code. If the flag is enabled, the BL2
354generic code loads the images based on the list of loadable images provided
355by the platform. BL2 passes the list of executable images provided by the
356platform to the next handover BL image. By default, this flag is disabled for
357AArch64 and the AArch32 build is supported only if this flag is enabled.
358
359SCP\_BL2 (System Control Processor Firmware) image load
360^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
361
362Some systems have a separate System Control Processor (SCP) for power, clock,
363reset and system control. BL2 loads the optional SCP\_BL2 image from platform
364storage into a platform-specific region of secure memory. The subsequent
365handling of SCP\_BL2 is platform specific. For example, on the Juno ARM
366development platform port the image is transferred into SCP's internal memory
367using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
368memory. The SCP executes SCP\_BL2 and signals to the Application Processor (AP)
369for BL2 execution to continue.
370
371EL3 Runtime Software image load
372^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
373
374BL2 loads the EL3 Runtime Software image from platform storage into a platform-
375specific address in trusted SRAM. If there is not enough memory to load the
376image or image is missing it leads to an assertion failure. If ``LOAD_IMAGE_V2``
377is disabled and if image loads successfully, BL2 updates the amount of trusted
378SRAM used and available for use by EL3 Runtime Software. This information is
379populated at a platform-specific memory address.
380
381AArch64 BL32 (Secure-EL1 Payload) image load
382^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
383
384BL2 loads the optional BL32 image from platform storage into a platform-
385specific region of secure memory. The image executes in the secure world. BL2
386relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
387populates a platform-specific area of memory with the entrypoint/load-address
388of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
389for entry into BL32 is not determined by BL2, it is initialized by the
390Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
391managing interaction with BL32. This information is passed to BL31.
392
393BL33 (Non-trusted Firmware) image load
394^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
395
396BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
397platform storage into non-secure memory as defined by the platform.
398
399BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
400initialization is complete. Hence, BL2 populates a platform-specific area of
401memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
402normal world software image. The entrypoint is the load address of the BL33
403image. The ``SPSR`` is determined as specified in Section 5.13 of the
404`PSCI PDD`_. This information is passed to the EL3 Runtime Software.
405
406AArch64 BL31 (EL3 Runtime Software) execution
407^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
408
409BL2 execution continues as follows:
410
411#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
412 BL31 entrypoint. The exception is handled by the SMC exception handler
413 installed by BL1.
414
415#. BL1 turns off the MMU and flushes the caches. It clears the
416 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
417 and invalidates the TLBs.
418
419#. BL1 passes control to BL31 at the specified entrypoint at EL3.
420
421AArch64 BL31
422~~~~~~~~~~~~
423
424The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
425EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
426loaded at a platform-specific base address (more information can be found later
427in this document). The functionality implemented by BL31 is as follows.
428
429Architectural initialization
430^^^^^^^^^^^^^^^^^^^^^^^^^^^^
431
432Currently, BL31 performs a similar architectural initialization to BL1 as
433far as system register settings are concerned. Since BL1 code resides in ROM,
434architectural initialization in BL31 allows override of any previous
435initialization done by BL1.
436
437BL31 initializes the per-CPU data framework, which provides a cache of
438frequently accessed per-CPU data optimised for fast, concurrent manipulation
439on different CPUs. This buffer includes pointers to per-CPU contexts, crash
440buffer, CPU reset and power down operations, PSCI data, platform data and so on.
441
442It then replaces the exception vectors populated by BL1 with its own. BL31
443exception vectors implement more elaborate support for handling SMCs since this
444is the only mechanism to access the runtime services implemented by BL31 (PSCI
445for example). BL31 checks each SMC for validity as specified by the
446`SMC calling convention PDD`_ before passing control to the required SMC
447handler routine.
448
449BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
450counter, which is provided by the platform.
451
452Platform initialization
453^^^^^^^^^^^^^^^^^^^^^^^
454
455BL31 performs detailed platform initialization, which enables normal world
456software to function correctly.
457
458On ARM platforms, this consists of the following:
459
460- Initialize the console.
461- Configure the Interconnect to enable hardware coherency.
462- Enable the MMU and map the memory it needs to access.
463- Initialize the generic interrupt controller.
464- Initialize the power controller device.
465- Detect the system topology.
466
467Runtime services initialization
468^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
469
470BL31 is responsible for initializing the runtime services. One of them is PSCI.
471
472As part of the PSCI initializations, BL31 detects the system topology. It also
473initializes the data structures that implement the state machine used to track
474the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
475``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
476that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
477initializes the locks that protect them. BL31 accesses the state of a CPU or
478cluster immediately after reset and before the data cache is enabled in the
479warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
480therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
481
482The runtime service framework and its initialization is described in more
483detail in the "EL3 runtime services framework" section below.
484
485Details about the status of the PSCI implementation are provided in the
486"Power State Coordination Interface" section below.
487
488AArch64 BL32 (Secure-EL1 Payload) image initialization
489^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
490
491If a BL32 image is present then there must be a matching Secure-EL1 Payload
492Dispatcher (SPD) service (see later for details). During initialization
493that service must register a function to carry out initialization of BL32
494once the runtime services are fully initialized. BL31 invokes such a
495registered function to initialize BL32 before running BL33. This initialization
496is not necessary for AArch32 SPs.
497
498Details on BL32 initialization and the SPD's role are described in the
499"Secure-EL1 Payloads and Dispatchers" section below.
500
501BL33 (Non-trusted Firmware) execution
502^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
503
504EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
505world cold boot, ensuring that no secure state information finds its way into
506the non-secure execution state. EL3 Runtime Software uses the entrypoint
507information provided by BL2 to jump to the Non-trusted firmware image (BL33)
508at the highest available Exception Level (EL2 if available, otherwise EL1).
509
510Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
511~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
512
513Some platforms have existing implementations of Trusted Boot Firmware that
514would like to use ARM Trusted Firmware BL31 for the EL3 Runtime Software. To
515enable this firmware architecture it is important to provide a fully documented
516and stable interface between the Trusted Boot Firmware and BL31.
517
518Future changes to the BL31 interface will be done in a backwards compatible
519way, and this enables these firmware components to be independently enhanced/
520updated to develop and exploit new functionality.
521
522Required CPU state when calling ``bl31_entrypoint()`` during cold boot
523^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
524
525This function must only be called by the primary CPU.
526
527On entry to this function the calling primary CPU must be executing in AArch64
528EL3, little-endian data access, and all interrupt sources masked:
529
530::
531
532 PSTATE.EL = 3
533 PSTATE.RW = 1
534 PSTATE.DAIF = 0xf
535 SCTLR_EL3.EE = 0
536
537X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
538platform code in BL31:
539
540::
541
542 X0 : Reserved for common Trusted Firmware information
543 X1 : Platform specific information
544
545BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
546these will be zero filled prior to invoking platform setup code.
547
548Use of the X0 and X1 parameters
549'''''''''''''''''''''''''''''''
550
551The parameters are platform specific and passed from ``bl31_entrypoint()`` to
552``bl31_early_platform_setup()``. The value of these parameters is never directly
553used by the common BL31 code.
554
555The convention is that ``X0`` conveys information regarding the BL31, BL32 and
556BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
557platform specific purpose. This convention allows platforms which use ARM
558Trusted Firmware's BL1 and BL2 images to transfer additional platform specific
559information from Secure Boot without conflicting with future evolution of the
560Trusted Firmware using ``X0`` to pass a ``bl31_params`` structure.
561
562BL31 common and SPD initialization code depends on image and entrypoint
563information about BL33 and BL32, which is provided via BL31 platform APIs.
564This information is required until the start of execution of BL33. This
565information can be provided in a platform defined manner, e.g. compiled into
566the platform code in BL31, or provided in a platform defined memory location
567by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
568Cold boot Initialization parameters. This data may need to be cleaned out of
569the CPU caches if it is provided by an earlier boot stage and then accessed by
570BL31 platform code before the caches are enabled.
571
572ARM Trusted Firmware's BL2 implementation passes a ``bl31_params`` structure in
573``X0`` and the ARM development platforms interpret this in the BL31 platform
574code.
575
576MMU, Data caches & Coherency
577''''''''''''''''''''''''''''
578
579BL31 does not depend on the enabled state of the MMU, data caches or
580interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
581on entry, these should be enabled during ``bl31_plat_arch_setup()``.
582
583Data structures used in the BL31 cold boot interface
584''''''''''''''''''''''''''''''''''''''''''''''''''''
585
586These structures are designed to support compatibility and independent
587evolution of the structures and the firmware images. For example, a version of
588BL31 that can interpret the BL3x image information from different versions of
589BL2, a platform that uses an extended entry\_point\_info structure to convey
590additional register information to BL31, or a ELF image loader that can convey
591more details about the firmware images.
592
593To support these scenarios the structures are versioned and sized, which enables
594BL31 to detect which information is present and respond appropriately. The
595``param_header`` is defined to capture this information:
596
597.. code:: c
598
599 typedef struct param_header {
600 uint8_t type; /* type of the structure */
601 uint8_t version; /* version of this structure */
602 uint16_t size; /* size of this structure in bytes */
603 uint32_t attr; /* attributes: unused bits SBZ */
604 } param_header_t;
605
606The structures using this format are ``entry_point_info``, ``image_info`` and
607``bl31_params``. The code that allocates and populates these structures must set
608the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
609to simplify this action.
610
611Required CPU state for BL31 Warm boot initialization
612^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
613
614When requesting a CPU power-on, or suspending a running CPU, ARM Trusted
615Firmware provides the platform power management code with a Warm boot
616initialization entry-point, to be invoked by the CPU immediately after the
617reset handler. On entry to the Warm boot initialization function the calling
618CPU must be in AArch64 EL3, little-endian data access and all interrupt sources
619masked:
620
621::
622
623 PSTATE.EL = 3
624 PSTATE.RW = 1
625 PSTATE.DAIF = 0xf
626 SCTLR_EL3.EE = 0
627
628The PSCI implementation will initialize the processor state and ensure that the
629platform power management code is then invoked as required to initialize all
630necessary system, cluster and CPU resources.
631
632AArch32 EL3 Runtime Software entrypoint interface
633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
634
635To enable this firmware architecture it is important to provide a fully
636documented and stable interface between the Trusted Boot Firmware and the
637AArch32 EL3 Runtime Software.
638
639Future changes to the entrypoint interface will be done in a backwards
640compatible way, and this enables these firmware components to be independently
641enhanced/updated to develop and exploit new functionality.
642
643Required CPU state when entering during cold boot
644^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
645
646This function must only be called by the primary CPU.
647
648On entry to this function the calling primary CPU must be executing in AArch32
649EL3, little-endian data access, and all interrupt sources masked:
650
651::
652
653 PSTATE.AIF = 0x7
654 SCTLR.EE = 0
655
656R0 and R1 are used to pass information from the Trusted Boot Firmware to the
657platform code in AArch32 EL3 Runtime Software:
658
659::
660
661 R0 : Reserved for common Trusted Firmware information
662 R1 : Platform specific information
663
664Use of the R0 and R1 parameters
665'''''''''''''''''''''''''''''''
666
667The parameters are platform specific and the convention is that ``R0`` conveys
668information regarding the BL3x images from the Trusted Boot firmware and ``R1``
669can be used for other platform specific purpose. This convention allows
670platforms which use ARM Trusted Firmware's BL1 and BL2 images to transfer
671additional platform specific information from Secure Boot without conflicting
672with future evolution of the Trusted Firmware using ``R0`` to pass a ``bl_params``
673structure.
674
675The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
676information can be obtained in a platform defined manner, e.g. compiled into
677the AArch32 EL3 Runtime Software, or provided in a platform defined memory
678location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
679via the Cold boot Initialization parameters. This data may need to be cleaned
680out of the CPU caches if it is provided by an earlier boot stage and then
681accessed by AArch32 EL3 Runtime Software before the caches are enabled.
682
683When using AArch32 EL3 Runtime Software, the ARM development platforms pass a
684``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
685Software platform code.
686
687MMU, Data caches & Coherency
688''''''''''''''''''''''''''''
689
690AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
691data caches or interconnect coherency in its entrypoint. They must be explicitly
692enabled if required.
693
694Data structures used in cold boot interface
695'''''''''''''''''''''''''''''''''''''''''''
696
697The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
698of ``bl31_params``. The ``bl_params`` structure is based on the convention
699described in AArch64 BL31 cold boot interface section.
700
701Required CPU state for warm boot initialization
702^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
703
704When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
705Runtime Software must ensure execution of a warm boot initialization entrypoint.
706If ARM Trusted Firmware BL1 is used and the PROGRAMMABLE\_RESET\_ADDRESS build
707flag is false, then AArch32 EL3 Runtime Software must ensure that BL1 branches
708to the warm boot entrypoint by arranging for the BL1 platform function,
709plat\_get\_my\_entrypoint(), to return a non-zero value.
710
711In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
712data access and all interrupt sources masked:
713
714::
715
716 PSTATE.AIF = 0x7
717 SCTLR.EE = 0
718
719The warm boot entrypoint may be implemented by using the ARM Trusted Firmware
720``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
721the pre-requisites mentioned in the `PSCI Library integration guide`_.
722
723EL3 runtime services framework
724------------------------------
725
726Software executing in the non-secure state and in the secure state at exception
727levels lower than EL3 will request runtime services using the Secure Monitor
728Call (SMC) instruction. These requests will follow the convention described in
729the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
730identifiers to each SMC request and describes how arguments are passed and
731returned.
732
733The EL3 runtime services framework enables the development of services by
734different providers that can be easily integrated into final product firmware.
735The following sections describe the framework which facilitates the
736registration, initialization and use of runtime services in EL3 Runtime
737Software (BL31).
738
739The design of the runtime services depends heavily on the concepts and
740definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
741Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
742conventions. Please refer to that document for more detailed explanation of
743these terms.
744
745The following runtime services are expected to be implemented first. They have
746not all been instantiated in the current implementation.
747
748#. Standard service calls
749
750 This service is for management of the entire system. The Power State
751 Coordination Interface (`PSCI`_) is the first set of standard service calls
752 defined by ARM (see PSCI section later).
753
754#. Secure-EL1 Payload Dispatcher service
755
756 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
757 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
758 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
759 The Secure Monitor will make these world switches in response to SMCs. The
760 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
761 Application Call OEN ranges.
762
763 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
764 not defined by the `SMCCC`_ or any other standard. As a result, each
765 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
766 service - within ARM Trusted Firmware this service is referred to as the
767 Secure-EL1 Payload Dispatcher (SPD).
768
769 ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and its
770 associated Dispatcher (TSPD). Details of SPD design and TSP/TSPD operation
771 are described in the "Secure-EL1 Payloads and Dispatchers" section below.
772
773#. CPU implementation service
774
775 This service will provide an interface to CPU implementation specific
776 services for a given platform e.g. access to processor errata workarounds.
777 This service is currently unimplemented.
778
779Additional services for ARM Architecture, SiP and OEM calls can be implemented.
780Each implemented service handles a range of SMC function identifiers as
781described in the `SMCCC`_.
782
783Registration
784~~~~~~~~~~~~
785
786A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
787the name of the service, the range of OENs covered, the type of service and
788initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
789This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
790the framework to find all service descriptors included into BL31.
791
792The specific service for a SMC Function is selected based on the OEN and call
793type of the Function ID, and the framework uses that information in the service
794descriptor to identify the handler for the SMC Call.
795
796The service descriptors do not include information to identify the precise set
797of SMC function identifiers supported by this service implementation, the
798security state from which such calls are valid nor the capability to support
79964-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
800to these aspects of a SMC call is the responsibility of the service
801implementation, the framework is focused on integration of services from
802different providers and minimizing the time taken by the framework before the
803service handler is invoked.
804
805Details of the parameters, requirements and behavior of the initialization and
806call handling functions are provided in the following sections.
807
808Initialization
809~~~~~~~~~~~~~~
810
811``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
812framework running on the primary CPU during cold boot as part of the BL31
813initialization. This happens prior to initializing a Trusted OS and running
814Normal world boot firmware that might in turn use these services.
815Initialization involves validating each of the declared runtime service
816descriptors, calling the service initialization function and populating the
817index used for runtime lookup of the service.
818
819The BL31 linker script collects all of the declared service descriptors into a
820single array and defines symbols that allow the framework to locate and traverse
821the array, and determine its size.
822
823The framework does basic validation of each descriptor to halt firmware
824initialization if service declaration errors are detected. The framework does
825not check descriptors for the following error conditions, and may behave in an
826unpredictable manner under such scenarios:
827
828#. Overlapping OEN ranges
829#. Multiple descriptors for the same range of OENs and ``call_type``
830#. Incorrect range of owning entity numbers for a given ``call_type``
831
832Once validated, the service ``init()`` callback is invoked. This function carries
833out any essential EL3 initialization before servicing requests. The ``init()``
834function is only invoked on the primary CPU during cold boot. If the service
835uses per-CPU data this must either be initialized for all CPUs during this call,
836or be done lazily when a CPU first issues an SMC call to that service. If
837``init()`` returns anything other than ``0``, this is treated as an initialization
838error and the service is ignored: this does not cause the firmware to halt.
839
840The OEN and call type fields present in the SMC Function ID cover a total of
841128 distinct services, but in practice a single descriptor can cover a range of
842OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
843service handler, the framework uses an array of 128 indices that map every
844distinct OEN/call-type combination either to one of the declared services or to
845indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
846populated for all of the OENs covered by a service after the service ``init()``
847function has reported success. So a service that fails to initialize will never
848have it's ``handle()`` function invoked.
849
850The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
851Function ID call type and OEN onto a specific service handler in the
852``rt_svc_descs[]`` array.
853
854|Image 1|
855
856Handling an SMC
857~~~~~~~~~~~~~~~
858
859When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
860Function ID is passed in W0 from the lower exception level (as per the
861`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
862SMC Function which indicates the SMC64 calling convention: such calls are
863ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
864in R0/X0.
865
866Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
867Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
868resulting value might indicate a service that has no handler, in this case the
869framework will also report an Unknown SMC Function ID. Otherwise, the value is
870used as a further index into the ``rt_svc_descs[]`` array to locate the required
871service and handler.
872
873The service's ``handle()`` callback is provided with five of the SMC parameters
874directly, the others are saved into memory for retrieval (if needed) by the
875handler. The handler is also provided with an opaque ``handle`` for use with the
876supporting library for parameter retrieval, setting return values and context
877manipulation; and with ``flags`` indicating the security state of the caller. The
878framework finally sets up the execution stack for the handler, and invokes the
879services ``handle()`` function.
880
881On return from the handler the result registers are populated in X0-X3 before
882restoring the stack and CPU state and returning from the original SMC.
883
884Power State Coordination Interface
885----------------------------------
886
887TODO: Provide design walkthrough of PSCI implementation.
888
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100889The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
890mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100891`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100892the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100893
894An API implementation might have a dependency on platform code e.g. CPU\_SUSPEND
895requires the platform to export a part of the implementation. Hence the level
896of support of the mandatory APIs depends upon the support exported by the
897platform port as well. The Juno and FVP (all variants) platforms export all the
898required support.
899
900+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100901| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100902+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100903| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100904+-----------------------------+-------------+-------------------------------+
905| ``CPU_SUSPEND`` | Yes\* | |
906+-----------------------------+-------------+-------------------------------+
907| ``CPU_OFF`` | Yes\* | |
908+-----------------------------+-------------+-------------------------------+
909| ``CPU_ON`` | Yes\* | |
910+-----------------------------+-------------+-------------------------------+
911| ``AFFINITY_INFO`` | Yes | |
912+-----------------------------+-------------+-------------------------------+
913| ``MIGRATE`` | Yes\*\* | |
914+-----------------------------+-------------+-------------------------------+
915| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
916+-----------------------------+-------------+-------------------------------+
917| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
918+-----------------------------+-------------+-------------------------------+
919| ``SYSTEM_OFF`` | Yes\* | |
920+-----------------------------+-------------+-------------------------------+
921| ``SYSTEM_RESET`` | Yes\* | |
922+-----------------------------+-------------+-------------------------------+
923| ``PSCI_FEATURES`` | Yes | |
924+-----------------------------+-------------+-------------------------------+
925| ``CPU_FREEZE`` | No | |
926+-----------------------------+-------------+-------------------------------+
927| ``CPU_DEFAULT_SUSPEND`` | No | |
928+-----------------------------+-------------+-------------------------------+
929| ``NODE_HW_STATE`` | Yes\* | |
930+-----------------------------+-------------+-------------------------------+
931| ``SYSTEM_SUSPEND`` | Yes\* | |
932+-----------------------------+-------------+-------------------------------+
933| ``PSCI_SET_SUSPEND_MODE`` | No | |
934+-----------------------------+-------------+-------------------------------+
935| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
936+-----------------------------+-------------+-------------------------------+
937| ``PSCI_STAT_COUNT`` | Yes\* | |
938+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100939| ``SYSTEM_RESET2`` | Yes\* | |
940+-----------------------------+-------------+-------------------------------+
941| ``MEM_PROTECT`` | Yes\* | |
942+-----------------------------+-------------+-------------------------------+
943| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
944+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100945
946\*Note : These PSCI APIs require platform power management hooks to be
947registered with the generic PSCI code to be supported.
948
949\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
950hooks to be registered with the generic PSCI code to be supported.
951
952The PSCI implementation in ARM Trusted Firmware is a library which can be
953integrated with AArch64 or AArch32 EL3 Runtime Software for ARMv8-A systems.
954A guide to integrating PSCI library with AArch32 EL3 Runtime Software
955can be found `here`_.
956
957Secure-EL1 Payloads and Dispatchers
958-----------------------------------
959
960On a production system that includes a Trusted OS running in Secure-EL1/EL0,
961the Trusted OS is coupled with a companion runtime service in the BL31
962firmware. This service is responsible for the initialisation of the Trusted
963OS and all communications with it. The Trusted OS is the BL32 stage of the
964boot flow in ARM Trusted Firmware. The firmware will attempt to locate, load
965and execute a BL32 image.
966
967ARM Trusted Firmware uses a more general term for the BL32 software that runs
968at Secure-EL1 - the *Secure-EL1 Payload* - as it is not always a Trusted OS.
969
970The ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and a Test
971Secure-EL1 Payload Dispatcher (TSPD) service as an example of how a Trusted OS
972is supported on a production system using the Runtime Services Framework. On
973such a system, the Test BL32 image and service are replaced by the Trusted OS
974and its dispatcher service. The ARM Trusted Firmware build system expects that
975the dispatcher will define the build flag ``NEED_BL32`` to enable it to include
976the BL32 in the build either as a binary or to compile from source depending
977on whether the ``BL32`` build option is specified or not.
978
979The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
980communication with the normal-world software running in EL1/EL2. Communication
981is initiated by the normal-world software
982
983- either directly through a Fast SMC (as defined in the `SMCCC`_)
984
985- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
986 informs the TSPD about the requested power management operation. This allows
987 the TSP to prepare for or respond to the power state change
988
989The TSPD service is responsible for.
990
991- Initializing the TSP
992
993- Routing requests and responses between the secure and the non-secure
994 states during the two types of communications just described
995
996Initializing a BL32 Image
997~~~~~~~~~~~~~~~~~~~~~~~~~
998
999The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1000the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1001so. This is provided by:
1002
1003.. code:: c
1004
1005 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1006
1007which returns a reference to the ``entry_point_info`` structure corresponding to
1008the image which will be run in the specified security state. The SPD uses this
1009API to get entry point information for the SECURE image, BL32.
1010
1011In the absence of a BL32 image, BL31 passes control to the normal world
1012bootloader image (BL33). When the BL32 image is present, it is typical
1013that the SPD wants control to be passed to BL32 first and then later to BL33.
1014
1015To do this the SPD has to register a BL32 initialization function during
1016initialization of the SPD service. The BL32 initialization function has this
1017prototype:
1018
1019.. code:: c
1020
1021 int32_t init(void);
1022
1023and is registered using the ``bl31_register_bl32_init()`` function.
1024
1025Trusted Firmware supports two approaches for the SPD to pass control to BL32
1026before returning through EL3 and running the non-trusted firmware (BL33):
1027
1028#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1029 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1030 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1031 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1032
1033 When the BL32 has completed initialization at Secure-EL1, it returns to
1034 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1035 receipt of this SMC, the SPD service handler should switch the CPU context
1036 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1037 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1038 the normal world firmware BL33. On return from the handler the framework
1039 will exit to EL2 and run BL33.
1040
1041#. The BL32 setup function registers an initialization function using
1042 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1043 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1044 entrypoint.
1045 NOTE: The Test SPD service included with the Trusted Firmware provides one
1046 implementation of such a mechanism.
1047
1048 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1049 SPD service handler invokes the synchronous call return mechanism to return
1050 to the BL32 initialization function. On return from this function,
1051 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1052 continue the boot process in the normal world.
1053
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001054Crash Reporting in BL31
1055-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001056
1057BL31 implements a scheme for reporting the processor state when an unhandled
1058exception is encountered. The reporting mechanism attempts to preserve all the
1059register contents and report it via a dedicated UART (PL011 console). BL31
1060reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1061
1062A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1063the per-CPU pointer cache. The implementation attempts to minimise the memory
1064required for this feature. The file ``crash_reporting.S`` contains the
1065implementation for crash reporting.
1066
1067The sample crash output is shown below.
1068
1069::
1070
1071 x0 :0x000000004F00007C
1072 x1 :0x0000000007FFFFFF
1073 x2 :0x0000000004014D50
1074 x3 :0x0000000000000000
1075 x4 :0x0000000088007998
1076 x5 :0x00000000001343AC
1077 x6 :0x0000000000000016
1078 x7 :0x00000000000B8A38
1079 x8 :0x00000000001343AC
1080 x9 :0x00000000000101A8
1081 x10 :0x0000000000000002
1082 x11 :0x000000000000011C
1083 x12 :0x00000000FEFDC644
1084 x13 :0x00000000FED93FFC
1085 x14 :0x0000000000247950
1086 x15 :0x00000000000007A2
1087 x16 :0x00000000000007A4
1088 x17 :0x0000000000247950
1089 x18 :0x0000000000000000
1090 x19 :0x00000000FFFFFFFF
1091 x20 :0x0000000004014D50
1092 x21 :0x000000000400A38C
1093 x22 :0x0000000000247950
1094 x23 :0x0000000000000010
1095 x24 :0x0000000000000024
1096 x25 :0x00000000FEFDC868
1097 x26 :0x00000000FEFDC86A
1098 x27 :0x00000000019EDEDC
1099 x28 :0x000000000A7CFDAA
1100 x29 :0x0000000004010780
1101 x30 :0x000000000400F004
1102 scr_el3 :0x0000000000000D3D
1103 sctlr_el3 :0x0000000000C8181F
1104 cptr_el3 :0x0000000000000000
1105 tcr_el3 :0x0000000080803520
1106 daif :0x00000000000003C0
1107 mair_el3 :0x00000000000004FF
1108 spsr_el3 :0x00000000800003CC
1109 elr_el3 :0x000000000400C0CC
1110 ttbr0_el3 :0x00000000040172A0
1111 esr_el3 :0x0000000096000210
1112 sp_el3 :0x0000000004014D50
1113 far_el3 :0x000000004F00007C
1114 spsr_el1 :0x0000000000000000
1115 elr_el1 :0x0000000000000000
1116 spsr_abt :0x0000000000000000
1117 spsr_und :0x0000000000000000
1118 spsr_irq :0x0000000000000000
1119 spsr_fiq :0x0000000000000000
1120 sctlr_el1 :0x0000000030C81807
1121 actlr_el1 :0x0000000000000000
1122 cpacr_el1 :0x0000000000300000
1123 csselr_el1 :0x0000000000000002
1124 sp_el1 :0x0000000004028800
1125 esr_el1 :0x0000000000000000
1126 ttbr0_el1 :0x000000000402C200
1127 ttbr1_el1 :0x0000000000000000
1128 mair_el1 :0x00000000000004FF
1129 amair_el1 :0x0000000000000000
1130 tcr_el1 :0x0000000000003520
1131 tpidr_el1 :0x0000000000000000
1132 tpidr_el0 :0x0000000000000000
1133 tpidrro_el0 :0x0000000000000000
1134 dacr32_el2 :0x0000000000000000
1135 ifsr32_el2 :0x0000000000000000
1136 par_el1 :0x0000000000000000
1137 far_el1 :0x0000000000000000
1138 afsr0_el1 :0x0000000000000000
1139 afsr1_el1 :0x0000000000000000
1140 contextidr_el1 :0x0000000000000000
1141 vbar_el1 :0x0000000004027000
1142 cntp_ctl_el0 :0x0000000000000000
1143 cntp_cval_el0 :0x0000000000000000
1144 cntv_ctl_el0 :0x0000000000000000
1145 cntv_cval_el0 :0x0000000000000000
1146 cntkctl_el1 :0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001147 sp_el0 :0x0000000004010780
1148
1149Guidelines for Reset Handlers
1150-----------------------------
1151
1152Trusted Firmware implements a framework that allows CPU and platform ports to
1153perform actions very early after a CPU is released from reset in both the cold
1154and warm boot paths. This is done by calling the ``reset_handler()`` function in
1155both the BL1 and BL31 images. It in turn calls the platform and CPU specific
1156reset handling functions.
1157
1158Details for implementing a CPU specific reset handler can be found in
1159Section 8. Details for implementing a platform specific reset handler can be
1160found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function).
1161
1162When adding functionality to a reset handler, keep in mind that if a different
1163reset handling behavior is required between the first and the subsequent
1164invocations of the reset handling code, this should be detected at runtime.
1165In other words, the reset handler should be able to detect whether an action has
1166already been performed and act as appropriate. Possible courses of actions are,
1167e.g. skip the action the second time, or undo/redo it.
1168
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001169Configuring secure interrupts
1170-----------------------------
1171
1172The GIC driver is responsible for performing initial configuration of secure
1173interrupts on the platform. To this end, the platform is expected to provide the
1174GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1175interrupt configuration during the driver initialisation.
1176
1177There are two ways to specify secure interrupt configuration:
1178
1179#. Array of secure interrupt properties: In this scheme, in both GICv2 and GICv3
1180 driver data structures, the ``interrupt_props`` member points to an array of
1181 interrupt properties. Each element of the array specifies the interrupt
1182 number and its configuration, viz. priority, group, configuration. Each
1183 element of the array shall be populated by the macro ``INTR_PROP_DESC()``.
1184 The macro takes the following arguments:
1185
1186 - 10-bit interrupt number,
1187
1188 - 8-bit interrupt priority,
1189
1190 - Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1191 ``INTR_TYPE_NS``),
1192
1193 - Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1194 ``GIC_INTR_CFG_EDGE``).
1195
1196#. Array of secure interrupts: In this scheme, the GIC driver is provided an
1197 array of secure interrupt numbers. The GIC driver, at the time of
1198 initialisation, iterates through the array and assigns each interrupt
1199 the appropriate group.
1200
1201 - For the GICv2 driver, in ``gicv2_driver_data`` structure, the
1202 ``g0_interrupt_array`` member of the should point to the array of
1203 interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
1204 member of the should be set to the number of interrupts in the array.
1205
1206 - For the GICv3 driver, in ``gicv3_driver_data`` structure:
1207
1208 - The ``g0_interrupt_array`` member of the should point to the array of
1209 interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
1210 member of the should be set to the number of interrupts in the array.
1211
1212 - The ``g1s_interrupt_array`` member of the should point to the array of
1213 interrupts to be assigned to *Group 1 Secure*, and the
1214 ``g1s_interrupt_num`` member of the should be set to the number of
1215 interrupts in the array.
1216
1217 **Note that this scheme is deprecated.**
1218
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001219CPU specific operations framework
1220---------------------------------
1221
1222Certain aspects of the ARMv8 architecture are implementation defined,
1223that is, certain behaviours are not architecturally defined, but must be defined
1224and documented by individual processor implementations. The ARM Trusted
1225Firmware implements a framework which categorises the common implementation
1226defined behaviours and allows a processor to export its implementation of that
1227behaviour. The categories are:
1228
1229#. Processor specific reset sequence.
1230
1231#. Processor specific power down sequences.
1232
1233#. Processor specific register dumping as a part of crash reporting.
1234
1235#. Errata status reporting.
1236
1237Each of the above categories fulfils a different requirement.
1238
1239#. allows any processor specific initialization before the caches and MMU
1240 are turned on, like implementation of errata workarounds, entry into
1241 the intra-cluster coherency domain etc.
1242
1243#. allows each processor to implement the power down sequence mandated in
1244 its Technical Reference Manual (TRM).
1245
1246#. allows a processor to provide additional information to the developer
1247 in the event of a crash, for example Cortex-A53 has registers which
1248 can expose the data cache contents.
1249
1250#. allows a processor to define a function that inspects and reports the status
1251 of all errata workarounds on that processor.
1252
1253Please note that only 2. is mandated by the TRM.
1254
1255The CPU specific operations framework scales to accommodate a large number of
1256different CPUs during power down and reset handling. The platform can specify
1257any CPU optimization it wants to enable for each CPU. It can also specify
1258the CPU errata workarounds to be applied for each CPU type during reset
1259handling by defining CPU errata compile time macros. Details on these macros
1260can be found in the `cpu-specific-build-macros.rst`_ file.
1261
1262The CPU specific operations framework depends on the ``cpu_ops`` structure which
1263needs to be exported for each type of CPU in the platform. It is defined in
1264``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1265``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1266``cpu_reg_dump()``.
1267
1268The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1269suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1270exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1271configuration, these CPU specific files must be included in the build by
1272the platform makefile. The generic CPU specific operations framework code exists
1273in ``lib/cpus/aarch64/cpu_helpers.S``.
1274
1275CPU specific Reset Handling
1276~~~~~~~~~~~~~~~~~~~~~~~~~~~
1277
1278After a reset, the state of the CPU when it calls generic reset handler is:
1279MMU turned off, both instruction and data caches turned off and not part
1280of any coherency domain.
1281
1282The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1283the platform to perform any system initialization required and any system
1284errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1285the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1286array and returns it. Note that only the part number and implementer fields
1287in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1288the returned ``cpu_ops`` is then invoked which executes the required reset
1289handling for that CPU and also any errata workarounds enabled by the platform.
1290This function must preserve the values of general purpose registers x20 to x29.
1291
1292Refer to Section "Guidelines for Reset Handlers" for general guidelines
1293regarding placement of code in a reset handler.
1294
1295CPU specific power down sequence
1296~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1297
1298During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1299entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1300retrieved during power down sequences.
1301
1302Various CPU drivers register handlers to perform power down at certain power
1303levels for that specific CPU. The PSCI service, upon receiving a power down
1304request, determines the highest power level at which to execute power down
1305sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1306pick the right power down handler for the requested level. The function
1307retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1308retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1309requested power level is higher than what a CPU driver supports, the handler
1310registered for highest level is invoked.
1311
1312At runtime the platform hooks for power down are invoked by the PSCI service to
1313perform platform specific operations during a power down sequence, for example
1314turning off CCI coherency during a cluster power down.
1315
1316CPU specific register reporting during crash
1317~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1318
1319If the crash reporting is enabled in BL31, when a crash occurs, the crash
1320reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1321``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1322``cpu_ops`` is invoked, which then returns the CPU specific register values to
1323be reported and a pointer to the ASCII list of register names in a format
1324expected by the crash reporting framework.
1325
1326CPU errata status reporting
1327~~~~~~~~~~~~~~~~~~~~~~~~~~~
1328
1329Errata workarounds for CPUs supported in ARM Trusted Firmware are applied during
1330both cold and warm boots, shortly after reset. Individual Errata workarounds are
1331enabled as build options. Some errata workarounds have potential run-time
1332implications; therefore some are enabled by default, others not. Platform ports
1333shall override build options to enable or disable errata as appropriate. The CPU
1334drivers take care of applying errata workarounds that are enabled and applicable
1335to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_
1336for more information.
1337
1338Functions in CPU drivers that apply errata workaround must follow the
1339conventions listed below.
1340
1341The errata workaround must be authored as two separate functions:
1342
1343- One that checks for errata. This function must determine whether that errata
1344 applies to the current CPU. Typically this involves matching the current
1345 CPUs revision and variant against a value that's known to be affected by the
1346 errata. If the function determines that the errata applies to this CPU, it
1347 must return ``ERRATA_APPLIES``; otherwise, it must return
1348 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1349 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1350
1351For an errata identified as ``E``, the check function must be named
1352``check_errata_E``.
1353
1354This function will be invoked at different times, both from assembly and from
1355C run time. Therefore it must follow AAPCS, and must not use stack.
1356
1357- Another one that applies the errata workaround. This function would call the
1358 check function described above, and applies errata workaround if required.
1359
1360CPU drivers that apply errata workaround can optionally implement an assembly
1361function that report the status of errata workarounds pertaining to that CPU.
1362For a driver that registers the CPU, for example, ``cpux`` via. ``declare_cpu_ops``
1363macro, the errata reporting function, if it exists, must be named
1364``cpux_errata_report``. This function will always be called with MMU enabled; it
1365must follow AAPCS and may use stack.
1366
1367In a debug build of ARM Trusted Firmware, on a CPU that comes out of reset, both
1368BL1 and the run time firmware (BL31 in AArch64, and BL32 in AArch32) will invoke
1369errata status reporting function, if one exists, for that type of CPU.
1370
1371To report the status of each errata workaround, the function shall use the
1372assembler macro ``report_errata``, passing it:
1373
1374- The build option that enables the errata;
1375
1376- The name of the CPU: this must be the same identifier that CPU driver
1377 registered itself with, using ``declare_cpu_ops``;
1378
1379- And the errata identifier: the identifier must match what's used in the
1380 errata's check function described above.
1381
1382The errata status reporting function will be called once per CPU type/errata
1383combination during the software's active life time.
1384
1385It's expected that whenever an errata workaround is submitted to ARM Trusted
1386Firmware, the errata reporting function is appropriately extended to report its
1387status as well.
1388
1389Reporting the status of errata workaround is for informational purpose only; it
1390has no functional significance.
1391
1392Memory layout of BL images
1393--------------------------
1394
1395Each bootloader image can be divided in 2 parts:
1396
1397- the static contents of the image. These are data actually stored in the
1398 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1399 sections;
1400
1401- the run-time contents of the image. These are data that don't occupy any
1402 space in the binary on the disk. The ELF binary just contains some
1403 metadata indicating where these data will be stored at run-time and the
1404 corresponding sections need to be allocated and initialized at run-time.
1405 In the ELF terminology, they are called ``NOBITS`` sections.
1406
1407All PROGBITS sections are grouped together at the beginning of the image,
1408followed by all NOBITS sections. This is true for all Trusted Firmware images
1409and it is governed by the linker scripts. This ensures that the raw binary
1410images are as small as possible. If a NOBITS section was inserted in between
1411PROGBITS sections then the resulting binary file would contain zero bytes in
1412place of this NOBITS section, making the image unnecessarily bigger. Smaller
1413images allow faster loading from the FIP to the main memory.
1414
1415Linker scripts and symbols
1416~~~~~~~~~~~~~~~~~~~~~~~~~~
1417
1418Each bootloader stage image layout is described by its own linker script. The
1419linker scripts export some symbols into the program symbol table. Their values
1420correspond to particular addresses. The trusted firmware code can refer to these
1421symbols to figure out the image memory layout.
1422
1423Linker symbols follow the following naming convention in the trusted firmware.
1424
1425- ``__<SECTION>_START__``
1426
1427 Start address of a given section named ``<SECTION>``.
1428
1429- ``__<SECTION>_END__``
1430
1431 End address of a given section named ``<SECTION>``. If there is an alignment
1432 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1433 to the end address of the section's actual contents, rounded up to the right
1434 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1435 actual end address of the section's contents.
1436
1437- ``__<SECTION>_UNALIGNED_END__``
1438
1439 End address of a given section named ``<SECTION>`` without any padding or
1440 rounding up due to some alignment constraint.
1441
1442- ``__<SECTION>_SIZE__``
1443
1444 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1445 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1446 corresponds to the size of the section's actual contents, rounded up to the
1447 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1448 to know the actual size of the section's contents.
1449
1450- ``__<SECTION>_UNALIGNED_SIZE__``
1451
1452 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1453 rounding up due to some alignment constraint. In other words,
1454 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1455
1456Some of the linker symbols are mandatory as the trusted firmware code relies on
1457them to be defined. They are listed in the following subsections. Some of them
1458must be provided for each bootloader stage and some are specific to a given
1459bootloader stage.
1460
1461The linker scripts define some extra, optional symbols. They are not actually
1462used by any code but they help in understanding the bootloader images' memory
1463layout as they are easy to spot in the link map files.
1464
1465Common linker symbols
1466^^^^^^^^^^^^^^^^^^^^^
1467
1468All BL images share the following requirements:
1469
1470- The BSS section must be zero-initialised before executing any C code.
1471- The coherent memory section (if enabled) must be zero-initialised as well.
1472- The MMU setup code needs to know the extents of the coherent and read-only
1473 memory regions to set the right memory attributes. When
1474 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1475 read-only memory region is divided between code and data.
1476
1477The following linker symbols are defined for this purpose:
1478
1479- ``__BSS_START__``
1480- ``__BSS_SIZE__``
1481- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1482- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1483- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1484- ``__RO_START__``
1485- ``__RO_END__``
1486- ``__TEXT_START__``
1487- ``__TEXT_END__``
1488- ``__RODATA_START__``
1489- ``__RODATA_END__``
1490
1491BL1's linker symbols
1492^^^^^^^^^^^^^^^^^^^^
1493
1494BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1495it is entirely executed in place but it needs some read-write memory for its
1496mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1497relocated from ROM to RAM before executing any C code.
1498
1499The following additional linker symbols are defined for BL1:
1500
1501- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1502 and ``.data`` section in ROM.
1503- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1504 aligned on a 16-byte boundary.
1505- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1506 copied over. Must be aligned on a 16-byte boundary.
1507- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1508- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1509- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1510
1511How to choose the right base addresses for each bootloader stage image
1512~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1513
1514There is currently no support for dynamic image loading in the Trusted Firmware.
1515This means that all bootloader images need to be linked against their ultimate
1516runtime locations and the base addresses of each image must be chosen carefully
1517such that images don't overlap each other in an undesired way. As the code
1518grows, the base addresses might need adjustments to cope with the new memory
1519layout.
1520
1521The memory layout is completely specific to the platform and so there is no
1522general recipe for choosing the right base addresses for each bootloader image.
1523However, there are tools to aid in understanding the memory layout. These are
1524the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1525being the stage bootloader. They provide a detailed view of the memory usage of
1526each image. Among other useful information, they provide the end address of
1527each image.
1528
1529- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1530- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1531- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1532- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1533
1534For each bootloader image, the platform code must provide its start address
1535as well as a limit address that it must not overstep. The latter is used in the
1536linker scripts to check that the image doesn't grow past that address. If that
1537happens, the linker will issue a message similar to the following:
1538
1539::
1540
1541 aarch64-none-elf-ld: BLx has exceeded its limit.
1542
1543Additionally, if the platform memory layout implies some image overlaying like
1544on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1545sections must not overstep. The platform code must provide those.
1546
1547When LOAD\_IMAGE\_V2 is disabled, Trusted Firmware provides a mechanism to
1548verify at boot time that the memory to load a new image is free to prevent
1549overwriting a previously loaded image. For this mechanism to work, the platform
1550must specify the memory available in the system as regions, where each region
1551consists of base address, total size and the free area within it (as defined
1552in the ``meminfo_t`` structure). Trusted Firmware retrieves these memory regions
1553by calling the corresponding platform API:
1554
1555- ``meminfo_t *bl1_plat_sec_mem_layout(void)``
1556- ``meminfo_t *bl2_plat_sec_mem_layout(void)``
1557- ``void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)``
1558- ``void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)``
1559- ``void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)``
1560
1561For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1562return the region defined by the platform where BL1 intends to load BL2. The
1563``load_image()`` function will check that the memory where BL2 will be loaded is
1564within the specified region and marked as free.
1565
1566The actual number of regions and their base addresses and sizes is platform
1567specific. The platform may return the same region or define a different one for
1568each API. However, the overlap verification mechanism applies only to a single
1569region. Hence, it is the platform responsibility to guarantee that different
1570regions do not overlap, or that if they do, the overlapping images are not
1571accessed at the same time. This could be used, for example, to load temporary
1572images (e.g. certificates) or firmware images prior to being transfered to its
1573corresponding processor (e.g. the SCP BL2 image).
1574
1575To reduce fragmentation and simplify the tracking of free memory, all the free
1576memory within a region is always located in one single buffer defined by its
1577base address and size. Trusted Firmware implements a top/bottom load approach:
1578after a new image is loaded, it checks how much memory remains free above and
1579below the image. The smallest area is marked as unavailable, while the larger
1580area becomes the new free memory buffer. Platforms should take this behaviour
1581into account when defining the base address for each of the images. For example,
1582if an image is loaded near the middle of the region, small changes in image size
1583could cause a flip between a top load and a bottom load, which may result in an
1584unexpected memory layout.
1585
1586The following diagram is an example of an image loaded in the bottom part of
1587the memory region. The region is initially free (nothing has been loaded yet):
1588
1589::
1590
1591 Memory region
1592 +----------+
1593 | |
1594 | | <<<<<<<<<<<<< Free
1595 | |
1596 |----------| +------------+
1597 | image | <<<<<<<<<<<<< | image |
1598 |----------| +------------+
1599 | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable
1600 +----------+
1601
1602And the following diagram is an example of an image loaded in the top part:
1603
1604::
1605
1606 Memory region
1607 +----------+
1608 | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable
1609 |----------| +------------+
1610 | image | <<<<<<<<<<<<< | image |
1611 |----------| +------------+
1612 | |
1613 | | <<<<<<<<<<<<< Free
1614 | |
1615 +----------+
1616
1617When LOAD\_IMAGE\_V2 is enabled, Trusted Firmware does not provide any mechanism
1618to verify at boot time that the memory to load a new image is free to prevent
1619overwriting a previously loaded image. The platform must specify the memory
1620available in the system for all the relevant BL images to be loaded.
1621
1622For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1623return the region defined by the platform where BL1 intends to load BL2. The
1624``load_image()`` function performs bounds check for the image size based on the
1625base and maximum image size provided by the platforms. Platforms must take
1626this behaviour into account when defining the base/size for each of the images.
1627
1628Memory layout on ARM development platforms
1629^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1630
1631The following list describes the memory layout on the ARM development platforms:
1632
1633- A 4KB page of shared memory is used for communication between Trusted
1634 Firmware and the platform's power controller. This is located at the base of
1635 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1636 images is reduced by the size of the shared memory.
1637
1638 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1639 this is also used for the MHU payload when passing messages to and from the
1640 SCP.
1641
1642- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1643 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1644 data are relocated to the top of Trusted SRAM at runtime.
1645
1646- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP\_MIN),
1647 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
1648 overwrite BL1 R/W data. This implies that BL1 global variables remain valid
1649 only until execution reaches the EL3 Runtime Software entry point during a
1650 cold boot.
1651
1652- BL2 is loaded below EL3 Runtime Software.
1653
1654- On Juno, SCP\_BL2 is loaded temporarily into the EL3 Runtime Software memory
1655 region and transfered to the SCP before being overwritten by EL3 Runtime
1656 Software.
1657
1658- BL32 (for AArch64) can be loaded in one of the following locations:
1659
1660 - Trusted SRAM
1661 - Trusted DRAM (FVP only)
1662 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1663 controller)
1664
1665 When BL32 (for AArch64) is loaded into Trusted SRAM, its NOBITS sections
1666 are allowed to overlay BL2. This memory layout is designed to give the
1667 BL32 image as much memory as possible when it is loaded into Trusted SRAM.
1668
1669When LOAD\_IMAGE\_V2 is disabled the memory regions for the overlap detection
1670mechanism at boot time are defined as follows (shown per API):
1671
1672- ``meminfo_t *bl1_plat_sec_mem_layout(void)``
1673
1674 This region corresponds to the whole Trusted SRAM except for the shared
1675 memory at the base. This region is initially free. At boot time, BL1 will
1676 mark the BL1(rw) section within this region as occupied. The BL1(rw) section
1677 is placed at the top of Trusted SRAM.
1678
1679- ``meminfo_t *bl2_plat_sec_mem_layout(void)``
1680
1681 This region corresponds to the whole Trusted SRAM as defined by
1682 ``bl1_plat_sec_mem_layout()``, but with the BL1(rw) section marked as
1683 occupied. This memory region is used to check that BL2 and BL31 do not
1684 overlap with each other. BL2\_BASE and BL1\_RW\_BASE are carefully chosen so
1685 that the memory for BL31 is top loaded above BL2.
1686
1687- ``void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)``
1688
1689 This region is an exact copy of the region defined by
1690 ``bl2_plat_sec_mem_layout()``. Being a disconnected copy means that all the
1691 changes made to this region by the Trusted Firmware will not be propagated.
1692 This approach is valid because the SCP BL2 image is loaded temporarily
1693 while it is being transferred to the SCP, so this memory is reused
1694 afterwards.
1695
1696- ``void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)``
1697
1698 This region depends on the location of the BL32 image. Currently, ARM
1699 platforms support three different locations (detailed below): Trusted SRAM,
1700 Trusted DRAM and the TZC-Secured DRAM.
1701
1702- ``void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)``
1703
1704 This region corresponds to the Non-Secure DDR-DRAM, excluding the
1705 TZC-Secured area.
1706
1707The location of the BL32 image will result in different memory maps. This is
1708illustrated for both FVP and Juno in the following diagrams, using the TSP as
1709an example.
1710
1711Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory
1712layout of the other images in Trusted SRAM.
1713
1714**FVP with TSP in Trusted SRAM (default option):**
1715(These diagrams only cover the AArch64 case)
1716
1717::
1718
1719 Trusted SRAM
1720 0x04040000 +----------+ loaded by BL2 ------------------
1721 | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
1722 |----------| <<<<<<<<<<<<< |----------------|
1723 | | <<<<<<<<<<<<< | BL31 PROGBITS |
1724 |----------| ------------------
1725 | BL2 | <<<<<<<<<<<<< | BL32 NOBITS |
1726 |----------| <<<<<<<<<<<<< |----------------|
1727 | | <<<<<<<<<<<<< | BL32 PROGBITS |
1728 0x04001000 +----------+ ------------------
1729 | Shared |
1730 0x04000000 +----------+
1731
1732 Trusted ROM
1733 0x04000000 +----------+
1734 | BL1 (ro) |
1735 0x00000000 +----------+
1736
1737**FVP with TSP in Trusted DRAM:**
1738
1739::
1740
1741 Trusted DRAM
1742 0x08000000 +----------+
1743 | BL32 |
1744 0x06000000 +----------+
1745
1746 Trusted SRAM
1747 0x04040000 +----------+ loaded by BL2 ------------------
1748 | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
1749 |----------| <<<<<<<<<<<<< |----------------|
1750 | | <<<<<<<<<<<<< | BL31 PROGBITS |
1751 |----------| ------------------
1752 | BL2 |
1753 |----------|
1754 | |
1755 0x04001000 +----------+
1756 | Shared |
1757 0x04000000 +----------+
1758
1759 Trusted ROM
1760 0x04000000 +----------+
1761 | BL1 (ro) |
1762 0x00000000 +----------+
1763
1764**FVP with TSP in TZC-Secured DRAM:**
1765
1766::
1767
1768 DRAM
1769 0xffffffff +----------+
1770 | BL32 | (secure)
1771 0xff000000 +----------+
1772 | |
1773 : : (non-secure)
1774 | |
1775 0x80000000 +----------+
1776
1777 Trusted SRAM
1778 0x04040000 +----------+ loaded by BL2 ------------------
1779 | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
1780 |----------| <<<<<<<<<<<<< |----------------|
1781 | | <<<<<<<<<<<<< | BL31 PROGBITS |
1782 |----------| ------------------
1783 | BL2 |
1784 |----------|
1785 | |
1786 0x04001000 +----------+
1787 | Shared |
1788 0x04000000 +----------+
1789
1790 Trusted ROM
1791 0x04000000 +----------+
1792 | BL1 (ro) |
1793 0x00000000 +----------+
1794
1795**Juno with BL32 in Trusted SRAM (default option):**
1796
1797::
1798
1799 Flash0
1800 0x0C000000 +----------+
1801 : :
1802 0x0BED0000 |----------|
1803 | BL1 (ro) |
1804 0x0BEC0000 |----------|
1805 : :
1806 0x08000000 +----------+ BL31 is loaded
1807 after SCP_BL2 has
1808 Trusted SRAM been sent to SCP
1809 0x04040000 +----------+ loaded by BL2 ------------------
1810 | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
1811 |----------| <<<<<<<<<<<<< |----------------|
1812 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
1813 |----------| ------------------
1814 | BL2 | <<<<<<<<<<<<< | BL32 NOBITS |
1815 |----------| <<<<<<<<<<<<< |----------------|
1816 | | <<<<<<<<<<<<< | BL32 PROGBITS |
1817 0x04001000 +----------+ ------------------
1818 | MHU |
1819 0x04000000 +----------+
1820
1821**Juno with BL32 in TZC-secured DRAM:**
1822
1823::
1824
1825 DRAM
1826 0xFFE00000 +----------+
1827 | BL32 | (secure)
1828 0xFF000000 |----------|
1829 | |
1830 : : (non-secure)
1831 | |
1832 0x80000000 +----------+
1833
1834 Flash0
1835 0x0C000000 +----------+
1836 : :
1837 0x0BED0000 |----------|
1838 | BL1 (ro) |
1839 0x0BEC0000 |----------|
1840 : :
1841 0x08000000 +----------+ BL31 is loaded
1842 after SCP_BL2 has
1843 Trusted SRAM been sent to SCP
1844 0x04040000 +----------+ loaded by BL2 ------------------
1845 | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
1846 |----------| <<<<<<<<<<<<< |----------------|
1847 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
1848 |----------| ------------------
1849 | BL2 |
1850 |----------|
1851 | |
1852 0x04001000 +----------+
1853 | MHU |
1854 0x04000000 +----------+
1855
1856Firmware Image Package (FIP)
1857----------------------------
1858
1859Using a Firmware Image Package (FIP) allows for packing bootloader images (and
1860potentially other payloads) into a single archive that can be loaded by the ARM
1861Trusted Firmware from non-volatile platform storage. A driver to load images
1862from a FIP has been added to the storage layer and allows a package to be read
1863from supported platform storage. A tool to create Firmware Image Packages is
1864also provided and described below.
1865
1866Firmware Image Package layout
1867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1868
1869The FIP layout consists of a table of contents (ToC) followed by payload data.
1870The ToC itself has a header followed by one or more table entries. The ToC is
1871terminated by an end marker entry. All ToC entries describe some payload data
1872that has been appended to the end of the binary package. With the information
1873provided in the ToC entry the corresponding payload data can be retrieved.
1874
1875::
1876
1877 ------------------
1878 | ToC Header |
1879 |----------------|
1880 | ToC Entry 0 |
1881 |----------------|
1882 | ToC Entry 1 |
1883 |----------------|
1884 | ToC End Marker |
1885 |----------------|
1886 | |
1887 | Data 0 |
1888 | |
1889 |----------------|
1890 | |
1891 | Data 1 |
1892 | |
1893 ------------------
1894
1895The ToC header and entry formats are described in the header file
1896``include/tools_share/firmware_image_package.h``. This file is used by both the
1897tool and the ARM Trusted firmware.
1898
1899The ToC header has the following fields:
1900
1901::
1902
1903 `name`: The name of the ToC. This is currently used to validate the header.
1904 `serial_number`: A non-zero number provided by the creation tool
1905 `flags`: Flags associated with this data.
1906 Bits 0-31: Reserved
1907 Bits 32-47: Platform defined
1908 Bits 48-63: Reserved
1909
1910A ToC entry has the following fields:
1911
1912::
1913
1914 `uuid`: All files are referred to by a pre-defined Universally Unique
1915 IDentifier [UUID] . The UUIDs are defined in
1916 `include/tools_share/firmware_image_package.h`. The platform translates
1917 the requested image name into the corresponding UUID when accessing the
1918 package.
1919 `offset_address`: The offset address at which the corresponding payload data
1920 can be found. The offset is calculated from the ToC base address.
1921 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02001922 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001923
1924Firmware Image Package creation tool
1925~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1926
1927The FIP creation tool can be used to pack specified images into a binary package
1928that can be loaded by the ARM Trusted Firmware from platform storage. The tool
1929currently only supports packing bootloader images. Additional image definitions
1930can be added to the tool as required.
1931
1932The tool can be found in ``tools/fiptool``.
1933
1934Loading from a Firmware Image Package (FIP)
1935~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1936
1937The Firmware Image Package (FIP) driver can load images from a binary package on
1938non-volatile platform storage. For the ARM development platforms, this is
1939currently NOR FLASH.
1940
1941Bootloader images are loaded according to the platform policy as specified by
1942the function ``plat_get_image_source()``. For the ARM development platforms, this
1943means the platform will attempt to load images from a Firmware Image Package
1944located at the start of NOR FLASH0.
1945
1946The ARM development platforms' policy is to only allow loading of a known set of
1947images. The platform policy can be modified to allow additional images.
1948
1949Use of coherent memory in Trusted Firmware
1950------------------------------------------
1951
1952There might be loss of coherency when physical memory with mismatched
1953shareability, cacheability and memory attributes is accessed by multiple CPUs
1954(refer to section B2.9 of `ARM ARM`_ for more details). This possibility occurs
1955in Trusted Firmware during power up/down sequences when coherency, MMU and
1956caches are turned on/off incrementally.
1957
1958Trusted Firmware defines coherent memory as a region of memory with Device
1959nGnRE attributes in the translation tables. The translation granule size in
1960Trusted Firmware is 4KB. This is the smallest possible size of the coherent
1961memory region.
1962
1963By default, all data structures which are susceptible to accesses with
1964mismatched attributes from various CPUs are allocated in a coherent memory
1965region (refer to section 2.1 of `Porting Guide`_). The coherent memory region
1966accesses are Outer Shareable, non-cacheable and they can be accessed
1967with the Device nGnRE attributes when the MMU is turned on. Hence, at the
1968expense of at least an extra page of memory, Trusted Firmware is able to work
1969around coherency issues due to mismatched memory attributes.
1970
1971The alternative to the above approach is to allocate the susceptible data
1972structures in Normal WriteBack WriteAllocate Inner shareable memory. This
1973approach requires the data structures to be designed so that it is possible to
1974work around the issue of mismatched memory attributes by performing software
1975cache maintenance on them.
1976
1977Disabling the use of coherent memory in Trusted Firmware
1978~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1979
1980It might be desirable to avoid the cost of allocating coherent memory on
1981platforms which are memory constrained. Trusted Firmware enables inclusion of
1982coherent memory in firmware images through the build flag ``USE_COHERENT_MEM``.
1983This flag is enabled by default. It can be disabled to choose the second
1984approach described above.
1985
1986The below sections analyze the data structures allocated in the coherent memory
1987region and the changes required to allocate them in normal memory.
1988
1989Coherent memory usage in PSCI implementation
1990~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1991
1992The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
1993tree information for state management of power domains. By default, this data
1994structure is allocated in the coherent memory region in the Trusted Firmware
1995because it can be accessed by multple CPUs, either with caches enabled or
1996disabled.
1997
1998.. code:: c
1999
2000 typedef struct non_cpu_pwr_domain_node {
2001 /*
2002 * Index of the first CPU power domain node level 0 which has this node
2003 * as its parent.
2004 */
2005 unsigned int cpu_start_idx;
2006
2007 /*
2008 * Number of CPU power domains which are siblings of the domain indexed
2009 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2010 * -> cpu_start_idx + ncpus' have this node as their parent.
2011 */
2012 unsigned int ncpus;
2013
2014 /*
2015 * Index of the parent power domain node.
2016 * TODO: Figure out whether to whether using pointer is more efficient.
2017 */
2018 unsigned int parent_node;
2019
2020 plat_local_state_t local_state;
2021
2022 unsigned char level;
2023
2024 /* For indexing the psci_lock array*/
2025 unsigned char lock_index;
2026 } non_cpu_pd_node_t;
2027
2028In order to move this data structure to normal memory, the use of each of its
2029fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2030``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2031them from coherent memory involves only doing a clean and invalidate of the
2032cache lines after these fields are written.
2033
2034The field ``local_state`` can be concurrently accessed by multiple CPUs in
2035different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
2036mutual exlusion to this field and a clean and invalidate is needed after it
2037is written.
2038
2039Bakery lock data
2040~~~~~~~~~~~~~~~~
2041
2042The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2043and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2044defined as follows:
2045
2046.. code:: c
2047
2048 typedef struct bakery_lock {
2049 /*
2050 * The lock_data is a bit-field of 2 members:
2051 * Bit[0] : choosing. This field is set when the CPU is
2052 * choosing its bakery number.
2053 * Bits[1 - 15] : number. This is the bakery number allocated.
2054 */
2055 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2056 } bakery_lock_t;
2057
2058It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2059fields can be read by all CPUs but only written to by the owning CPU.
2060
2061Depending upon the data cache line size, the per-CPU fields of the
2062``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2063These per-CPU fields can be read and written during lock contention by multiple
2064CPUs with mismatched memory attributes. Since these fields are a part of the
2065lock implementation, they do not have access to any other locking primitive to
2066safeguard against the resulting coherency issues. As a result, simple software
2067cache maintenance is not enough to allocate them in coherent memory. Consider
2068the following example.
2069
2070CPU0 updates its per-CPU field with data cache enabled. This write updates a
2071local cache line which contains a copy of the fields for other CPUs as well. Now
2072CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2073disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2074its field in any other cache line in the system. This operation will invalidate
2075the update made by CPU0 as well.
2076
2077To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2078has been redesigned. The changes utilise the characteristic of Lamport's Bakery
2079algorithm mentioned earlier. The bakery\_lock structure only allocates the memory
2080for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2081needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
2082for other cores by using the total size allocated for the bakery\_lock section
2083and multiplying it with (PLATFORM\_CORE\_COUNT - 1). This enables software to
2084perform software cache maintenance on the lock data structure without running
2085into coherency issues associated with mismatched attributes.
2086
2087The bakery lock data structure ``bakery_info_t`` is defined for use when
2088``USE_COHERENT_MEM`` is disabled as follows:
2089
2090.. code:: c
2091
2092 typedef struct bakery_info {
2093 /*
2094 * The lock_data is a bit-field of 2 members:
2095 * Bit[0] : choosing. This field is set when the CPU is
2096 * choosing its bakery number.
2097 * Bits[1 - 15] : number. This is the bakery number allocated.
2098 */
2099 volatile uint16_t lock_data;
2100 } bakery_info_t;
2101
2102The ``bakery_info_t`` represents a single per-CPU field of one lock and
2103the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2104system represents the complete bakery lock. The view in memory for a system
2105with n bakery locks are:
2106
2107::
2108
2109 bakery_lock section start
2110 |----------------|
2111 | `bakery_info_t`| <-- Lock_0 per-CPU field
2112 | Lock_0 | for CPU0
2113 |----------------|
2114 | `bakery_info_t`| <-- Lock_1 per-CPU field
2115 | Lock_1 | for CPU0
2116 |----------------|
2117 | .... |
2118 |----------------|
2119 | `bakery_info_t`| <-- Lock_N per-CPU field
2120 | Lock_N | for CPU0
2121 ------------------
2122 | XXXXX |
2123 | Padding to |
2124 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2125 | Granule | continuous memory for remaining CPUs.
2126 ------------------
2127 | `bakery_info_t`| <-- Lock_0 per-CPU field
2128 | Lock_0 | for CPU1
2129 |----------------|
2130 | `bakery_info_t`| <-- Lock_1 per-CPU field
2131 | Lock_1 | for CPU1
2132 |----------------|
2133 | .... |
2134 |----------------|
2135 | `bakery_info_t`| <-- Lock_N per-CPU field
2136 | Lock_N | for CPU1
2137 ------------------
2138 | XXXXX |
2139 | Padding to |
2140 | next Cache WB |
2141 | Granule |
2142 ------------------
2143
2144Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
2145operation on Lock\_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
2146``bakery_lock`` section need to be fetched and appropriate cache operations need
2147to be performed for each access.
2148
2149On ARM Platforms, bakery locks are used in psci (``psci_locks``) and power controller
2150driver (``arm_lock``).
2151
2152Non Functional Impact of removing coherent memory
2153~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2154
2155Removal of the coherent memory region leads to the additional software overhead
2156of performing cache maintenance for the affected data structures. However, since
2157the memory where the data structures are allocated is cacheable, the overhead is
2158mostly mitigated by an increase in performance.
2159
2160There is however a performance impact for bakery locks, due to:
2161
2162- Additional cache maintenance operations, and
2163- Multiple cache line reads for each lock operation, since the bakery locks
2164 for each CPU are distributed across different cache lines.
2165
2166The implementation has been optimized to minimize this additional overhead.
2167Measurements indicate that when bakery locks are allocated in Normal memory, the
2168minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2169in Device memory the same is 2 micro seconds. The measurements were done on the
2170Juno ARM development platform.
2171
2172As mentioned earlier, almost a page of memory can be saved by disabling
2173``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2174whether coherent memory should be used. If a platform disables
2175``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2176optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
2177`Porting Guide`_). Refer to the reference platform code for examples.
2178
2179Isolating code and read-only data on separate memory pages
2180----------------------------------------------------------
2181
2182In the ARMv8 VMSA, translation table entries include fields that define the
2183properties of the target memory region, such as its access permissions. The
2184smallest unit of memory that can be addressed by a translation table entry is
2185a memory page. Therefore, if software needs to set different permissions on two
2186memory regions then it needs to map them using different memory pages.
2187
2188The default memory layout for each BL image is as follows:
2189
2190::
2191
2192 | ... |
2193 +-------------------+
2194 | Read-write data |
2195 +-------------------+ Page boundary
2196 | <Padding> |
2197 +-------------------+
2198 | Exception vectors |
2199 +-------------------+ 2 KB boundary
2200 | <Padding> |
2201 +-------------------+
2202 | Read-only data |
2203 +-------------------+
2204 | Code |
2205 +-------------------+ BLx_BASE
2206
2207Note: The 2KB alignment for the exception vectors is an architectural
2208requirement.
2209
2210The read-write data start on a new memory page so that they can be mapped with
2211read-write permissions, whereas the code and read-only data below are configured
2212as read-only.
2213
2214However, the read-only data are not aligned on a page boundary. They are
2215contiguous to the code. Therefore, the end of the code section and the beginning
2216of the read-only data one might share a memory page. This forces both to be
2217mapped with the same memory attributes. As the code needs to be executable, this
2218means that the read-only data stored on the same memory page as the code are
2219executable as well. This could potentially be exploited as part of a security
2220attack.
2221
2222TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2223read-only data on separate memory pages. This in turn allows independent control
2224of the access permissions for the code and read-only data. In this case,
2225platform code gets a finer-grained view of the image layout and can
2226appropriately map the code region as executable and the read-only data as
2227execute-never.
2228
2229This has an impact on memory footprint, as padding bytes need to be introduced
2230between the code and read-only data to ensure the segragation of the two. To
2231limit the memory cost, this flag also changes the memory layout such that the
2232code and exception vectors are now contiguous, like so:
2233
2234::
2235
2236 | ... |
2237 +-------------------+
2238 | Read-write data |
2239 +-------------------+ Page boundary
2240 | <Padding> |
2241 +-------------------+
2242 | Read-only data |
2243 +-------------------+ Page boundary
2244 | <Padding> |
2245 +-------------------+
2246 | Exception vectors |
2247 +-------------------+ 2 KB boundary
2248 | <Padding> |
2249 +-------------------+
2250 | Code |
2251 +-------------------+ BLx_BASE
2252
2253With this more condensed memory layout, the separation of read-only data will
2254add zero or one page to the memory footprint of each BL image. Each platform
2255should consider the trade-off between memory footprint and security.
2256
2257This build flag is disabled by default, minimising memory footprint. On ARM
2258platforms, it is enabled.
2259
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002260Publish and Subscribe Framework
2261-------------------------------
2262
2263The Publish and Subscribe Framework allows EL3 components to define and publish
2264events, to which other EL3 components can subscribe.
2265
2266The following macros are provided by the framework:
2267
2268- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2269 the event name, which must be a valid C identifier. All calls to
2270 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2271 ``pubsub_events.h``.
2272
2273- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2274 subscribed handlers and calling them in turn. The handlers will be passed the
2275 parameter ``arg``. The expected use-case is to broadcast an event.
2276
2277- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2278 ``NULL`` is passed to subscribed handlers.
2279
2280- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2281 subscribe to ``event``. The handler will be executed whenever the ``event``
2282 is published.
2283
2284- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2285 subscribed for ``event``. ``subscriber`` must be a local variable of type
2286 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2287 iteration. This macro can be used for those patterns that none of the
2288 ``PUBLISH_EVENT_*()`` macros cover.
2289
2290Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2291result in build error. Subscribing to an undefined event however won't.
2292
2293Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2294signature:
2295
2296::
2297
2298 typedef void* (*pubsub_cb_t)(const void *arg);
2299
2300There may be arbitrary number of handlers registered to the same event. The
2301order in which subscribed handlers are notified when that event is published is
2302not defined. Subscribed handlers may be executed in any order; handlers should
2303not assume any relative ordering amongst them.
2304
2305Publishing an event on a PE will result in subscribed handlers executing on that
2306PE only; it won't cause handlers to execute on a different PE.
2307
2308Note that publishing an event on a PE blocks until all the subscribed handlers
2309finish executing on the PE.
2310
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002311ARM Trusted Firmware generic code publishes and subscribes to some events
2312within. Platform ports are discouraged from subscribing to them. These events
2313may be withdrawn, renamed, or have their semantics altered in the future.
2314Platforms may however register, publish, and subscribe to platform-specific
2315events.
2316
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002317Publish and Subscribe Example
2318~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2319
2320A publisher that wants to publish event ``foo`` would:
2321
2322- Define the event ``foo`` in the ``pubsub_events.h``.
2323
2324 ::
2325
2326 REGISTER_PUBSUB_EVENT(foo);
2327
2328- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2329 publish the event at the appropriate path and time of execution.
2330
2331A subscriber that wants to subscribe to event ``foo`` published above would
2332implement:
2333
2334::
2335
2336 void *foo_handler(const void *arg)
2337 {
2338 void *result;
2339
2340 /* Do handling ... */
2341
2342 return result;
2343 }
2344
2345 SUBSCRIBE_TO_EVENT(foo, foo_handler);
2346
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002347Performance Measurement Framework
2348---------------------------------
2349
2350The Performance Measurement Framework (PMF) facilitates collection of
2351timestamps by registered services and provides interfaces to retrieve
2352them from within the ARM Trusted Firmware. A platform can choose to
2353expose appropriate SMCs to retrieve these collected timestamps.
2354
2355By default, the global physical counter is used for the timestamp
2356value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2357timestamps captured by other CPUs.
2358
2359Timestamp identifier format
2360~~~~~~~~~~~~~~~~~~~~~~~~~~~
2361
2362A PMF timestamp is uniquely identified across the system via the
2363timestamp ID or ``tid``. The ``tid`` is composed as follows:
2364
2365::
2366
2367 Bits 0-7: The local timestamp identifier.
2368 Bits 8-9: Reserved.
2369 Bits 10-15: The service identifier.
2370 Bits 16-31: Reserved.
2371
2372#. The service identifier. Each PMF service is identified by a
2373 service name and a service identifier. Both the service name and
2374 identifier are unique within the system as a whole.
2375
2376#. The local timestamp identifier. This identifier is unique within a given
2377 service.
2378
2379Registering a PMF service
2380~~~~~~~~~~~~~~~~~~~~~~~~~
2381
2382To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2383is used. The arguments required are the service name, the service ID,
2384the total number of local timestamps to be captured and a set of flags.
2385
2386The ``flags`` field can be specified as a bitwise-OR of the following values:
2387
2388::
2389
2390 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2391 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2392
2393The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2394timestamps in a PMF specific linker section at build time.
2395Additionally, it defines necessary functions to capture and
2396retrieve a particular timestamp for the given service at runtime.
2397
2398The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF
2399timestamps from within ARM Trusted Firmware. In order to retrieve
2400timestamps from outside of ARM Trusted Firmware, the
2401``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2402accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2403macro but additionally supports retrieving timestamps using SMCs.
2404
2405Capturing a timestamp
2406~~~~~~~~~~~~~~~~~~~~~
2407
2408PMF timestamps are stored in a per-service timestamp region. On a
2409system with multiple CPUs, each timestamp is captured and stored
2410in a per-CPU cache line aligned memory region.
2411
2412Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2413used to capture a timestamp at the location where it is used. The macro
2414takes the service name, a local timestamp identifier and a flag as arguments.
2415
2416The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2417instructs PMF to do cache maintenance following the capture. Cache
2418maintenance is required if any of the service's timestamps are captured
2419with data cache disabled.
2420
2421To capture a timestamp in assembly code, the caller should use
2422``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2423calculate the address of where the timestamp would be stored. The
2424caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2425and store it at the determined address for later retrieval.
2426
2427Retrieving a timestamp
2428~~~~~~~~~~~~~~~~~~~~~~
2429
2430From within ARM Trusted Firmware, timestamps for individual CPUs can
2431be retrieved using either ``PMF_GET_TIMESTAMP_BY_MPIDR()`` or
2432``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. These macros accept the CPU's MPIDR
2433value, or its ordinal position, respectively.
2434
2435From outside ARM Trusted Firmware, timestamps for individual CPUs can be
2436retrieved by calling into ``pmf_smc_handler()``.
2437
2438.. code:: c
2439
2440 Interface : pmf_smc_handler()
2441 Argument : unsigned int smc_fid, u_register_t x1,
2442 u_register_t x2, u_register_t x3,
2443 u_register_t x4, void *cookie,
2444 void *handle, u_register_t flags
2445 Return : uintptr_t
2446
2447 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2448 when the caller of the SMC is running in AArch32 mode
2449 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2450 x1: Timestamp identifier.
2451 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2452 This can be the `mpidr` of a different core to the one initiating
2453 the SMC. In that case, service specific cache maintenance may be
2454 required to ensure the updated copy of the timestamp is returned.
2455 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2456 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2457 cache invalidate before reading the timestamp. This ensures
2458 an updated copy is returned.
2459
2460The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2461in this implementation.
2462
2463PMF code structure
2464~~~~~~~~~~~~~~~~~~
2465
2466#. ``pmf_main.c`` consists of core functions that implement service registration,
2467 initialization, storing, dumping and retrieving timestamps.
2468
2469#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2470
2471#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2472
2473#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2474 assembly code.
2475
2476#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2477
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01002478ARMv8 Architecture Extensions
2479-----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002480
2481ARM Trusted Firmware makes use of ARMv8 Architecture Extensions where
2482applicable. This section lists the usage of Architecture Extensions, and build
2483flags controlling them.
2484
2485In general, and unless individually mentioned, the build options
2486``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` selects the Architecture Extension to
2487target when building ARM Trusted Firmware. Subsequent ARM Architecture
2488Extensions are backward compatible with previous versions.
2489
2490The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2491valid numeric value. These build options only control whether or not
2492Architecture Extension-specific code is included in the build. Otherwise, ARM
2493Trusted Firmware targets the base ARMv8.0 architecture; i.e. as if
2494``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` == 0, which are also their respective
2495default values.
2496
2497See also the *Summary of build options* in `User Guide`_.
2498
2499For details on the Architecture Extension and available features, please refer
2500to the respective Architecture Extension Supplement.
2501
2502ARMv8.1
2503~~~~~~~
2504
2505This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2506``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2507
2508- The Compare and Swap instruction is used to implement spinlocks. Otherwise,
2509 the load-/store-exclusive instruction pair is used.
2510
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002511ARMv8.2
2512~~~~~~~
2513
2514This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and
2515``ARM_ARCH_MINOR`` >= 2.
2516
2517- The Common not Private (CnP) bit is enabled to indicate that multiple
2518 Page Entries in the same Inner Shareable domain use the same translation
2519 table entries for a given stage of translation for a particular translation
2520 regime.
2521
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002522Code Structure
2523--------------
2524
2525Trusted Firmware code is logically divided between the three boot loader
2526stages mentioned in the previous sections. The code is also divided into the
2527following categories (present as directories in the source code):
2528
2529- **Platform specific.** Choice of architecture specific code depends upon
2530 the platform.
2531- **Common code.** This is platform and architecture agnostic code.
2532- **Library code.** This code comprises of functionality commonly used by all
2533 other code. The PSCI implementation and other EL3 runtime frameworks reside
2534 as Library components.
2535- **Stage specific.** Code specific to a boot stage.
2536- **Drivers.**
2537- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2538 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2539
2540Each boot loader stage uses code from one or more of the above mentioned
2541categories. Based upon the above, the code layout looks like this:
2542
2543::
2544
2545 Directory Used by BL1? Used by BL2? Used by BL31?
2546 bl1 Yes No No
2547 bl2 No Yes No
2548 bl31 No No Yes
2549 plat Yes Yes Yes
2550 drivers Yes No Yes
2551 common Yes Yes Yes
2552 lib Yes Yes Yes
2553 services No No Yes
2554
2555The build system provides a non configurable build option IMAGE\_BLx for each
2556boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE\_BL1 will be
2557defined by the build system. This enables the Trusted Firmware to compile
2558certain code only for specific boot loader stages
2559
2560All assembler files have the ``.S`` extension. The linker source files for each
2561boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2562linker scripts which have the extension ``.ld``.
2563
2564FDTs provide a description of the hardware platform and are used by the Linux
2565kernel at boot time. These can be found in the ``fdts`` directory.
2566
2567References
2568----------
2569
Qixiang Xue4071da2017-10-16 17:29:18 +08002570.. [#] Trusted Board Boot Requirements CLIENT PDD (ARM DEN0006C-1). Available
Douglas Raillard30d7b362017-06-28 16:14:55 +01002571 under NDA through your ARM account representative.
2572.. [#] `Power State Coordination Interface PDD`_
2573.. [#] `SMC Calling Convention PDD`_
2574.. [#] `ARM Trusted Firmware Interrupt Management Design guide`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002575
2576--------------
2577
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002578*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002579
2580.. _Reset Design: ./reset-design.rst
2581.. _Porting Guide: ./porting-guide.rst
2582.. _Firmware Update: ./firmware-update.rst
2583.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2584.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2585.. _PSCI Library integration guide: ./psci-lib-integration-guide.rst
2586.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2587.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2588.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2589.. _here: ./psci-lib-integration-guide.rst
2590.. _cpu-specific-build-macros.rst: ./cpu-specific-build-macros.rst
2591.. _CPUBM: ./cpu-specific-build-macros.rst
2592.. _ARM ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
2593.. _User Guide: ./user-guide.rst
2594.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2595.. _ARM Trusted Firmware Interrupt Management Design guide: ./interrupt-framework-design.rst
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002596.. _Xlat_tables design: xlat-tables-lib-v2-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002597
2598.. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true