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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Anthony Zhou59fd6152017-03-13 15:34:08 +08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef TEGRA_PRIVATE_H
8#define TEGRA_PRIVATE_H
Varun Wadekarb316e242015-05-19 16:48:04 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <platform_def.h>
11
Varun Wadekara78bb1b2015-08-07 10:03:00 +053012#include <arch.h>
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070013#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/psci/psci.h>
15#include <lib/xlat_tables/xlat_tables_v2.h>
16
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070017#include <tegra_gic.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053018
Varun Wadekar7a269e22015-06-10 14:04:32 +053019/*******************************************************************************
20 * Tegra DRAM memory base address
21 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070022#define TEGRA_DRAM_BASE ULL(0x80000000)
23#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
Varun Wadekar7a269e22015-06-10 14:04:32 +053024
Varun Wadekarb7b45752015-12-28 14:55:41 -080025/*******************************************************************************
Steven Kaod417cea2017-06-14 14:02:23 +080026 * Implementation defined ACTLR_EL1 bit definitions
27 ******************************************************************************/
28#define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0)
29
30/*******************************************************************************
31 * Implementation defined ACTLR_EL2 bit definitions
32 ******************************************************************************/
33#define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0)
34
35/*******************************************************************************
Varun Wadekarb7b45752015-12-28 14:55:41 -080036 * Struct for parameters received from BL2
37 ******************************************************************************/
Varun Wadekarb316e242015-05-19 16:48:04 +053038typedef struct plat_params_from_bl2 {
Varun Wadekar6bb62462015-10-06 12:49:31 +053039 /* TZ memory size */
Varun Wadekarb316e242015-05-19 16:48:04 +053040 uint64_t tzdram_size;
Varun Wadekar6bb62462015-10-06 12:49:31 +053041 /* TZ memory base */
42 uint64_t tzdram_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053043 /* UART port ID */
Varun Wadekarfda095f2019-01-02 10:48:18 -080044 int32_t uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +080045 /* L2 ECC parity protection disable flag */
Varun Wadekarfda095f2019-01-02 10:48:18 -080046 int32_t l2_ecc_parity_prot_dis;
Varun Wadekar4967c3d2017-07-21 13:34:16 -070047 /* SHMEM base address for storing the boot logs */
48 uint64_t boot_profiler_shmem_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053049} plat_params_from_bl2_t;
50
Varun Wadekardc799302015-12-28 16:36:42 -080051/*******************************************************************************
Harvey Hsiehfbdfce12016-11-23 19:13:08 +080052 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs
53 ******************************************************************************/
54DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
55
56/*******************************************************************************
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010057 * Struct describing parameters passed to bl31
58 ******************************************************************************/
59struct tegra_bl31_params {
60 param_header_t h;
61 image_info_t *bl31_image_info;
62 entry_point_info_t *bl32_ep_info;
63 image_info_t *bl32_image_info;
64 entry_point_info_t *bl33_ep_info;
65 image_info_t *bl33_image_info;
66};
67
Varun Wadekar254441d2015-07-23 10:07:54 +053068/* Declarations for plat_psci_handlers.c */
Anthony Zhou5d1bb052017-03-03 16:23:08 +080069int32_t tegra_soc_validate_power_state(uint32_t power_state,
Varun Wadekara78bb1b2015-08-07 10:03:00 +053070 psci_power_state_t *req_state);
Varun Wadekar254441d2015-07-23 10:07:54 +053071
Varun Wadekarb316e242015-05-19 16:48:04 +053072/* Declarations for plat_setup.c */
73const mmap_region_t *plat_get_mmio_map(void);
Anthony Zhou25d127f2017-03-21 15:58:50 +080074uint32_t plat_get_console_from_id(int32_t id);
Varun Wadekarb7b45752015-12-28 14:55:41 -080075void plat_gic_setup(void);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010076struct tegra_bl31_params *plat_get_bl31_params(void);
Varun Wadekard22d4ad2016-05-23 11:41:07 -070077plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
Dilan Lee1f66f3d2017-10-27 09:51:09 +080078void plat_early_platform_setup(void);
79void plat_late_platform_setup(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053080
81/* Declarations for plat_secondary.c */
82void plat_secondary_setup(void);
Anthony Zhoufaad3462017-03-21 15:50:09 +080083int32_t plat_lock_cpu_vectors(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053084
Varun Wadekardc799302015-12-28 16:36:42 -080085/* Declarations for tegra_fiq_glue.c */
86void tegra_fiq_handler_setup(void);
87int tegra_fiq_get_intr_context(void);
88void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
89
Varun Wadekarb316e242015-05-19 16:48:04 +053090/* Declarations for tegra_security.c */
91void tegra_security_setup(void);
92void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
93
94/* Declarations for tegra_pm.c */
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080095extern uint8_t tegra_fake_system_suspend;
96
Varun Wadekarb316e242015-05-19 16:48:04 +053097void tegra_pm_system_suspend_entry(void);
98void tegra_pm_system_suspend_exit(void);
Anthony Zhou85a8fa02017-03-22 14:42:42 +080099int32_t tegra_system_suspended(void);
100int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
101int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
102int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
103int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
104int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
105int32_t tegra_soc_prepare_system_reset(void);
106__dead2 void tegra_soc_prepare_system_off(void);
107plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
108 const plat_local_state_t *states,
109 uint32_t ncpu);
110void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state);
111void tegra_cpu_standby(plat_local_state_t cpu_state);
112int32_t tegra_pwr_domain_on(u_register_t mpidr);
113void tegra_pwr_domain_off(const psci_power_state_t *target_state);
114void tegra_pwr_domain_suspend(const psci_power_state_t *target_state);
115void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
116void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state);
117void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state);
118__dead2 void tegra_system_off(void);
119__dead2 void tegra_system_reset(void);
120int32_t tegra_validate_power_state(uint32_t power_state,
121 psci_power_state_t *req_state);
122int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint);
Varun Wadekarb316e242015-05-19 16:48:04 +0530123
124/* Declarations for tegraXXX_pm.c */
125int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
126int tegra_prepare_cpu_on_finish(unsigned long mpidr);
127
128/* Declarations for tegra_bl31_setup.c */
129plat_params_from_bl2_t *bl31_get_plat_params(void);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800130int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
Varun Wadekarb316e242015-05-19 16:48:04 +0530131
Varun Wadekarbc74fec2015-07-16 15:47:03 +0530132/* Declarations for tegra_delay_timer.c */
133void tegra_delay_timer_init(void);
134
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700135void tegra_secure_entrypoint(void);
136void tegra186_cpu_reset_handler(void);
137
Anthony Zhoue5bd3452017-03-01 12:47:37 +0800138/* Declarations for tegra_sip_calls.c */
139uintptr_t tegra_sip_handler(uint32_t smc_fid,
140 u_register_t x1,
141 u_register_t x2,
142 u_register_t x3,
143 u_register_t x4,
144 void *cookie,
145 void *handle,
146 u_register_t flags);
147int plat_sip_handler(uint32_t smc_fid,
148 uint64_t x1,
149 uint64_t x2,
150 uint64_t x3,
151 uint64_t x4,
152 const void *cookie,
153 void *handle,
154 uint64_t flags);
155
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000156#endif /* TEGRA_PRIVATE_H */