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git01.mediatek.com / filogic / atf / 18babd39fd780630dffcfd2dd05e7a7d096677f4 / . / plat / nvidia / tegra / include / platform_def.h
blob: cd06d93f53c00928d79653ad2db2627b9ce916c1 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
35#include <common_def.h>
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]36#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]37
38/*******************************************************************************
39 * Generic platform constants
40 ******************************************************************************/
41
42/* Size of cacheable stacks */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]43#ifdef IMAGE_BL31
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]44#define PLATFORM_STACK_SIZE 0x400
45#endif
46
47#define TEGRA_PRIMARY_CPU 0x0
48
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]49#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]50#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
51 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]52#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]53 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]54
55/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]56 * Platform power states
57 ******************************************************************************/
58#define PLAT_MAX_RET_STATE 1
59#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
60
61/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]62 * Platform console related constants
63 ******************************************************************************/
64#define TEGRA_CONSOLE_BAUDRATE 115200
65#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000
66
67/*******************************************************************************
68 * Platform memory map related constants
69 ******************************************************************************/
70/* Size of trusted dram */
71#define TZDRAM_SIZE 0x00400000
72#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
73
74/*******************************************************************************
75 * BL31 specific defines.
76 ******************************************************************************/
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]77#define BL31_SIZE 0x20000
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]78#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]79#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
80#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
81#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]82
83/*******************************************************************************
84 * Platform specific page table and MMU setup constants
85 ******************************************************************************/
86#define ADDR_SPACE_SIZE (1ull << 32)
87#define MAX_XLAT_TABLES 3
88#define MAX_MMAP_REGIONS 8
89
90/*******************************************************************************
91 * Some data must be aligned on the biggest cache line size in the platform.
92 * This is known only to the platform as it might have a combination of
93 * integrated and external caches.
94 ******************************************************************************/
95#define CACHE_WRITEBACK_SHIFT 6
96#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
97
98#endif /* __PLATFORM_DEF_H__ */