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git01.mediatek.com / filogic / atf / 18babd39fd780630dffcfd2dd05e7a7d096677f4 / . / plat / arm / board / common / board_css_common.c
blob: 3fcc6ee02ccf07b6426e7cd24a69a5727d30b39f [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arm_def.h>
31#include <plat_arm.h>
32
33/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]34 * Table of memory regions for different BL stages to map using the MMU.
35 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
36 * takes care of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]37 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]38#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]39const mmap_region_t plat_arm_mmap[] = {
40 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]41 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]42 V2M_MAP_IOFPGA,
43 CSS_MAP_DEVICE,
44 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]45#if TRUSTED_BOARD_BOOT
46 ARM_MAP_NS_DRAM1,
47#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]48 {0}
49};
50#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]51#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]52const mmap_region_t plat_arm_mmap[] = {
53 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]54 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]55 V2M_MAP_IOFPGA,
56 CSS_MAP_DEVICE,
57 SOC_CSS_MAP_DEVICE,
58 ARM_MAP_NS_DRAM1,
59 ARM_MAP_TSP_SEC_MEM,
60 {0}
61};
62#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]63#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100[diff] [blame]64const mmap_region_t plat_arm_mmap[] = {
65 ARM_MAP_SHARED_RAM,
66 CSS_MAP_DEVICE,
67 SOC_CSS_MAP_DEVICE,
68 {0}
69};
70#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]71#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]72const mmap_region_t plat_arm_mmap[] = {
73 ARM_MAP_SHARED_RAM,
74 V2M_MAP_IOFPGA,
75 CSS_MAP_DEVICE,
76 SOC_CSS_MAP_DEVICE,
77 {0}
78};
79#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]80#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]81const mmap_region_t plat_arm_mmap[] = {
82 V2M_MAP_IOFPGA,
83 CSS_MAP_DEVICE,
84 SOC_CSS_MAP_DEVICE,
85 {0}
86};
87#endif
88
89ARM_CASSERT_MMAP
90