blob: ee467728e1de5a71ed2a3d427ce9f4134b905b61 [file] [log] [blame]
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02001/*
Yann Gautieradbf1d12021-03-22 14:21:15 +01002 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02007#include <assert.h>
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02008#include <errno.h>
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02009#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
15#include <drivers/arm/pl011.h>
16#include <drivers/generic_delay_timer.h>
17#include <drivers/partition/partition.h>
18#include <drivers/synopsys/dw_mmc.h>
19#include <drivers/mmc.h>
20#include <lib/mmio.h>
21#include <lib/optee_utils.h>
22#include <plat/common/platform.h>
23
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020024#include "hi3798cv200.h"
25#include "plat_private.h"
26
Victor Chong175dd8a2018-02-01 00:35:22 +090027static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
Andre Przywara2b1b1a52020-01-25 00:58:35 +000028static console_t console;
Yann Gautieradbf1d12021-03-22 14:21:15 +010029#if !POPLAR_RECOVERY
30static struct mmc_device_info mmc_info;
31#endif
Victor Chong175dd8a2018-02-01 00:35:22 +090032
Victor Chong175dd8a2018-02-01 00:35:22 +090033/*******************************************************************************
34 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
35 * Return 0 on success, -1 otherwise.
36 ******************************************************************************/
Victor Chong175dd8a2018-02-01 00:35:22 +090037int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
Victor Chong175dd8a2018-02-01 00:35:22 +090038{
39 /*
40 * This platform has no SCP_BL2 yet
41 */
42 return 0;
43}
44
45/*******************************************************************************
46 * Gets SPSR for BL32 entry
47 ******************************************************************************/
48uint32_t poplar_get_spsr_for_bl32_entry(void)
49{
50 /*
51 * The Secure Payload Dispatcher service is responsible for
52 * setting the SPSR prior to entry into the BL3-2 image.
53 */
54 return 0;
55}
56
57/*******************************************************************************
58 * Gets SPSR for BL33 entry
59 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -070060#ifdef __aarch64__
Victor Chong175dd8a2018-02-01 00:35:22 +090061uint32_t poplar_get_spsr_for_bl33_entry(void)
62{
63 unsigned long el_status;
64 unsigned int mode;
65 uint32_t spsr;
66
67 /* Figure out what mode we enter the non-secure world in */
68 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
69 el_status &= ID_AA64PFR0_ELX_MASK;
70
71 mode = (el_status) ? MODE_EL2 : MODE_EL1;
72
73 /*
74 * TODO: Consider the possibility of specifying the SPSR in
75 * the FIP ToC and allowing the platform to have a say as
76 * well.
77 */
78 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
79 return spsr;
80}
81#else
82uint32_t poplar_get_spsr_for_bl33_entry(void)
83{
84 unsigned int hyp_status, mode, spsr;
85
86 hyp_status = GET_VIRT_EXT(read_id_pfr1());
87
88 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
89
90 /*
91 * TODO: Consider the possibility of specifying the SPSR in
92 * the FIP ToC and allowing the platform to have a say as
93 * well.
94 */
95 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
96 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
97 return spsr;
98}
Julius Werner8e0ef0f2019-07-09 14:02:43 -070099#endif /* __aarch64__ */
Victor Chong175dd8a2018-02-01 00:35:22 +0900100
Victor Chong175dd8a2018-02-01 00:35:22 +0900101int poplar_bl2_handle_post_image_load(unsigned int image_id)
102{
103 int err = 0;
104 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Victor Chongaa033472018-02-01 00:35:39 +0900105#ifdef SPD_opteed
106 bl_mem_params_node_t *pager_mem_params = NULL;
107 bl_mem_params_node_t *paged_mem_params = NULL;
108#endif
Victor Chong175dd8a2018-02-01 00:35:22 +0900109
110 assert(bl_mem_params);
111
112 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700113#ifdef __aarch64__
Victor Chong175dd8a2018-02-01 00:35:22 +0900114 case BL32_IMAGE_ID:
Victor Chongaa033472018-02-01 00:35:39 +0900115#ifdef SPD_opteed
116 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
117 assert(pager_mem_params);
118
119 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
120 assert(paged_mem_params);
121
122 err = parse_optee_header(&bl_mem_params->ep_info,
123 &pager_mem_params->image_info,
124 &paged_mem_params->image_info);
125 if (err != 0) {
126 WARN("OPTEE header parse error.\n");
127 }
128
129 /*
130 * OP-TEE expect to receive DTB address in x2.
131 * This will be copied into x2 by dispatcher.
132 * Set this (arg3) if necessary
133 */
134 /* bl_mem_params->ep_info.args.arg3 = PLAT_HIKEY_DT_BASE; */
135#endif
Victor Chong175dd8a2018-02-01 00:35:22 +0900136 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry();
137 break;
138#endif
139
140 case BL33_IMAGE_ID:
141 /* BL33 expects to receive the primary CPU MPID (through r0) */
142 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
143 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry();
144 break;
145
146#ifdef SCP_BL2_BASE
147 case SCP_BL2_IMAGE_ID:
148 /* The subsequent handling of SCP_BL2 is platform specific */
149 err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info);
150 if (err) {
151 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
152 }
153 break;
154#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000155 default:
156 /* Do nothing in default case */
157 break;
Victor Chong175dd8a2018-02-01 00:35:22 +0900158 }
159
160 return err;
161}
162
163/*******************************************************************************
164 * This function can be used by the platforms to update/use image
165 * information for given `image_id`.
166 ******************************************************************************/
167int bl2_plat_handle_post_image_load(unsigned int image_id)
168{
169 return poplar_bl2_handle_post_image_load(image_id);
170}
171
Antonio Nino Diaze93cde12018-09-24 17:15:15 +0100172void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
173 u_register_t arg2, u_register_t arg3)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200174{
Antonio Nino Diaze93cde12018-09-24 17:15:15 +0100175 struct meminfo *mem_layout = (struct meminfo *)arg1;
Shawn Guod793ff02018-09-27 16:48:00 +0800176#if !POPLAR_RECOVERY
Victor Chong539408d2018-01-03 01:53:08 +0900177 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
Victor Chongf0c7c612018-01-16 00:29:47 +0900178#endif
Victor Chong539408d2018-01-03 01:53:08 +0900179
Jerome Forissier74a19f22018-11-08 11:57:30 +0000180 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
181 PL011_BAUDRATE, &console);
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200182
183 /* Enable arch timer */
184 generic_delay_timer_init();
185
186 bl2_tzram_layout = *mem_layout;
Victor Chong539408d2018-01-03 01:53:08 +0900187
Victor Chongf0c7c612018-01-16 00:29:47 +0900188#if !POPLAR_RECOVERY
Victor Chong539408d2018-01-03 01:53:08 +0900189 /* SoC-specific emmc register are initialized/configured by bootrom */
190 INFO("BL2: initializing emmc\n");
Yann Gautieradbf1d12021-03-22 14:21:15 +0100191 mmc_info.mmc_dev_type = MMC_IS_EMMC;
192 dw_mmc_init(&params, &mmc_info);
Victor Chongf0c7c612018-01-16 00:29:47 +0900193#endif
Victor Chong539408d2018-01-03 01:53:08 +0900194
195 plat_io_setup();
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200196}
197
198void bl2_plat_arch_setup(void)
199{
200 plat_configure_mmu_el1(bl2_tzram_layout.total_base,
201 bl2_tzram_layout.total_size,
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000202 BL_CODE_BASE,
203 BL_CODE_END,
204 BL_COHERENT_RAM_BASE,
205 BL_COHERENT_RAM_END);
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200206}
207
208void bl2_platform_setup(void)
209{
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200210}
211
Victor Chong175dd8a2018-02-01 00:35:22 +0900212uintptr_t plat_get_ns_image_entrypoint(void)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200213{
Victor Chong175dd8a2018-02-01 00:35:22 +0900214#ifdef PRELOADED_BL33_BASE
215 return PRELOADED_BL33_BASE;
216#else
Victor Chong6df271c2017-10-27 00:09:14 +0900217 return PLAT_POPLAR_NS_IMAGE_OFFSET;
Victor Chong175dd8a2018-02-01 00:35:22 +0900218#endif
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200219}