Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <bl_common.h> |
| 33 | #include <bl1.h> |
| 34 | #include <platform.h> |
| 35 | #include <runtime_svc.h> |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 36 | #include <asm_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
| 38 | .globl early_exceptions |
Achin Gupta | 5443f2b | 2014-01-18 16:26:30 +0000 | [diff] [blame] | 39 | .weak display_boot_progress |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 41 | .section .vectors, "ax"; .align 11 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | |
| 43 | /* ----------------------------------------------------- |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 44 | * Very simple stackless exception handlers used by all |
| 45 | * bootloader stages. BL31 uses them before stacks are |
| 46 | * setup. BL1/BL2 use them throughout. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | * ----------------------------------------------------- |
| 48 | */ |
| 49 | .align 7 |
| 50 | early_exceptions: |
| 51 | /* ----------------------------------------------------- |
| 52 | * Current EL with SP0 : 0x0 - 0x180 |
| 53 | * ----------------------------------------------------- |
| 54 | */ |
| 55 | SynchronousExceptionSP0: |
| 56 | mov x0, #SYNC_EXCEPTION_SP_EL0 |
| 57 | bl plat_report_exception |
| 58 | b SynchronousExceptionSP0 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 59 | check_vector_size SynchronousExceptionSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | |
| 61 | .align 7 |
| 62 | IrqSP0: |
| 63 | mov x0, #IRQ_SP_EL0 |
| 64 | bl plat_report_exception |
| 65 | b IrqSP0 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 66 | check_vector_size IrqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 67 | |
| 68 | .align 7 |
| 69 | FiqSP0: |
| 70 | mov x0, #FIQ_SP_EL0 |
| 71 | bl plat_report_exception |
| 72 | b FiqSP0 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 73 | check_vector_size FiqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 74 | |
| 75 | .align 7 |
| 76 | SErrorSP0: |
| 77 | mov x0, #SERROR_SP_EL0 |
| 78 | bl plat_report_exception |
| 79 | b SErrorSP0 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 80 | check_vector_size SErrorSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | |
| 82 | /* ----------------------------------------------------- |
| 83 | * Current EL with SPx: 0x200 - 0x380 |
| 84 | * ----------------------------------------------------- |
| 85 | */ |
| 86 | .align 7 |
| 87 | SynchronousExceptionSPx: |
| 88 | mov x0, #SYNC_EXCEPTION_SP_ELX |
| 89 | bl plat_report_exception |
| 90 | b SynchronousExceptionSPx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 91 | check_vector_size SynchronousExceptionSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 92 | |
| 93 | .align 7 |
| 94 | IrqSPx: |
| 95 | mov x0, #IRQ_SP_ELX |
| 96 | bl plat_report_exception |
| 97 | b IrqSPx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 98 | check_vector_size IrqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 99 | |
| 100 | .align 7 |
| 101 | FiqSPx: |
| 102 | mov x0, #FIQ_SP_ELX |
| 103 | bl plat_report_exception |
| 104 | b FiqSPx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 105 | check_vector_size FiqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 106 | |
| 107 | .align 7 |
| 108 | SErrorSPx: |
| 109 | mov x0, #SERROR_SP_ELX |
| 110 | bl plat_report_exception |
| 111 | b SErrorSPx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 112 | check_vector_size SErrorSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 113 | |
| 114 | /* ----------------------------------------------------- |
| 115 | * Lower EL using AArch64 : 0x400 - 0x580 |
| 116 | * ----------------------------------------------------- |
| 117 | */ |
| 118 | .align 7 |
| 119 | SynchronousExceptionA64: |
| 120 | /* --------------------------------------------- |
| 121 | * Only a single SMC exception from BL2 to ask |
| 122 | * BL1 to pass EL3 control to BL31 is expected |
| 123 | * here. |
| 124 | * --------------------------------------------- |
| 125 | */ |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 126 | b process_exception |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 127 | check_vector_size SynchronousExceptionA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 128 | |
| 129 | .align 7 |
| 130 | IrqA64: |
| 131 | mov x0, #IRQ_AARCH64 |
| 132 | bl plat_report_exception |
| 133 | b IrqA64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 134 | check_vector_size IrqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 135 | |
| 136 | .align 7 |
| 137 | FiqA64: |
| 138 | mov x0, #FIQ_AARCH64 |
| 139 | bl plat_report_exception |
| 140 | b FiqA64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 141 | check_vector_size FiqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 142 | |
| 143 | .align 7 |
| 144 | SErrorA64: |
| 145 | mov x0, #SERROR_AARCH64 |
| 146 | bl plat_report_exception |
| 147 | b SErrorA64 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 148 | check_vector_size SErrorA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 149 | |
| 150 | /* ----------------------------------------------------- |
| 151 | * Lower EL using AArch32 : 0x0 - 0x180 |
| 152 | * ----------------------------------------------------- |
| 153 | */ |
| 154 | .align 7 |
| 155 | SynchronousExceptionA32: |
| 156 | mov x0, #SYNC_EXCEPTION_AARCH32 |
| 157 | bl plat_report_exception |
| 158 | b SynchronousExceptionA32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 159 | check_vector_size SynchronousExceptionA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 160 | |
| 161 | .align 7 |
| 162 | IrqA32: |
| 163 | mov x0, #IRQ_AARCH32 |
| 164 | bl plat_report_exception |
| 165 | b IrqA32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 166 | check_vector_size IrqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 167 | |
| 168 | .align 7 |
| 169 | FiqA32: |
| 170 | mov x0, #FIQ_AARCH32 |
| 171 | bl plat_report_exception |
| 172 | b FiqA32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 173 | check_vector_size FiqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 174 | |
| 175 | .align 7 |
| 176 | SErrorA32: |
| 177 | mov x0, #SERROR_AARCH32 |
| 178 | bl plat_report_exception |
| 179 | b SErrorA32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 180 | check_vector_size SErrorA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 181 | |
| 182 | .align 7 |
| 183 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 184 | .section .text, "ax" |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 185 | process_exception: |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 186 | sub sp, sp, #0x40 |
| 187 | stp x0, x1, [sp, #0x0] |
| 188 | stp x2, x3, [sp, #0x10] |
| 189 | stp x4, x5, [sp, #0x20] |
| 190 | stp x6, x7, [sp, #0x30] |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 191 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 192 | mov x19, x0 |
| 193 | mov x20, x1 |
| 194 | mov x21, x2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 195 | mov x0, #SYNC_EXCEPTION_AARCH64 |
| 196 | bl plat_report_exception |
| 197 | |
| 198 | bl read_esr |
| 199 | ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 200 | cmp x1, #EC_AARCH64_SMC |
| 201 | b.ne panic |
| 202 | mov x1, #RUN_IMAGE |
| 203 | cmp x19, x1 |
| 204 | b.ne panic |
| 205 | mov x0, x20 |
| 206 | mov x1, x21 |
| 207 | mov x2, x3 |
| 208 | mov x3, x4 |
| 209 | bl display_boot_progress |
| 210 | mov x0, x20 |
| 211 | bl write_elr |
| 212 | mov x0, x21 |
| 213 | bl write_spsr |
| 214 | ubfx x0, x21, #MODE_EL_SHIFT, #2 |
| 215 | cmp x0, #MODE_EL3 |
| 216 | b.ne skip_mmu_teardown |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 217 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 218 | /* --------------------------------------------- |
| 219 | * If BL31 is to be executed in EL3 as well |
| 220 | * then turn off the MMU so that it can perform |
| 221 | * its own setup. TODO: Assuming flat mapped |
| 222 | * translations here. Also all should go into a |
| 223 | * separate MMU teardown function |
| 224 | * --------------------------------------------- |
| 225 | */ |
| 226 | mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) |
| 227 | bl read_sctlr |
| 228 | bic x0, x0, x1 |
| 229 | bl write_sctlr |
| 230 | mov x0, #DCCISW |
| 231 | bl dcsw_op_all |
| 232 | bl tlbialle3 |
| 233 | skip_mmu_teardown: |
| 234 | ldp x6, x7, [sp, #0x30] |
| 235 | ldp x4, x5, [sp, #0x20] |
| 236 | ldp x2, x3, [sp, #0x10] |
| 237 | ldp x0, x1, [sp, #0x0] |
| 238 | add sp, sp, #0x40 |
| 239 | eret |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 240 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | panic: |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 242 | wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 243 | b panic |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 244 | |
Achin Gupta | 5443f2b | 2014-01-18 16:26:30 +0000 | [diff] [blame] | 245 | /* ----------------------------------------------------- |
| 246 | * BL1 redefines this function to print the fact that |
| 247 | * BL2 has done its job and BL31 is about to be loaded. |
| 248 | * This weak definition allows other bootloader stages |
| 249 | * to use the 'early_exceptions' without running into |
| 250 | * compilation errors. |
| 251 | * ----------------------------------------------------- |
| 252 | */ |
| 253 | display_boot_progress: |
| 254 | ret |