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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Alexei Fedorov913cb7e2020-01-23 14:27:38 +00002# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000022# ARM Architecture major and minor versions: 8.0 by default.
23ARM_ARCH_MAJOR := 8
24ARM_ARCH_MINOR := 0
25
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010026# Base commit to perform code check on
27BASE_COMMIT := origin/master
28
Roberto Vargase0e99462017-10-30 14:43:43 +000029# Execute BL2 at EL3
30BL2_AT_EL3 := 0
31
Jiafei Pan43a7bf42018-03-21 07:20:09 +000032# BL2 image is stored in XIP memory, for now, this option is only supported
33# when BL2_AT_EL3 is 1.
34BL2_IN_XIP_MEM := 0
35
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080036# Do dcache invalidate upon BL2 entry at EL3
37BL2_INV_DCACHE := 1
38
Alexei Fedorov90f2e882019-05-24 12:17:09 +010039# Select the branch protection features to use.
40BRANCH_PROTECTION := 0
41
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010042# By default, consider that the platform may release several CPUs out of reset.
43# The platform Makefile is free to override this value.
44COLD_BOOT_SINGLE_CPU := 0
45
Julius Wernerb624ae02017-06-09 15:17:15 -070046# Flag to compile in coreboot support code. Exclude by default. The coreboot
47# Makefile system will set this when compiling TF as part of a coreboot image.
48COREBOOT := 0
49
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010050# For Chain of Trust
51CREATE_KEYS := 1
52
53# Build flag to include AArch32 registers in cpu context save and restore during
54# world switch. This flag must be set to 0 for AArch64-only platforms.
55CTX_INCLUDE_AARCH32_REGS := 1
56
57# Include FP registers in cpu context
58CTX_INCLUDE_FPREGS := 0
59
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000060# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
61# must be set to 1 if the platform wants to use this feature in the Secure
62# world. It is not needed to use it in the Non-secure world.
63CTX_INCLUDE_PAUTH_REGS := 0
64
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010065# Debug build
66DEBUG := 0
67
68# Build platform
69DEFAULT_PLAT := fvp
70
Christoph Müllner4f088e42019-04-24 09:45:30 +020071# Disable the generation of the binary image (ELF only).
72DISABLE_BIN_GENERATION := 0
73
Soby Mathew9fe88042018-03-26 12:43:37 +010074# Enable capability to disable authentication dynamically. Only meant for
75# development platforms.
76DYN_DISABLE_AUTH := 0
77
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010078# Build option to enable MPAM for lower ELs
79ENABLE_MPAM_FOR_LOWER_ELS := 0
80
Soby Mathew078f1a42018-08-28 11:13:55 +010081# Flag to Enable Position Independant support (PIE)
82ENABLE_PIE := 0
83
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010084# Flag to enable Performance Measurement Framework
85ENABLE_PMF := 0
86
87# Flag to enable PSCI STATs functionality
88ENABLE_PSCI_STAT := 0
89
90# Flag to enable runtime instrumentation using PMF
91ENABLE_RUNTIME_INSTRUMENTATION := 0
92
Douglas Raillard306593d2017-02-24 18:14:15 +000093# Flag to enable stack corruption protection
94ENABLE_STACK_PROTECTOR := 0
95
Jeenu Viswambharan10a67272017-09-22 08:32:10 +010096# Flag to enable exception handling in EL3
97EL3_EXCEPTION_HANDLING := 0
98
Alexei Fedorov90f2e882019-05-24 12:17:09 +010099# Flag to enable Branch Target Identification.
100# Internal flag not meant for direct setting.
101# Use BRANCH_PROTECTION to enable BTI.
102ENABLE_BTI := 0
103
104# Flag to enable Pointer Authentication.
105# Internal flag not meant for direct setting.
106# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000107ENABLE_PAUTH := 0
108
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100109# Build flag to treat usage of deprecated platform and framework APIs as error.
110ERROR_DEPRECATED := 0
111
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000112# Fault injection support
113FAULT_INJECTION_SUPPORT := 0
114
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900115# Byte alignment that each component in FIP is aligned to
116FIP_ALIGN := 0
117
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100118# Default FIP file name
119FIP_NAME := fip.bin
120
121# Default FWU_FIP file name
122FWU_FIP_NAME := fwu_fip.bin
123
124# For Chain of Trust
125GENERATE_COT := 0
126
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100127# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
128# default, they are for Secure EL1.
129GICV2_G0_FOR_EL3 := 0
130
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000131# Route External Aborts to EL3. Disabled by default; External Aborts are handled
132# by lower ELs.
133HANDLE_EA_EL3_FIRST := 0
134
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000135# Whether system coherency is managed in hardware, without explicit software
136# operations.
137HW_ASSISTED_COHERENCY := 0
138
Soby Mathew13b16052017-08-31 11:49:32 +0100139# Set the default algorithm for the generation of Trusted Board Boot keys
140KEY_ALG := rsa
141
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000142# Option to build TF with Measured Boot support
143MEASURED_BOOT := 0
144
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100145# NS timer register save and restore
146NS_TIMER_SWITCH := 0
147
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800148# Include lib/libc in the final image
149OVERRIDE_LIBC := 0
150
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100151# Build PL011 UART driver in minimal generic UART mode
152PL011_GENERIC_UART := 0
153
154# By default, consider that the platform's reset address is not programmable.
155# The platform Makefile is free to override this value.
156PROGRAMMABLE_RESET_ADDRESS := 0
157
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000158# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100159PSCI_EXTENDED_STATE_ID := 0
160
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100161# Enable RAS support
162RAS_EXTENSION := 0
163
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100164# By default, BL1 acts as the reset handler, not BL31
165RESET_TO_BL31 := 0
166
167# For Chain of Trust
168SAVE_KEYS := 0
169
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100170# Software Delegated Exception support
171SDEI_SUPPORT := 0
172
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100173# Whether code and read-only data should be put on separate memory pages. The
174# platform Makefile is free to override this value.
175SEPARATE_CODE_AND_RODATA := 0
176
Samuel Holland31a14e12018-10-17 21:40:18 -0500177# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
178# separate memory region, which may be discontiguous from the rest of BL31.
179SEPARATE_NOBITS_REGION := 0
180
Daniel Boulby468f0d72018-09-18 11:45:51 +0100181# If the BL31 image initialisation code is recalimed after use for the secondary
182# cores stack
183RECLAIM_INIT_CODE := 0
184
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100185# SPD choice
186SPD := none
187
Paul Beesleyfe975b42019-09-16 11:29:03 +0000188# Enable the Management Mode (MM)-based Secure Partition Manager implementation
189SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000190
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100191# Flag to introduce an infinite loop in BL1 just before it exits into the next
192# image. This is meant to help debugging the post-BL2 phase.
193SPIN_ON_BL1_EXIT := 0
194
195# Flags to build TF with Trusted Boot support
196TRUSTED_BOARD_BOOT := 0
197
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100198# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100199USE_COHERENT_MEM := 1
200
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200201# Build option to add debugfs support
202USE_DEBUGFS := 0
203
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100204# Build option to fconf based io
205USE_FCONF_BASED_IO := 0
206
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100207# Build option to choose whether Trusted Firmware uses library at ROM
208USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100209
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100210# Chain of trust.
211COT := tbbr
212
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900213# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100214USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900215
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100216# Build verbosity
217V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100218
219# Whether to enable D-Cache early during warm boot. This is usually
220# applicable for platforms wherein interconnect programming is not
221# required to enable cache coherency after warm reset (eg: single cluster
222# platforms).
223WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100224
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100225# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100226ENABLE_SPE_FOR_LOWER_ELS := 1
227
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100228# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100229ifeq (${ARCH},aarch32)
230 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100231endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100232
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100233# Include Memory Tagging Extension registers in cpu context. This must be set
234# to 1 if the platform wants to use this feature in the Secure world and MTE is
235# enabled at ELX.
236CTX_INCLUDE_MTE_REGS := 0
237
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100238ENABLE_AMU := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100239
240# By default, enable Scalable Vector Extension if implemented for Non-secure
241# lower ELs
242# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
243ifneq (${ARCH},aarch32)
244 ENABLE_SVE_FOR_NS := 1
245else
246 override ENABLE_SVE_FOR_NS := 0
247endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100248
249SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100250
251# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
252# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
253# Default: disabled
254USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600255
256# Enable Link Time Optimization
257ENABLE_LTO := 0