Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 1 | /* |
Heyi Guo | 774d28e | 2020-05-13 16:25:37 +0800 | [diff] [blame] | 2 | * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 7 | #ifndef TZC400_H |
| 8 | #define TZC400_H |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc_common.h> |
| 11 | #include <lib/utils_def.h> |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 12 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 13 | #define BUILD_CONFIG_OFF U(0x000) |
| 14 | #define GATE_KEEPER_OFF U(0x008) |
| 15 | #define SPECULATION_CTRL_OFF U(0x00c) |
| 16 | #define INT_STATUS U(0x010) |
| 17 | #define INT_CLEAR U(0x014) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 18 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 19 | #define FAIL_ADDRESS_LOW_OFF U(0x020) |
| 20 | #define FAIL_ADDRESS_HIGH_OFF U(0x024) |
| 21 | #define FAIL_CONTROL_OFF U(0x028) |
| 22 | #define FAIL_ID U(0x02c) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 23 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 24 | /* ID registers not common across different varieties of TZC */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 25 | #define PID5 U(0xFD4) |
| 26 | #define PID6 U(0xFD8) |
| 27 | #define PID7 U(0xFDC) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 28 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 29 | #define BUILD_CONFIG_NF_SHIFT 24 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 30 | #define BUILD_CONFIG_NF_MASK U(0x3) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 31 | #define BUILD_CONFIG_AW_SHIFT 8 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 32 | #define BUILD_CONFIG_AW_MASK U(0x3f) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 33 | #define BUILD_CONFIG_NR_SHIFT 0 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 34 | #define BUILD_CONFIG_NR_MASK U(0x1f) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 35 | |
| 36 | /* |
| 37 | * Number of gate keepers is implementation defined. But we know the max for |
| 38 | * this device is 4. Get implementation details from BUILD_CONFIG. |
| 39 | */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 40 | #define GATE_KEEPER_OS_SHIFT 16 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 41 | #define GATE_KEEPER_OS_MASK U(0xf) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 42 | #define GATE_KEEPER_OR_SHIFT 0 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 43 | #define GATE_KEEPER_OR_MASK U(0xf) |
| 44 | #define GATE_KEEPER_FILTER_MASK U(0x1) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 45 | |
| 46 | /* Speculation is enabled by default. */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 47 | #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1) |
| 48 | #define SPECULATION_CTRL_READ_DISABLE BIT_32(0) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 49 | |
| 50 | /* Max number of filters allowed is 4. */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 51 | #define INT_STATUS_OVERLAP_SHIFT 16 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 52 | #define INT_STATUS_OVERLAP_MASK U(0xf) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 53 | #define INT_STATUS_OVERRUN_SHIFT 8 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 54 | #define INT_STATUS_OVERRUN_MASK U(0xf) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 55 | #define INT_STATUS_STATUS_SHIFT 0 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 56 | #define INT_STATUS_STATUS_MASK U(0xf) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 57 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 58 | #define INT_CLEAR_CLEAR_SHIFT 0 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 59 | #define INT_CLEAR_CLEAR_MASK U(0xf) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 60 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 61 | #define FAIL_CONTROL_DIR_SHIFT 24 |
| 62 | #define FAIL_CONTROL_DIR_READ U(0) |
| 63 | #define FAIL_CONTROL_DIR_WRITE U(1) |
| 64 | #define FAIL_CONTROL_NS_SHIFT 21 |
| 65 | #define FAIL_CONTROL_NS_SECURE U(0) |
| 66 | #define FAIL_CONTROL_NS_NONSECURE U(1) |
| 67 | #define FAIL_CONTROL_PRIV_SHIFT 20 |
Yann Gautier | 3a719c0 | 2020-11-06 15:32:25 +0100 | [diff] [blame] | 68 | #define FAIL_CONTROL_PRIV_UNPRIV U(0) |
| 69 | #define FAIL_CONTROL_PRIV_PRIV U(1) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. |
| 73 | * Platform should provide the value on initialisation. |
| 74 | */ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 75 | #define FAIL_ID_VNET_SHIFT 24 |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 76 | #define FAIL_ID_VNET_MASK U(0xf) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 77 | #define FAIL_ID_ID_SHIFT 0 |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 78 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 79 | #define TZC_400_PERIPHERAL_ID U(0x460) |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 80 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 81 | /* Filter enable bits in a TZC */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 82 | #define TZC_400_REGION_ATTR_F_EN_MASK U(0xf) |
Heyi Guo | 774d28e | 2020-05-13 16:25:37 +0800 | [diff] [blame] | 83 | #define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x)) |
| 84 | #define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 85 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 86 | /* |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 87 | * All TZC region configuration registers are placed one after another. It |
| 88 | * depicts size of block of registers for programming each region. |
| 89 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 90 | #define TZC_400_REGION_SIZE U(0x20) |
| 91 | #define TZC_400_ACTION_OFF U(0x4) |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 92 | |
Yann Gautier | 2ac75b1 | 2019-02-15 16:45:48 +0100 | [diff] [blame] | 93 | #define FILTER_OFFSET U(0x10) |
| 94 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 95 | #ifndef __ASSEMBLER__ |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 96 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 97 | #include <cdefs.h> |
Dan Handley | 7607676 | 2015-03-19 19:26:52 +0000 | [diff] [blame] | 98 | #include <stdint.h> |
| 99 | |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 100 | /******************************************************************************* |
| 101 | * Function & variable prototypes |
| 102 | ******************************************************************************/ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 103 | void tzc400_init(uintptr_t base); |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 104 | void tzc400_configure_region0(unsigned int sec_attr, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 105 | unsigned int ns_device_access); |
| 106 | void tzc400_configure_region(unsigned int filters, |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 107 | unsigned int region, |
Yatharth Kochar | fc71975 | 2016-04-08 14:40:44 +0100 | [diff] [blame] | 108 | unsigned long long region_base, |
| 109 | unsigned long long region_top, |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 110 | unsigned int sec_attr, |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 111 | unsigned int nsaid_permissions); |
Lionel Debieve | 7bd2336 | 2020-09-27 20:48:30 +0200 | [diff] [blame] | 112 | void tzc400_update_filters(unsigned int region, unsigned int filters); |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 113 | void tzc400_set_action(unsigned int action); |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 114 | void tzc400_enable_filters(void); |
| 115 | void tzc400_disable_filters(void); |
Yann Gautier | 2ac75b1 | 2019-02-15 16:45:48 +0100 | [diff] [blame] | 116 | int tzc400_it_handler(void); |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 117 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 118 | static inline void tzc_init(uintptr_t base) |
| 119 | { |
| 120 | tzc400_init(base); |
| 121 | } |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 122 | |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 123 | static inline void tzc_configure_region0( |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 124 | unsigned int sec_attr, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 125 | unsigned int ns_device_access) |
| 126 | { |
| 127 | tzc400_configure_region0(sec_attr, ns_device_access); |
| 128 | } |
| 129 | |
| 130 | static inline void tzc_configure_region( |
| 131 | unsigned int filters, |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 132 | unsigned int region, |
Yatharth Kochar | fc71975 | 2016-04-08 14:40:44 +0100 | [diff] [blame] | 133 | unsigned long long region_base, |
| 134 | unsigned long long region_top, |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 135 | unsigned int sec_attr, |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 136 | unsigned int ns_device_access) |
| 137 | { |
| 138 | tzc400_configure_region(filters, region, region_base, |
| 139 | region_top, sec_attr, ns_device_access); |
| 140 | } |
| 141 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 142 | static inline void tzc_set_action(unsigned int action) |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 143 | { |
| 144 | tzc400_set_action(action); |
| 145 | } |
| 146 | |
| 147 | |
| 148 | static inline void tzc_enable_filters(void) |
| 149 | { |
| 150 | tzc400_enable_filters(); |
| 151 | } |
| 152 | |
| 153 | static inline void tzc_disable_filters(void) |
| 154 | { |
| 155 | tzc400_disable_filters(); |
| 156 | } |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 157 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 158 | #endif /* __ASSEMBLER__ */ |
Harry Liebel | afd1ec7 | 2014-04-01 19:19:22 +0100 | [diff] [blame] | 159 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 160 | #endif /* TZC400_H */ |