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Harry Liebelafd1ec72014-04-01 19:19:22 +01001/*
Heyi Guo774d28e2020-05-13 16:25:37 +08002 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
Harry Liebelafd1ec72014-04-01 19:19:22 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Harry Liebelafd1ec72014-04-01 19:19:22 +01005 */
6
Antonio Nino Diaz5f475792018-10-15 14:58:11 +01007#ifndef TZC400_H
8#define TZC400_H
Harry Liebelafd1ec72014-04-01 19:19:22 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <drivers/arm/tzc_common.h>
11#include <lib/utils_def.h>
Harry Liebelafd1ec72014-04-01 19:19:22 +010012
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010013#define BUILD_CONFIG_OFF U(0x000)
14#define GATE_KEEPER_OFF U(0x008)
15#define SPECULATION_CTRL_OFF U(0x00c)
16#define INT_STATUS U(0x010)
17#define INT_CLEAR U(0x014)
Harry Liebelafd1ec72014-04-01 19:19:22 +010018
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010019#define FAIL_ADDRESS_LOW_OFF U(0x020)
20#define FAIL_ADDRESS_HIGH_OFF U(0x024)
21#define FAIL_CONTROL_OFF U(0x028)
22#define FAIL_ID U(0x02c)
Harry Liebelafd1ec72014-04-01 19:19:22 +010023
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000024/* ID registers not common across different varieties of TZC */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010025#define PID5 U(0xFD4)
26#define PID6 U(0xFD8)
27#define PID7 U(0xFDC)
Harry Liebelafd1ec72014-04-01 19:19:22 +010028
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000029#define BUILD_CONFIG_NF_SHIFT 24
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010030#define BUILD_CONFIG_NF_MASK U(0x3)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000031#define BUILD_CONFIG_AW_SHIFT 8
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010032#define BUILD_CONFIG_AW_MASK U(0x3f)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000033#define BUILD_CONFIG_NR_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010034#define BUILD_CONFIG_NR_MASK U(0x1f)
Harry Liebelafd1ec72014-04-01 19:19:22 +010035
36/*
37 * Number of gate keepers is implementation defined. But we know the max for
38 * this device is 4. Get implementation details from BUILD_CONFIG.
39 */
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000040#define GATE_KEEPER_OS_SHIFT 16
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010041#define GATE_KEEPER_OS_MASK U(0xf)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000042#define GATE_KEEPER_OR_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010043#define GATE_KEEPER_OR_MASK U(0xf)
44#define GATE_KEEPER_FILTER_MASK U(0x1)
Harry Liebelafd1ec72014-04-01 19:19:22 +010045
46/* Speculation is enabled by default. */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010047#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
48#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
Harry Liebelafd1ec72014-04-01 19:19:22 +010049
50/* Max number of filters allowed is 4. */
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000051#define INT_STATUS_OVERLAP_SHIFT 16
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010052#define INT_STATUS_OVERLAP_MASK U(0xf)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000053#define INT_STATUS_OVERRUN_SHIFT 8
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010054#define INT_STATUS_OVERRUN_MASK U(0xf)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000055#define INT_STATUS_STATUS_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010056#define INT_STATUS_STATUS_MASK U(0xf)
Harry Liebelafd1ec72014-04-01 19:19:22 +010057
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000058#define INT_CLEAR_CLEAR_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010059#define INT_CLEAR_CLEAR_MASK U(0xf)
Harry Liebelafd1ec72014-04-01 19:19:22 +010060
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010061#define FAIL_CONTROL_DIR_SHIFT 24
62#define FAIL_CONTROL_DIR_READ U(0)
63#define FAIL_CONTROL_DIR_WRITE U(1)
64#define FAIL_CONTROL_NS_SHIFT 21
65#define FAIL_CONTROL_NS_SECURE U(0)
66#define FAIL_CONTROL_NS_NONSECURE U(1)
67#define FAIL_CONTROL_PRIV_SHIFT 20
Yann Gautier3a719c02020-11-06 15:32:25 +010068#define FAIL_CONTROL_PRIV_UNPRIV U(0)
69#define FAIL_CONTROL_PRIV_PRIV U(1)
Harry Liebelafd1ec72014-04-01 19:19:22 +010070
71/*
72 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
73 * Platform should provide the value on initialisation.
74 */
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000075#define FAIL_ID_VNET_SHIFT 24
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010076#define FAIL_ID_VNET_MASK U(0xf)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000077#define FAIL_ID_ID_SHIFT 0
Harry Liebelafd1ec72014-04-01 19:19:22 +010078
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010079#define TZC_400_PERIPHERAL_ID U(0x460)
Harry Liebelafd1ec72014-04-01 19:19:22 +010080
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000081/* Filter enable bits in a TZC */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010082#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
Heyi Guo774d28e2020-05-13 16:25:37 +080083#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
84#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
Harry Liebelafd1ec72014-04-01 19:19:22 +010085
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000086/*
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000087 * All TZC region configuration registers are placed one after another. It
88 * depicts size of block of registers for programming each region.
89 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010090#define TZC_400_REGION_SIZE U(0x20)
91#define TZC_400_ACTION_OFF U(0x4)
Dan Handley76076762015-03-19 19:26:52 +000092
Yann Gautier2ac75b12019-02-15 16:45:48 +010093#define FILTER_OFFSET U(0x10)
94
Julius Werner53456fc2019-07-09 13:49:11 -070095#ifndef __ASSEMBLER__
Dan Handley76076762015-03-19 19:26:52 +000096
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +000097#include <cdefs.h>
Dan Handley76076762015-03-19 19:26:52 +000098#include <stdint.h>
99
Harry Liebelafd1ec72014-04-01 19:19:22 +0100100/*******************************************************************************
101 * Function & variable prototypes
102 ******************************************************************************/
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000103void tzc400_init(uintptr_t base);
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100104void tzc400_configure_region0(unsigned int sec_attr,
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000105 unsigned int ns_device_access);
106void tzc400_configure_region(unsigned int filters,
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100107 unsigned int region,
Yatharth Kocharfc719752016-04-08 14:40:44 +0100108 unsigned long long region_base,
109 unsigned long long region_top,
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100110 unsigned int sec_attr,
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000111 unsigned int nsaid_permissions);
Lionel Debieve7bd23362020-09-27 20:48:30 +0200112void tzc400_update_filters(unsigned int region, unsigned int filters);
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100113void tzc400_set_action(unsigned int action);
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000114void tzc400_enable_filters(void);
115void tzc400_disable_filters(void);
Yann Gautier2ac75b12019-02-15 16:45:48 +0100116int tzc400_it_handler(void);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100117
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000118static inline void tzc_init(uintptr_t base)
119{
120 tzc400_init(base);
121}
Harry Liebelafd1ec72014-04-01 19:19:22 +0100122
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000123static inline void tzc_configure_region0(
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100124 unsigned int sec_attr,
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000125 unsigned int ns_device_access)
126{
127 tzc400_configure_region0(sec_attr, ns_device_access);
128}
129
130static inline void tzc_configure_region(
131 unsigned int filters,
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100132 unsigned int region,
Yatharth Kocharfc719752016-04-08 14:40:44 +0100133 unsigned long long region_base,
134 unsigned long long region_top,
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100135 unsigned int sec_attr,
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000136 unsigned int ns_device_access)
137{
138 tzc400_configure_region(filters, region, region_base,
139 region_top, sec_attr, ns_device_access);
140}
141
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100142static inline void tzc_set_action(unsigned int action)
Vikram Kanigiri1eabdbc2016-01-28 17:22:16 +0000143{
144 tzc400_set_action(action);
145}
146
147
148static inline void tzc_enable_filters(void)
149{
150 tzc400_enable_filters();
151}
152
153static inline void tzc_disable_filters(void)
154{
155 tzc400_disable_filters();
156}
Harry Liebelafd1ec72014-04-01 19:19:22 +0100157
Julius Werner53456fc2019-07-09 13:49:11 -0700158#endif /* __ASSEMBLER__ */
Harry Liebelafd1ec72014-04-01 19:19:22 +0100159
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100160#endif /* TZC400_H */