| commit | 3a719c099d8e4aff944cff63f7bfa61cc9ade4a3 | [log] [tgz] |
|---|---|---|
| author | Yann Gautier <yann.gautier@st.com> | Fri Nov 06 15:32:25 2020 +0100 |
| committer | Yann Gautier <yann.gautier@foss.st.com> | Mon Mar 08 18:15:26 2021 +0100 |
| tree | be463e9767e1b197d269a579b47a77be676c395d | |
| parent | ed54a041b2336c187f946af28efec05e820d4d84 [diff] [blame] |
tzc400: correct FAIL_CONTROL Privileged bit When bit 20 of TZC400 Fail control register [1] is set to 1, it means Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this. [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e Signed-off-by: Yann Gautier <yann.gautier@st.com>
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index cf2e82b..aacd5df 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h
@@ -65,8 +65,8 @@ #define FAIL_CONTROL_NS_SECURE U(0) #define FAIL_CONTROL_NS_NONSECURE U(1) #define FAIL_CONTROL_PRIV_SHIFT 20 -#define FAIL_CONTROL_PRIV_PRIV U(0) -#define FAIL_CONTROL_PRIV_UNPRIV U(1) +#define FAIL_CONTROL_PRIV_UNPRIV U(0) +#define FAIL_CONTROL_PRIV_PRIV U(1) /* * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.