Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 1 | /* |
Rajan Vaja | cd82568 | 2020-11-23 21:33:39 -0800 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for pin control. |
| 9 | */ |
| 10 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 11 | #ifndef PM_API_PINCTRL_H |
| 12 | #define PM_API_PINCTRL_H |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 13 | |
| 14 | #include "pm_common.h" |
| 15 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 16 | #define FUNCTION_NAME_LEN U(16) |
| 17 | #define GROUPS_PAYLOAD_LEN U(12) |
| 18 | #define NUM_GROUPS_PER_RESP U(6) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 19 | #define END_OF_FUNCTION "END_OF_FUNCTION" |
| 20 | #define END_OF_GROUPS -1 |
| 21 | #define PINCTRL_GRP_RESERVED -2 |
| 22 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 23 | //pinctrl function ids |
| 24 | enum { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 25 | PINCTRL_FUNC_CAN0, |
| 26 | PINCTRL_FUNC_CAN1, |
| 27 | PINCTRL_FUNC_ETHERNET0, |
| 28 | PINCTRL_FUNC_ETHERNET1, |
| 29 | PINCTRL_FUNC_ETHERNET2, |
| 30 | PINCTRL_FUNC_ETHERNET3, |
| 31 | PINCTRL_FUNC_GEMTSU0, |
| 32 | PINCTRL_FUNC_GPIO0, |
| 33 | PINCTRL_FUNC_I2C0, |
| 34 | PINCTRL_FUNC_I2C1, |
| 35 | PINCTRL_FUNC_MDIO0, |
| 36 | PINCTRL_FUNC_MDIO1, |
| 37 | PINCTRL_FUNC_MDIO2, |
| 38 | PINCTRL_FUNC_MDIO3, |
| 39 | PINCTRL_FUNC_QSPI0, |
| 40 | PINCTRL_FUNC_QSPI_FBCLK, |
| 41 | PINCTRL_FUNC_QSPI_SS, |
| 42 | PINCTRL_FUNC_SPI0, |
| 43 | PINCTRL_FUNC_SPI1, |
| 44 | PINCTRL_FUNC_SPI0_SS, |
| 45 | PINCTRL_FUNC_SPI1_SS, |
| 46 | PINCTRL_FUNC_SDIO0, |
| 47 | PINCTRL_FUNC_SDIO0_PC, |
| 48 | PINCTRL_FUNC_SDIO0_CD, |
| 49 | PINCTRL_FUNC_SDIO0_WP, |
| 50 | PINCTRL_FUNC_SDIO1, |
| 51 | PINCTRL_FUNC_SDIO1_PC, |
| 52 | PINCTRL_FUNC_SDIO1_CD, |
| 53 | PINCTRL_FUNC_SDIO1_WP, |
| 54 | PINCTRL_FUNC_NAND0, |
| 55 | PINCTRL_FUNC_NAND0_CE, |
| 56 | PINCTRL_FUNC_NAND0_RB, |
| 57 | PINCTRL_FUNC_NAND0_DQS, |
| 58 | PINCTRL_FUNC_TTC0_CLK, |
| 59 | PINCTRL_FUNC_TTC0_WAV, |
| 60 | PINCTRL_FUNC_TTC1_CLK, |
| 61 | PINCTRL_FUNC_TTC1_WAV, |
| 62 | PINCTRL_FUNC_TTC2_CLK, |
| 63 | PINCTRL_FUNC_TTC2_WAV, |
| 64 | PINCTRL_FUNC_TTC3_CLK, |
| 65 | PINCTRL_FUNC_TTC3_WAV, |
| 66 | PINCTRL_FUNC_UART0, |
| 67 | PINCTRL_FUNC_UART1, |
| 68 | PINCTRL_FUNC_USB0, |
| 69 | PINCTRL_FUNC_USB1, |
| 70 | PINCTRL_FUNC_SWDT0_CLK, |
| 71 | PINCTRL_FUNC_SWDT0_RST, |
| 72 | PINCTRL_FUNC_SWDT1_CLK, |
| 73 | PINCTRL_FUNC_SWDT1_RST, |
| 74 | PINCTRL_FUNC_PMU0, |
| 75 | PINCTRL_FUNC_PCIE0, |
| 76 | PINCTRL_FUNC_CSU0, |
| 77 | PINCTRL_FUNC_DPAUX0, |
| 78 | PINCTRL_FUNC_PJTAG0, |
| 79 | PINCTRL_FUNC_TRACE0, |
| 80 | PINCTRL_FUNC_TRACE0_CLK, |
| 81 | PINCTRL_FUNC_TESTSCAN0, |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 82 | END_FUNCTION, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 83 | }; |
| 84 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 85 | #define MAX_FUNCTION (unsigned int)(END_FUNCTION) |
| 86 | |
| 87 | // pinctrl pin numbers |
| 88 | enum { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 89 | PINCTRL_PIN_0, |
| 90 | PINCTRL_PIN_1, |
| 91 | PINCTRL_PIN_2, |
| 92 | PINCTRL_PIN_3, |
| 93 | PINCTRL_PIN_4, |
| 94 | PINCTRL_PIN_5, |
| 95 | PINCTRL_PIN_6, |
| 96 | PINCTRL_PIN_7, |
| 97 | PINCTRL_PIN_8, |
| 98 | PINCTRL_PIN_9, |
| 99 | PINCTRL_PIN_10, |
| 100 | PINCTRL_PIN_11, |
| 101 | PINCTRL_PIN_12, |
| 102 | PINCTRL_PIN_13, |
| 103 | PINCTRL_PIN_14, |
| 104 | PINCTRL_PIN_15, |
| 105 | PINCTRL_PIN_16, |
| 106 | PINCTRL_PIN_17, |
| 107 | PINCTRL_PIN_18, |
| 108 | PINCTRL_PIN_19, |
| 109 | PINCTRL_PIN_20, |
| 110 | PINCTRL_PIN_21, |
| 111 | PINCTRL_PIN_22, |
| 112 | PINCTRL_PIN_23, |
| 113 | PINCTRL_PIN_24, |
| 114 | PINCTRL_PIN_25, |
| 115 | PINCTRL_PIN_26, |
| 116 | PINCTRL_PIN_27, |
| 117 | PINCTRL_PIN_28, |
| 118 | PINCTRL_PIN_29, |
| 119 | PINCTRL_PIN_30, |
| 120 | PINCTRL_PIN_31, |
| 121 | PINCTRL_PIN_32, |
| 122 | PINCTRL_PIN_33, |
| 123 | PINCTRL_PIN_34, |
| 124 | PINCTRL_PIN_35, |
| 125 | PINCTRL_PIN_36, |
| 126 | PINCTRL_PIN_37, |
| 127 | PINCTRL_PIN_38, |
| 128 | PINCTRL_PIN_39, |
| 129 | PINCTRL_PIN_40, |
| 130 | PINCTRL_PIN_41, |
| 131 | PINCTRL_PIN_42, |
| 132 | PINCTRL_PIN_43, |
| 133 | PINCTRL_PIN_44, |
| 134 | PINCTRL_PIN_45, |
| 135 | PINCTRL_PIN_46, |
| 136 | PINCTRL_PIN_47, |
| 137 | PINCTRL_PIN_48, |
| 138 | PINCTRL_PIN_49, |
| 139 | PINCTRL_PIN_50, |
| 140 | PINCTRL_PIN_51, |
| 141 | PINCTRL_PIN_52, |
| 142 | PINCTRL_PIN_53, |
| 143 | PINCTRL_PIN_54, |
| 144 | PINCTRL_PIN_55, |
| 145 | PINCTRL_PIN_56, |
| 146 | PINCTRL_PIN_57, |
| 147 | PINCTRL_PIN_58, |
| 148 | PINCTRL_PIN_59, |
| 149 | PINCTRL_PIN_60, |
| 150 | PINCTRL_PIN_61, |
| 151 | PINCTRL_PIN_62, |
| 152 | PINCTRL_PIN_63, |
| 153 | PINCTRL_PIN_64, |
| 154 | PINCTRL_PIN_65, |
| 155 | PINCTRL_PIN_66, |
| 156 | PINCTRL_PIN_67, |
| 157 | PINCTRL_PIN_68, |
| 158 | PINCTRL_PIN_69, |
| 159 | PINCTRL_PIN_70, |
| 160 | PINCTRL_PIN_71, |
| 161 | PINCTRL_PIN_72, |
| 162 | PINCTRL_PIN_73, |
| 163 | PINCTRL_PIN_74, |
| 164 | PINCTRL_PIN_75, |
| 165 | PINCTRL_PIN_76, |
| 166 | PINCTRL_PIN_77, |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 167 | END_PINS, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 168 | }; |
| 169 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 170 | #define MAX_PIN (unsigned int)(END_PINS) |
| 171 | |
| 172 | // pinctrl group ids |
| 173 | enum { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 174 | PINCTRL_GRP_ETHERNET0_0, |
| 175 | PINCTRL_GRP_ETHERNET1_0, |
| 176 | PINCTRL_GRP_ETHERNET2_0, |
| 177 | PINCTRL_GRP_ETHERNET3_0, |
| 178 | PINCTRL_GRP_GEMTSU0_0, |
| 179 | PINCTRL_GRP_GEMTSU0_1, |
| 180 | PINCTRL_GRP_GEMTSU0_2, |
| 181 | PINCTRL_GRP_MDIO0_0, |
| 182 | PINCTRL_GRP_MDIO1_0, |
| 183 | PINCTRL_GRP_MDIO1_1, |
| 184 | PINCTRL_GRP_MDIO2_0, |
| 185 | PINCTRL_GRP_MDIO3_0, |
| 186 | PINCTRL_GRP_QSPI0_0, |
| 187 | PINCTRL_GRP_QSPI_SS, |
| 188 | PINCTRL_GRP_QSPI_FBCLK, |
| 189 | PINCTRL_GRP_SPI0_0, |
| 190 | PINCTRL_GRP_SPI0_0_SS0, |
| 191 | PINCTRL_GRP_SPI0_0_SS1, |
| 192 | PINCTRL_GRP_SPI0_0_SS2, |
| 193 | PINCTRL_GRP_SPI0_1, |
| 194 | PINCTRL_GRP_SPI0_1_SS0, |
| 195 | PINCTRL_GRP_SPI0_1_SS1, |
| 196 | PINCTRL_GRP_SPI0_1_SS2, |
| 197 | PINCTRL_GRP_SPI0_2, |
| 198 | PINCTRL_GRP_SPI0_2_SS0, |
| 199 | PINCTRL_GRP_SPI0_2_SS1, |
| 200 | PINCTRL_GRP_SPI0_2_SS2, |
| 201 | PINCTRL_GRP_SPI0_3, |
| 202 | PINCTRL_GRP_SPI0_3_SS0, |
| 203 | PINCTRL_GRP_SPI0_3_SS1, |
| 204 | PINCTRL_GRP_SPI0_3_SS2, |
| 205 | PINCTRL_GRP_SPI0_4, |
| 206 | PINCTRL_GRP_SPI0_4_SS0, |
| 207 | PINCTRL_GRP_SPI0_4_SS1, |
| 208 | PINCTRL_GRP_SPI0_4_SS2, |
| 209 | PINCTRL_GRP_SPI0_5, |
| 210 | PINCTRL_GRP_SPI0_5_SS0, |
| 211 | PINCTRL_GRP_SPI0_5_SS1, |
| 212 | PINCTRL_GRP_SPI0_5_SS2, |
| 213 | PINCTRL_GRP_SPI1_0, |
| 214 | PINCTRL_GRP_SPI1_0_SS0, |
| 215 | PINCTRL_GRP_SPI1_0_SS1, |
| 216 | PINCTRL_GRP_SPI1_0_SS2, |
| 217 | PINCTRL_GRP_SPI1_1, |
| 218 | PINCTRL_GRP_SPI1_1_SS0, |
| 219 | PINCTRL_GRP_SPI1_1_SS1, |
| 220 | PINCTRL_GRP_SPI1_1_SS2, |
| 221 | PINCTRL_GRP_SPI1_2, |
| 222 | PINCTRL_GRP_SPI1_2_SS0, |
| 223 | PINCTRL_GRP_SPI1_2_SS1, |
| 224 | PINCTRL_GRP_SPI1_2_SS2, |
| 225 | PINCTRL_GRP_SPI1_3, |
| 226 | PINCTRL_GRP_SPI1_3_SS0, |
| 227 | PINCTRL_GRP_SPI1_3_SS1, |
| 228 | PINCTRL_GRP_SPI1_3_SS2, |
| 229 | PINCTRL_GRP_SPI1_4, |
| 230 | PINCTRL_GRP_SPI1_4_SS0, |
| 231 | PINCTRL_GRP_SPI1_4_SS1, |
| 232 | PINCTRL_GRP_SPI1_4_SS2, |
| 233 | PINCTRL_GRP_SPI1_5, |
| 234 | PINCTRL_GRP_SPI1_5_SS0, |
| 235 | PINCTRL_GRP_SPI1_5_SS1, |
| 236 | PINCTRL_GRP_SPI1_5_SS2, |
| 237 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 238 | PINCTRL_GRP_SDIO0_1, |
| 239 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 240 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 241 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 242 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 243 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 244 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 245 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 246 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 247 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 248 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 249 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 250 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 251 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 252 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 253 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 254 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 255 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 256 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 257 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 258 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 259 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 260 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 261 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 262 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 263 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 264 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 265 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 266 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 267 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 268 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 269 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 270 | PINCTRL_GRP_SDIO0_0_PC, |
| 271 | PINCTRL_GRP_SDIO0_0_CD, |
| 272 | PINCTRL_GRP_SDIO0_0_WP, |
| 273 | PINCTRL_GRP_SDIO0_1_PC, |
| 274 | PINCTRL_GRP_SDIO0_1_CD, |
| 275 | PINCTRL_GRP_SDIO0_1_WP, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 276 | PINCTRL_GRP_SDIO0_2_PC, |
| 277 | PINCTRL_GRP_SDIO0_2_CD, |
| 278 | PINCTRL_GRP_SDIO0_2_WP, |
| 279 | PINCTRL_GRP_SDIO1_0, |
| 280 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 281 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 282 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 283 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 284 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 285 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 286 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 287 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 288 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 289 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 290 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 291 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 292 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 293 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 294 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 295 | PINCTRL_GRP_SDIO1_0_PC, |
| 296 | PINCTRL_GRP_SDIO1_0_CD, |
| 297 | PINCTRL_GRP_SDIO1_0_WP, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 298 | PINCTRL_GRP_SDIO1_1_PC, |
| 299 | PINCTRL_GRP_SDIO1_1_CD, |
| 300 | PINCTRL_GRP_SDIO1_1_WP, |
| 301 | PINCTRL_GRP_NAND0_0, |
| 302 | PINCTRL_GRP_NAND0_0_CE, |
| 303 | PINCTRL_GRP_NAND0_0_RB, |
| 304 | PINCTRL_GRP_NAND0_0_DQS, |
| 305 | PINCTRL_GRP_NAND0_1_CE, |
| 306 | PINCTRL_GRP_NAND0_1_RB, |
| 307 | PINCTRL_GRP_NAND0_1_DQS, |
| 308 | PINCTRL_GRP_CAN0_0, |
| 309 | PINCTRL_GRP_CAN0_1, |
| 310 | PINCTRL_GRP_CAN0_2, |
| 311 | PINCTRL_GRP_CAN0_3, |
| 312 | PINCTRL_GRP_CAN0_4, |
| 313 | PINCTRL_GRP_CAN0_5, |
| 314 | PINCTRL_GRP_CAN0_6, |
| 315 | PINCTRL_GRP_CAN0_7, |
| 316 | PINCTRL_GRP_CAN0_8, |
| 317 | PINCTRL_GRP_CAN0_9, |
| 318 | PINCTRL_GRP_CAN0_10, |
| 319 | PINCTRL_GRP_CAN0_11, |
| 320 | PINCTRL_GRP_CAN0_12, |
| 321 | PINCTRL_GRP_CAN0_13, |
| 322 | PINCTRL_GRP_CAN0_14, |
| 323 | PINCTRL_GRP_CAN0_15, |
| 324 | PINCTRL_GRP_CAN0_16, |
| 325 | PINCTRL_GRP_CAN0_17, |
| 326 | PINCTRL_GRP_CAN0_18, |
| 327 | PINCTRL_GRP_CAN1_0, |
| 328 | PINCTRL_GRP_CAN1_1, |
| 329 | PINCTRL_GRP_CAN1_2, |
| 330 | PINCTRL_GRP_CAN1_3, |
| 331 | PINCTRL_GRP_CAN1_4, |
| 332 | PINCTRL_GRP_CAN1_5, |
| 333 | PINCTRL_GRP_CAN1_6, |
| 334 | PINCTRL_GRP_CAN1_7, |
| 335 | PINCTRL_GRP_CAN1_8, |
| 336 | PINCTRL_GRP_CAN1_9, |
| 337 | PINCTRL_GRP_CAN1_10, |
| 338 | PINCTRL_GRP_CAN1_11, |
| 339 | PINCTRL_GRP_CAN1_12, |
| 340 | PINCTRL_GRP_CAN1_13, |
| 341 | PINCTRL_GRP_CAN1_14, |
| 342 | PINCTRL_GRP_CAN1_15, |
| 343 | PINCTRL_GRP_CAN1_16, |
| 344 | PINCTRL_GRP_CAN1_17, |
| 345 | PINCTRL_GRP_CAN1_18, |
| 346 | PINCTRL_GRP_CAN1_19, |
| 347 | PINCTRL_GRP_UART0_0, |
| 348 | PINCTRL_GRP_UART0_1, |
| 349 | PINCTRL_GRP_UART0_2, |
| 350 | PINCTRL_GRP_UART0_3, |
| 351 | PINCTRL_GRP_UART0_4, |
| 352 | PINCTRL_GRP_UART0_5, |
| 353 | PINCTRL_GRP_UART0_6, |
| 354 | PINCTRL_GRP_UART0_7, |
| 355 | PINCTRL_GRP_UART0_8, |
| 356 | PINCTRL_GRP_UART0_9, |
| 357 | PINCTRL_GRP_UART0_10, |
| 358 | PINCTRL_GRP_UART0_11, |
| 359 | PINCTRL_GRP_UART0_12, |
| 360 | PINCTRL_GRP_UART0_13, |
| 361 | PINCTRL_GRP_UART0_14, |
| 362 | PINCTRL_GRP_UART0_15, |
| 363 | PINCTRL_GRP_UART0_16, |
| 364 | PINCTRL_GRP_UART0_17, |
| 365 | PINCTRL_GRP_UART0_18, |
| 366 | PINCTRL_GRP_UART1_0, |
| 367 | PINCTRL_GRP_UART1_1, |
| 368 | PINCTRL_GRP_UART1_2, |
| 369 | PINCTRL_GRP_UART1_3, |
| 370 | PINCTRL_GRP_UART1_4, |
| 371 | PINCTRL_GRP_UART1_5, |
| 372 | PINCTRL_GRP_UART1_6, |
| 373 | PINCTRL_GRP_UART1_7, |
| 374 | PINCTRL_GRP_UART1_8, |
| 375 | PINCTRL_GRP_UART1_9, |
| 376 | PINCTRL_GRP_UART1_10, |
| 377 | PINCTRL_GRP_UART1_11, |
| 378 | PINCTRL_GRP_UART1_12, |
| 379 | PINCTRL_GRP_UART1_13, |
| 380 | PINCTRL_GRP_UART1_14, |
| 381 | PINCTRL_GRP_UART1_15, |
| 382 | PINCTRL_GRP_UART1_16, |
| 383 | PINCTRL_GRP_UART1_17, |
| 384 | PINCTRL_GRP_UART1_18, |
| 385 | PINCTRL_GRP_I2C0_0, |
| 386 | PINCTRL_GRP_I2C0_1, |
| 387 | PINCTRL_GRP_I2C0_2, |
| 388 | PINCTRL_GRP_I2C0_3, |
| 389 | PINCTRL_GRP_I2C0_4, |
| 390 | PINCTRL_GRP_I2C0_5, |
| 391 | PINCTRL_GRP_I2C0_6, |
| 392 | PINCTRL_GRP_I2C0_7, |
| 393 | PINCTRL_GRP_I2C0_8, |
| 394 | PINCTRL_GRP_I2C0_9, |
| 395 | PINCTRL_GRP_I2C0_10, |
| 396 | PINCTRL_GRP_I2C0_11, |
| 397 | PINCTRL_GRP_I2C0_12, |
| 398 | PINCTRL_GRP_I2C0_13, |
| 399 | PINCTRL_GRP_I2C0_14, |
| 400 | PINCTRL_GRP_I2C0_15, |
| 401 | PINCTRL_GRP_I2C0_16, |
| 402 | PINCTRL_GRP_I2C0_17, |
| 403 | PINCTRL_GRP_I2C0_18, |
| 404 | PINCTRL_GRP_I2C1_0, |
| 405 | PINCTRL_GRP_I2C1_1, |
| 406 | PINCTRL_GRP_I2C1_2, |
| 407 | PINCTRL_GRP_I2C1_3, |
| 408 | PINCTRL_GRP_I2C1_4, |
| 409 | PINCTRL_GRP_I2C1_5, |
| 410 | PINCTRL_GRP_I2C1_6, |
| 411 | PINCTRL_GRP_I2C1_7, |
| 412 | PINCTRL_GRP_I2C1_8, |
| 413 | PINCTRL_GRP_I2C1_9, |
| 414 | PINCTRL_GRP_I2C1_10, |
| 415 | PINCTRL_GRP_I2C1_11, |
| 416 | PINCTRL_GRP_I2C1_12, |
| 417 | PINCTRL_GRP_I2C1_13, |
| 418 | PINCTRL_GRP_I2C1_14, |
| 419 | PINCTRL_GRP_I2C1_15, |
| 420 | PINCTRL_GRP_I2C1_16, |
| 421 | PINCTRL_GRP_I2C1_17, |
| 422 | PINCTRL_GRP_I2C1_18, |
| 423 | PINCTRL_GRP_I2C1_19, |
| 424 | PINCTRL_GRP_TTC0_0_CLK, |
| 425 | PINCTRL_GRP_TTC0_0_WAV, |
| 426 | PINCTRL_GRP_TTC0_1_CLK, |
| 427 | PINCTRL_GRP_TTC0_1_WAV, |
| 428 | PINCTRL_GRP_TTC0_2_CLK, |
| 429 | PINCTRL_GRP_TTC0_2_WAV, |
| 430 | PINCTRL_GRP_TTC0_3_CLK, |
| 431 | PINCTRL_GRP_TTC0_3_WAV, |
| 432 | PINCTRL_GRP_TTC0_4_CLK, |
| 433 | PINCTRL_GRP_TTC0_4_WAV, |
| 434 | PINCTRL_GRP_TTC0_5_CLK, |
| 435 | PINCTRL_GRP_TTC0_5_WAV, |
| 436 | PINCTRL_GRP_TTC0_6_CLK, |
| 437 | PINCTRL_GRP_TTC0_6_WAV, |
| 438 | PINCTRL_GRP_TTC0_7_CLK, |
| 439 | PINCTRL_GRP_TTC0_7_WAV, |
| 440 | PINCTRL_GRP_TTC0_8_CLK, |
| 441 | PINCTRL_GRP_TTC0_8_WAV, |
| 442 | PINCTRL_GRP_TTC1_0_CLK, |
| 443 | PINCTRL_GRP_TTC1_0_WAV, |
| 444 | PINCTRL_GRP_TTC1_1_CLK, |
| 445 | PINCTRL_GRP_TTC1_1_WAV, |
| 446 | PINCTRL_GRP_TTC1_2_CLK, |
| 447 | PINCTRL_GRP_TTC1_2_WAV, |
| 448 | PINCTRL_GRP_TTC1_3_CLK, |
| 449 | PINCTRL_GRP_TTC1_3_WAV, |
| 450 | PINCTRL_GRP_TTC1_4_CLK, |
| 451 | PINCTRL_GRP_TTC1_4_WAV, |
| 452 | PINCTRL_GRP_TTC1_5_CLK, |
| 453 | PINCTRL_GRP_TTC1_5_WAV, |
| 454 | PINCTRL_GRP_TTC1_6_CLK, |
| 455 | PINCTRL_GRP_TTC1_6_WAV, |
| 456 | PINCTRL_GRP_TTC1_7_CLK, |
| 457 | PINCTRL_GRP_TTC1_7_WAV, |
| 458 | PINCTRL_GRP_TTC1_8_CLK, |
| 459 | PINCTRL_GRP_TTC1_8_WAV, |
| 460 | PINCTRL_GRP_TTC2_0_CLK, |
| 461 | PINCTRL_GRP_TTC2_0_WAV, |
| 462 | PINCTRL_GRP_TTC2_1_CLK, |
| 463 | PINCTRL_GRP_TTC2_1_WAV, |
| 464 | PINCTRL_GRP_TTC2_2_CLK, |
| 465 | PINCTRL_GRP_TTC2_2_WAV, |
| 466 | PINCTRL_GRP_TTC2_3_CLK, |
| 467 | PINCTRL_GRP_TTC2_3_WAV, |
| 468 | PINCTRL_GRP_TTC2_4_CLK, |
| 469 | PINCTRL_GRP_TTC2_4_WAV, |
| 470 | PINCTRL_GRP_TTC2_5_CLK, |
| 471 | PINCTRL_GRP_TTC2_5_WAV, |
| 472 | PINCTRL_GRP_TTC2_6_CLK, |
| 473 | PINCTRL_GRP_TTC2_6_WAV, |
| 474 | PINCTRL_GRP_TTC2_7_CLK, |
| 475 | PINCTRL_GRP_TTC2_7_WAV, |
| 476 | PINCTRL_GRP_TTC2_8_CLK, |
| 477 | PINCTRL_GRP_TTC2_8_WAV, |
| 478 | PINCTRL_GRP_TTC3_0_CLK, |
| 479 | PINCTRL_GRP_TTC3_0_WAV, |
| 480 | PINCTRL_GRP_TTC3_1_CLK, |
| 481 | PINCTRL_GRP_TTC3_1_WAV, |
| 482 | PINCTRL_GRP_TTC3_2_CLK, |
| 483 | PINCTRL_GRP_TTC3_2_WAV, |
| 484 | PINCTRL_GRP_TTC3_3_CLK, |
| 485 | PINCTRL_GRP_TTC3_3_WAV, |
| 486 | PINCTRL_GRP_TTC3_4_CLK, |
| 487 | PINCTRL_GRP_TTC3_4_WAV, |
| 488 | PINCTRL_GRP_TTC3_5_CLK, |
| 489 | PINCTRL_GRP_TTC3_5_WAV, |
| 490 | PINCTRL_GRP_TTC3_6_CLK, |
| 491 | PINCTRL_GRP_TTC3_6_WAV, |
| 492 | PINCTRL_GRP_TTC3_7_CLK, |
| 493 | PINCTRL_GRP_TTC3_7_WAV, |
| 494 | PINCTRL_GRP_TTC3_8_CLK, |
| 495 | PINCTRL_GRP_TTC3_8_WAV, |
| 496 | PINCTRL_GRP_SWDT0_0_CLK, |
| 497 | PINCTRL_GRP_SWDT0_0_RST, |
| 498 | PINCTRL_GRP_SWDT0_1_CLK, |
| 499 | PINCTRL_GRP_SWDT0_1_RST, |
| 500 | PINCTRL_GRP_SWDT0_2_CLK, |
| 501 | PINCTRL_GRP_SWDT0_2_RST, |
| 502 | PINCTRL_GRP_SWDT0_3_CLK, |
| 503 | PINCTRL_GRP_SWDT0_3_RST, |
| 504 | PINCTRL_GRP_SWDT0_4_CLK, |
| 505 | PINCTRL_GRP_SWDT0_4_RST, |
| 506 | PINCTRL_GRP_SWDT0_5_CLK, |
| 507 | PINCTRL_GRP_SWDT0_5_RST, |
| 508 | PINCTRL_GRP_SWDT0_6_CLK, |
| 509 | PINCTRL_GRP_SWDT0_6_RST, |
| 510 | PINCTRL_GRP_SWDT0_7_CLK, |
| 511 | PINCTRL_GRP_SWDT0_7_RST, |
| 512 | PINCTRL_GRP_SWDT0_8_CLK, |
| 513 | PINCTRL_GRP_SWDT0_8_RST, |
| 514 | PINCTRL_GRP_SWDT0_9_CLK, |
| 515 | PINCTRL_GRP_SWDT0_9_RST, |
| 516 | PINCTRL_GRP_SWDT0_10_CLK, |
| 517 | PINCTRL_GRP_SWDT0_10_RST, |
| 518 | PINCTRL_GRP_SWDT0_11_CLK, |
| 519 | PINCTRL_GRP_SWDT0_11_RST, |
| 520 | PINCTRL_GRP_SWDT0_12_CLK, |
| 521 | PINCTRL_GRP_SWDT0_12_RST, |
| 522 | PINCTRL_GRP_SWDT1_0_CLK, |
| 523 | PINCTRL_GRP_SWDT1_0_RST, |
| 524 | PINCTRL_GRP_SWDT1_1_CLK, |
| 525 | PINCTRL_GRP_SWDT1_1_RST, |
| 526 | PINCTRL_GRP_SWDT1_2_CLK, |
| 527 | PINCTRL_GRP_SWDT1_2_RST, |
| 528 | PINCTRL_GRP_SWDT1_3_CLK, |
| 529 | PINCTRL_GRP_SWDT1_3_RST, |
| 530 | PINCTRL_GRP_SWDT1_4_CLK, |
| 531 | PINCTRL_GRP_SWDT1_4_RST, |
| 532 | PINCTRL_GRP_SWDT1_5_CLK, |
| 533 | PINCTRL_GRP_SWDT1_5_RST, |
| 534 | PINCTRL_GRP_SWDT1_6_CLK, |
| 535 | PINCTRL_GRP_SWDT1_6_RST, |
| 536 | PINCTRL_GRP_SWDT1_7_CLK, |
| 537 | PINCTRL_GRP_SWDT1_7_RST, |
| 538 | PINCTRL_GRP_SWDT1_8_CLK, |
| 539 | PINCTRL_GRP_SWDT1_8_RST, |
| 540 | PINCTRL_GRP_SWDT1_9_CLK, |
| 541 | PINCTRL_GRP_SWDT1_9_RST, |
| 542 | PINCTRL_GRP_SWDT1_10_CLK, |
| 543 | PINCTRL_GRP_SWDT1_10_RST, |
| 544 | PINCTRL_GRP_SWDT1_11_CLK, |
| 545 | PINCTRL_GRP_SWDT1_11_RST, |
| 546 | PINCTRL_GRP_SWDT1_12_CLK, |
| 547 | PINCTRL_GRP_SWDT1_12_RST, |
| 548 | PINCTRL_GRP_GPIO0_0, |
| 549 | PINCTRL_GRP_GPIO0_1, |
| 550 | PINCTRL_GRP_GPIO0_2, |
| 551 | PINCTRL_GRP_GPIO0_3, |
| 552 | PINCTRL_GRP_GPIO0_4, |
| 553 | PINCTRL_GRP_GPIO0_5, |
| 554 | PINCTRL_GRP_GPIO0_6, |
| 555 | PINCTRL_GRP_GPIO0_7, |
| 556 | PINCTRL_GRP_GPIO0_8, |
| 557 | PINCTRL_GRP_GPIO0_9, |
| 558 | PINCTRL_GRP_GPIO0_10, |
| 559 | PINCTRL_GRP_GPIO0_11, |
| 560 | PINCTRL_GRP_GPIO0_12, |
| 561 | PINCTRL_GRP_GPIO0_13, |
| 562 | PINCTRL_GRP_GPIO0_14, |
| 563 | PINCTRL_GRP_GPIO0_15, |
| 564 | PINCTRL_GRP_GPIO0_16, |
| 565 | PINCTRL_GRP_GPIO0_17, |
| 566 | PINCTRL_GRP_GPIO0_18, |
| 567 | PINCTRL_GRP_GPIO0_19, |
| 568 | PINCTRL_GRP_GPIO0_20, |
| 569 | PINCTRL_GRP_GPIO0_21, |
| 570 | PINCTRL_GRP_GPIO0_22, |
| 571 | PINCTRL_GRP_GPIO0_23, |
| 572 | PINCTRL_GRP_GPIO0_24, |
| 573 | PINCTRL_GRP_GPIO0_25, |
| 574 | PINCTRL_GRP_GPIO0_26, |
| 575 | PINCTRL_GRP_GPIO0_27, |
| 576 | PINCTRL_GRP_GPIO0_28, |
| 577 | PINCTRL_GRP_GPIO0_29, |
| 578 | PINCTRL_GRP_GPIO0_30, |
| 579 | PINCTRL_GRP_GPIO0_31, |
| 580 | PINCTRL_GRP_GPIO0_32, |
| 581 | PINCTRL_GRP_GPIO0_33, |
| 582 | PINCTRL_GRP_GPIO0_34, |
| 583 | PINCTRL_GRP_GPIO0_35, |
| 584 | PINCTRL_GRP_GPIO0_36, |
| 585 | PINCTRL_GRP_GPIO0_37, |
| 586 | PINCTRL_GRP_GPIO0_38, |
| 587 | PINCTRL_GRP_GPIO0_39, |
| 588 | PINCTRL_GRP_GPIO0_40, |
| 589 | PINCTRL_GRP_GPIO0_41, |
| 590 | PINCTRL_GRP_GPIO0_42, |
| 591 | PINCTRL_GRP_GPIO0_43, |
| 592 | PINCTRL_GRP_GPIO0_44, |
| 593 | PINCTRL_GRP_GPIO0_45, |
| 594 | PINCTRL_GRP_GPIO0_46, |
| 595 | PINCTRL_GRP_GPIO0_47, |
| 596 | PINCTRL_GRP_GPIO0_48, |
| 597 | PINCTRL_GRP_GPIO0_49, |
| 598 | PINCTRL_GRP_GPIO0_50, |
| 599 | PINCTRL_GRP_GPIO0_51, |
| 600 | PINCTRL_GRP_GPIO0_52, |
| 601 | PINCTRL_GRP_GPIO0_53, |
| 602 | PINCTRL_GRP_GPIO0_54, |
| 603 | PINCTRL_GRP_GPIO0_55, |
| 604 | PINCTRL_GRP_GPIO0_56, |
| 605 | PINCTRL_GRP_GPIO0_57, |
| 606 | PINCTRL_GRP_GPIO0_58, |
| 607 | PINCTRL_GRP_GPIO0_59, |
| 608 | PINCTRL_GRP_GPIO0_60, |
| 609 | PINCTRL_GRP_GPIO0_61, |
| 610 | PINCTRL_GRP_GPIO0_62, |
| 611 | PINCTRL_GRP_GPIO0_63, |
| 612 | PINCTRL_GRP_GPIO0_64, |
| 613 | PINCTRL_GRP_GPIO0_65, |
| 614 | PINCTRL_GRP_GPIO0_66, |
| 615 | PINCTRL_GRP_GPIO0_67, |
| 616 | PINCTRL_GRP_GPIO0_68, |
| 617 | PINCTRL_GRP_GPIO0_69, |
| 618 | PINCTRL_GRP_GPIO0_70, |
| 619 | PINCTRL_GRP_GPIO0_71, |
| 620 | PINCTRL_GRP_GPIO0_72, |
| 621 | PINCTRL_GRP_GPIO0_73, |
| 622 | PINCTRL_GRP_GPIO0_74, |
| 623 | PINCTRL_GRP_GPIO0_75, |
| 624 | PINCTRL_GRP_GPIO0_76, |
| 625 | PINCTRL_GRP_GPIO0_77, |
| 626 | PINCTRL_GRP_USB0_0, |
| 627 | PINCTRL_GRP_USB1_0, |
| 628 | PINCTRL_GRP_PMU0_0, |
| 629 | PINCTRL_GRP_PMU0_1, |
| 630 | PINCTRL_GRP_PMU0_2, |
| 631 | PINCTRL_GRP_PMU0_3, |
| 632 | PINCTRL_GRP_PMU0_4, |
| 633 | PINCTRL_GRP_PMU0_5, |
| 634 | PINCTRL_GRP_PMU0_6, |
| 635 | PINCTRL_GRP_PMU0_7, |
| 636 | PINCTRL_GRP_PMU0_8, |
| 637 | PINCTRL_GRP_PMU0_9, |
| 638 | PINCTRL_GRP_PMU0_10, |
| 639 | PINCTRL_GRP_PMU0_11, |
| 640 | PINCTRL_GRP_PCIE0_0, |
| 641 | PINCTRL_GRP_PCIE0_1, |
| 642 | PINCTRL_GRP_PCIE0_2, |
| 643 | PINCTRL_GRP_PCIE0_3, |
| 644 | PINCTRL_GRP_PCIE0_4, |
| 645 | PINCTRL_GRP_PCIE0_5, |
| 646 | PINCTRL_GRP_PCIE0_6, |
| 647 | PINCTRL_GRP_PCIE0_7, |
| 648 | PINCTRL_GRP_CSU0_0, |
| 649 | PINCTRL_GRP_CSU0_1, |
| 650 | PINCTRL_GRP_CSU0_2, |
| 651 | PINCTRL_GRP_CSU0_3, |
| 652 | PINCTRL_GRP_CSU0_4, |
| 653 | PINCTRL_GRP_CSU0_5, |
| 654 | PINCTRL_GRP_CSU0_6, |
| 655 | PINCTRL_GRP_CSU0_7, |
| 656 | PINCTRL_GRP_CSU0_8, |
| 657 | PINCTRL_GRP_CSU0_9, |
| 658 | PINCTRL_GRP_CSU0_10, |
| 659 | PINCTRL_GRP_CSU0_11, |
| 660 | PINCTRL_GRP_DPAUX0_0, |
| 661 | PINCTRL_GRP_DPAUX0_1, |
| 662 | PINCTRL_GRP_DPAUX0_2, |
| 663 | PINCTRL_GRP_DPAUX0_3, |
| 664 | PINCTRL_GRP_PJTAG0_0, |
| 665 | PINCTRL_GRP_PJTAG0_1, |
| 666 | PINCTRL_GRP_PJTAG0_2, |
| 667 | PINCTRL_GRP_PJTAG0_3, |
| 668 | PINCTRL_GRP_PJTAG0_4, |
| 669 | PINCTRL_GRP_PJTAG0_5, |
| 670 | PINCTRL_GRP_TRACE0_0, |
| 671 | PINCTRL_GRP_TRACE0_0_CLK, |
| 672 | PINCTRL_GRP_TRACE0_1, |
| 673 | PINCTRL_GRP_TRACE0_1_CLK, |
| 674 | PINCTRL_GRP_TRACE0_2, |
| 675 | PINCTRL_GRP_TRACE0_2_CLK, |
| 676 | PINCTRL_GRP_TESTSCAN0_0, |
| 677 | }; |
| 678 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 679 | // pinctrl config parameters |
| 680 | enum { |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 681 | PINCTRL_CONFIG_SLEW_RATE, |
| 682 | PINCTRL_CONFIG_BIAS_STATUS, |
| 683 | PINCTRL_CONFIG_PULL_CTRL, |
| 684 | PINCTRL_CONFIG_SCHMITT_CMOS, |
| 685 | PINCTRL_CONFIG_DRIVE_STRENGTH, |
| 686 | PINCTRL_CONFIG_VOLTAGE_STATUS, |
| 687 | PINCTRL_CONFIG_MAX, |
| 688 | }; |
| 689 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 690 | // pinctrl slew rate |
| 691 | #define PINCTRL_SLEW_RATE_FAST 0U |
| 692 | #define PINCTRL_SLEW_RATE_SLOW 1U |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 693 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 694 | // pinctrl bias status |
| 695 | #define PINCTRL_BIAS_DISABLE 0U |
| 696 | #define PINCTRL_BIAS_ENABLE 1U |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 697 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 698 | // pinctrl pull control |
| 699 | #define PINCTRL_BIAS_PULL_DOWN 0U |
| 700 | #define PINCTRL_BIAS_PULL_UP 1U |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 701 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 702 | // pinctrl schmitt cmos type |
| 703 | #define PINCTRL_INPUT_TYPE_CMOS 0U |
| 704 | #define PINCTRL_INPUT_TYPE_SCHMITT 1U |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 705 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 706 | //pinctrl drive strength values |
| 707 | #define PINCTRL_DRIVE_STRENGTH_2MA 0U |
| 708 | #define PINCTRL_DRIVE_STRENGTH_4MA 1U |
| 709 | #define PINCTRL_DRIVE_STRENGTH_8MA 2U |
| 710 | #define PINCTRL_DRIVE_STRENGTH_12MA 3U |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 711 | |
Rajan Vaja | cd82568 | 2020-11-23 21:33:39 -0800 | [diff] [blame] | 712 | void pm_api_pinctrl_get_function_name(unsigned int fid, char *name); |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 713 | enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, |
| 714 | unsigned int index, |
| 715 | uint16_t *groups); |
| 716 | enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, |
| 717 | unsigned int index, |
| 718 | uint16_t *groups); |
| 719 | enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins); |
| 720 | enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs); |
| 721 | enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, |
| 722 | unsigned int *ngroups); |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 723 | #endif /* PM_API_PINCTRL_H */ |