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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arm_def.h>
Daniel Boulby45a2c9e2018-07-06 16:54:44 +01008#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +00009#include <bl_common.h>
10#include <console.h>
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010011#include <debug.h>
12#include <pl011.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010013#include <plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000014#include <platform_def.h>
15#include <platform_tsp.h>
Dan Handley9df48042015-03-19 18:58:55 +000016
Dan Handley9df48042015-03-19 18:58:55 +000017#define BL32_END (unsigned long)(&__BL32_END__)
18
Dan Handley9df48042015-03-19 18:58:55 +000019/* Weak definitions may be overridden in specific ARM standard platform */
20#pragma weak tsp_early_platform_setup
21#pragma weak tsp_platform_setup
22#pragma weak tsp_plat_arch_setup
23
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010024#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \
25 BL32_BASE, \
26 BL32_END - BL32_BASE, \
27 MT_MEMORY | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +000028
29/*******************************************************************************
30 * Initialize the UART
31 ******************************************************************************/
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010032#if MULTI_CONSOLE_API
33static console_pl011_t arm_tsp_runtime_console;
34#endif
35
Dan Handley9df48042015-03-19 18:58:55 +000036void arm_tsp_early_platform_setup(void)
37{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010038#if MULTI_CONSOLE_API
Dan Handley9df48042015-03-19 18:58:55 +000039 /*
40 * Initialize a different console than already in use to display
41 * messages from TSP
42 */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010043 int rc = console_pl011_register(PLAT_ARM_TSP_UART_BASE,
44 PLAT_ARM_TSP_UART_CLK_IN_HZ,
45 ARM_CONSOLE_BAUDRATE,
46 &arm_tsp_runtime_console);
47 if (rc == 0)
48 panic();
49
50 console_set_scope(&arm_tsp_runtime_console.console,
51 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
52#else
Dan Handley9df48042015-03-19 18:58:55 +000053 console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
54 ARM_CONSOLE_BAUDRATE);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010055#endif /* MULTI_CONSOLE_API */
Dan Handley9df48042015-03-19 18:58:55 +000056}
57
58void tsp_early_platform_setup(void)
59{
60 arm_tsp_early_platform_setup();
61}
62
63/*******************************************************************************
64 * Perform platform specific setup placeholder
65 ******************************************************************************/
66void tsp_platform_setup(void)
67{
Achin Gupta1fa7eb62015-11-03 14:18:34 +000068 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +000069}
70
71/*******************************************************************************
72 * Perform the very early platform specific architectural setup here. At the
73 * moment this is only intializes the MMU
74 ******************************************************************************/
75void tsp_plat_arch_setup(void)
76{
Dan Handley9df48042015-03-19 18:58:55 +000077#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010078 /* Ensure ARM platforms dont use coherent memory in TSP */
79 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +000080#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010081
82 const mmap_region_t bl_regions[] = {
83 MAP_BL_TSP_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +010084 ARM_MAP_BL_RO,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010085 {0}
86 };
87
88 arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010089 enable_mmu_el1(0);
Dan Handley9df48042015-03-19 18:58:55 +000090}