Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 1 | /* |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2019-2022, Arm Limited. All rights reserved. |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 8 | |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 9 | /dts-v1/; |
| 10 | |
| 11 | / { |
| 12 | model = "V2P-CA5s"; |
| 13 | compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; |
| 14 | interrupt-parent = <&gic>; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 15 | #address-cells = <2>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 16 | #size-cells = <1>; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; |
| 21 | |
| 22 | cpu@0 { |
| 23 | device_type = "cpu"; |
| 24 | compatible = "arm,cortex-a5"; |
| 25 | reg = <0>; |
| 26 | }; |
| 27 | |
| 28 | }; |
| 29 | |
| 30 | memory@80000000 { |
| 31 | device_type = "memory"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 32 | reg = <0 0x80000000 0x1000000>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | hdlcd@2a110000 { |
| 36 | compatible = "arm,hdlcd"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 37 | reg = <0 0x2a110000 0x1000>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 38 | interrupts = <0 85 4>; |
| 39 | clocks = <&oscclk3>; |
| 40 | clock-names = "pxlclk"; |
| 41 | }; |
| 42 | |
| 43 | scu@2c000000 { |
| 44 | compatible = "arm,cortex-a5-scu"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 45 | reg = <0 0x2c000000 0x58>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | watchdog@2c000620 { |
| 49 | compatible = "arm,cortex-a5-twd-wdt"; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 50 | reg = <0 0x2c000620 0x20>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 51 | interrupts = <1 14 0x304>; |
| 52 | }; |
| 53 | |
| 54 | gic: interrupt-controller@2c001000 { |
| 55 | compatible = "arm,cortex-a9-gic"; |
| 56 | #interrupt-cells = <3>; |
| 57 | #address-cells = <0>; |
| 58 | interrupt-controller; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 59 | reg = <0 0x2c001000 0x1000>, |
| 60 | <0 0x2c000100 0x100>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | dcc { |
| 64 | compatible = "arm,vexpress,config-bus"; |
| 65 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 66 | |
| 67 | oscclk0: osc@0 { |
| 68 | /* CPU and internal AXI reference clock */ |
| 69 | compatible = "arm,vexpress-osc"; |
| 70 | arm,vexpress-sysreg,func = <1 0>; |
| 71 | freq-range = <50000000 100000000>; |
| 72 | #clock-cells = <0>; |
| 73 | clock-output-names = "oscclk0"; |
| 74 | }; |
| 75 | |
| 76 | oscclk1: osc@1 { |
| 77 | /* Multiplexed AXI master clock */ |
| 78 | compatible = "arm,vexpress-osc"; |
| 79 | arm,vexpress-sysreg,func = <1 1>; |
| 80 | freq-range = <5000000 50000000>; |
| 81 | #clock-cells = <0>; |
| 82 | clock-output-names = "oscclk1"; |
| 83 | }; |
| 84 | |
| 85 | osc@2 { |
| 86 | /* DDR2 */ |
| 87 | compatible = "arm,vexpress-osc"; |
| 88 | arm,vexpress-sysreg,func = <1 2>; |
| 89 | freq-range = <80000000 120000000>; |
| 90 | #clock-cells = <0>; |
| 91 | clock-output-names = "oscclk2"; |
| 92 | }; |
| 93 | |
| 94 | oscclk3: osc@3 { |
| 95 | /* HDLCD */ |
| 96 | compatible = "arm,vexpress-osc"; |
| 97 | arm,vexpress-sysreg,func = <1 3>; |
| 98 | freq-range = <23750000 165000000>; |
| 99 | #clock-cells = <0>; |
| 100 | clock-output-names = "oscclk3"; |
| 101 | }; |
| 102 | |
| 103 | osc@4 { |
| 104 | /* Test chip gate configuration */ |
| 105 | compatible = "arm,vexpress-osc"; |
| 106 | arm,vexpress-sysreg,func = <1 4>; |
| 107 | freq-range = <80000000 80000000>; |
| 108 | #clock-cells = <0>; |
| 109 | clock-output-names = "oscclk4"; |
| 110 | }; |
| 111 | |
| 112 | smbclk: osc@5 { |
| 113 | /* SMB clock */ |
| 114 | compatible = "arm,vexpress-osc"; |
| 115 | arm,vexpress-sysreg,func = <1 5>; |
| 116 | freq-range = <25000000 60000000>; |
| 117 | #clock-cells = <0>; |
| 118 | clock-output-names = "oscclk5"; |
| 119 | }; |
| 120 | }; |
| 121 | |
| 122 | smb { |
| 123 | compatible = "simple-bus"; |
| 124 | |
| 125 | #address-cells = <2>; |
| 126 | #size-cells = <1>; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 127 | ranges = <0 0 0 0x08000000 0x04000000>, |
| 128 | <1 0 0 0x14000000 0x04000000>, |
| 129 | <2 0 0 0x18000000 0x04000000>, |
| 130 | <3 0 0 0x1c000000 0x04000000>, |
| 131 | <4 0 0 0x0c000000 0x04000000>, |
| 132 | <5 0 0 0x10000000 0x04000000>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 133 | |
| 134 | #interrupt-cells = <1>; |
| 135 | interrupt-map-mask = <0 0 63>; |
Andre Przywara | 14f5dab | 2022-08-25 12:59:10 +0100 | [diff] [blame^] | 136 | interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 137 | <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 138 | <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 139 | <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 140 | <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 141 | <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| 142 | <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 143 | <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 144 | <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 145 | <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 146 | <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| 147 | <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 148 | <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 149 | <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 150 | <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 151 | <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 152 | <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| 154 | <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 155 | |
Balint Dobszay | 5ce2c32 | 2020-01-10 17:16:27 +0100 | [diff] [blame] | 156 | #include "rtsm_ve-motherboard-aarch32.dtsi" |
Usama Arif | 078e66f | 2018-12-12 17:14:29 +0000 | [diff] [blame] | 157 | }; |
| 158 | }; |