fdts/fvp-ve-Cortex-A5x1.dts

/*
 * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/dts-v1/;

/ {
	model = "V2P-CA5s";
	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
		};

	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0x1000000>;
	};

	hdlcd@2a110000 {
		compatible = "arm,hdlcd";
		reg = <0 0x2a110000 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&oscclk3>;
		clock-names = "pxlclk";
	};

	scu@2c000000 {
		compatible = "arm,cortex-a5-scu";
		reg = <0 0x2c000000 0x58>;
	};

	watchdog@2c000620 {
		compatible = "arm,cortex-a5-twd-wdt";
		reg = <0 0x2c000620 0x20>;
		interrupts = <1 14 0x304>;
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0x1000>,
		      <0 0x2c000100 0x100>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0: osc@0 {
			/* CPU and internal AXI reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <50000000 100000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		oscclk1: osc@1 {
			/* Multiplexed AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <5000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk1";
		};

		osc@2 {
			/* DDR2 */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <80000000 120000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk2";
		};

		oscclk3: osc@3 {
			/* HDLCD */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 3>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk3";
		};

		osc@4 {
			/* Test chip gate configuration */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <80000000 80000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		smbclk: osc@5 {
			/* SMB clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <25000000 60000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};
	};

	smb {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

		#include "rtsm_ve-motherboard-aarch32.dtsi"
	};
};