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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Soby Mathew12012dd2015-10-26 14:01:53 +00009#include <gicv2.h>
10#include <gicv3.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010011#include <platform_def.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000012#include <v2m_def.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010013#include "../drivers/pwrc/fvp_pwrc.h"
Dan Handley2b6b5742015-03-19 19:17:53 +000014#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
Vikram Kanigiri96377452014-04-24 11:02:16 +010016 .globl plat_secondary_cold_boot_setup
Soby Mathewfec4eb72015-07-01 16:16:20 +010017 .globl plat_get_my_entrypoint
Soby Mathewfec4eb72015-07-01 16:16:20 +010018 .globl plat_is_my_cpu_primary
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
Dan Handleyea451572014-05-15 14:53:30 +010020 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
Dan Handley2b6b5742015-03-19 19:17:53 +000021 ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
Vikram Kanigiri96377452014-04-24 11:02:16 +010022 ldr \w_tmp, [\x_tmp]
Dan Handley2b6b5742015-03-19 19:17:53 +000023 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
Vikram Kanigiri96377452014-04-24 11:02:16 +010024 cmp \w_tmp, #BLD_GIC_VE_MMAP
25 csel \res, \param1, \param2, eq
26 .endm
27
28 /* -----------------------------------------------------
29 * void plat_secondary_cold_boot_setup (void);
30 *
31 * This function performs any platform specific actions
32 * needed for a secondary cpu after a cold reset e.g
33 * mark the cpu's presence, mechanism to place it in a
34 * holding pen etc.
35 * TODO: Should we read the PSYS register to make sure
36 * that the request has gone through.
37 * -----------------------------------------------------
38 */
39func plat_secondary_cold_boot_setup
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +010040#ifndef EL3_PAYLOAD_BASE
Vikram Kanigiri96377452014-04-24 11:02:16 +010041 /* ---------------------------------------------
42 * Power down this cpu.
43 * TODO: Do we need to worry about powering the
44 * cluster down as well here. That will need
45 * locks which we won't have unless an elf-
46 * loader zeroes out the zi section.
47 * ---------------------------------------------
48 */
49 mrs x0, mpidr_el1
50 ldr x1, =PWRC_BASE
51 str w0, [x1, #PPOFFR_OFF]
52
53 /* ---------------------------------------------
Soby Mathew12012dd2015-10-26 14:01:53 +000054 * Disable GIC bypass as well
Vikram Kanigiri96377452014-04-24 11:02:16 +010055 * ---------------------------------------------
56 */
Soby Mathew12012dd2015-10-26 14:01:53 +000057 /* Check for GICv3 system register access */
58 mrs x0, id_aa64pfr0_el1
59 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
60 cmp x0, #1
61 b.ne gicv2_bypass_disable
62
63 /* Check for SRE enable */
64 mrs x1, ICC_SRE_EL3
65 tst x1, #ICC_SRE_SRE_BIT
66 b.eq gicv2_bypass_disable
67
68 mrs x2, ICC_SRE_EL3
69 orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
70 msr ICC_SRE_EL3, x2
71 b secondary_cold_boot_wait
72
73gicv2_bypass_disable:
Vikram Kanigiri96377452014-04-24 11:02:16 +010074 ldr x0, =VE_GICC_BASE
75 ldr x1, =BASE_GICC_BASE
Dan Handleyea451572014-05-15 14:53:30 +010076 fvp_choose_gicmmap x0, x1, x2, w2, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +010077 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
78 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
79 str w0, [x1, #GICC_CTLR]
80
Soby Mathew12012dd2015-10-26 14:01:53 +000081secondary_cold_boot_wait:
Vikram Kanigiri96377452014-04-24 11:02:16 +010082 /* ---------------------------------------------
83 * There is no sane reason to come out of this
84 * wfi so panic if we do. This cpu will be pow-
85 * ered on and reset by the cpu_on pm api
86 * ---------------------------------------------
87 */
88 dsb sy
89 wfi
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000090 no_ret plat_panic_handler
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +010091#else
92 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
93
94 /* Wait until the entrypoint gets populated */
95poll_mailbox:
96 ldr x1, [x0]
97 cbz x1, 1f
98 br x1
991:
100 wfe
101 b poll_mailbox
102#endif /* EL3_PAYLOAD_BASE */
Kévin Petita877c252015-03-24 14:03:57 +0000103endfunc plat_secondary_cold_boot_setup
Vikram Kanigiri96377452014-04-24 11:02:16 +0100104
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100105 /* ---------------------------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +0100106 * uintptr_t plat_get_my_entrypoint (void);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100107 *
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100108 * Main job of this routine is to distinguish between a cold and warm
109 * boot. On FVP, this information can be queried from the power
110 * controller. The Power Control SYS Status Register (PSYSR) indicates
111 * the wake-up reason for the CPU.
112 *
113 * For a cold boot, return 0.
114 * For a warm boot, read the mailbox and return the address it contains.
Vikram Kanigiri96377452014-04-24 11:02:16 +0100115 *
Vikram Kanigiri96377452014-04-24 11:02:16 +0100116 * TODO: PSYSR is a common register and should be
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000117 * accessed using locks. Since it is not possible
Vikram Kanigiri96377452014-04-24 11:02:16 +0100118 * to use locks immediately after a cold reset
119 * we are relying on the fact that after a cold
120 * reset all cpus will read the same WK field
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100121 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100122 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100123func plat_get_my_entrypoint
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100124 /* ---------------------------------------------------------------------
125 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
126 * WakeRequest signal" then it is a warm boot.
127 * ---------------------------------------------------------------------
128 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100129 mrs x2, mpidr_el1
Vikram Kanigiri96377452014-04-24 11:02:16 +0100130 ldr x1, =PWRC_BASE
131 str w2, [x1, #PSYSR_OFF]
132 ldr w2, [x1, #PSYSR_OFF]
Soby Mathew2ae23192015-04-30 12:27:41 +0100133 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100134 cmp w2, #WKUP_PPONR
135 beq warm_reset
136 cmp w2, #WKUP_GICREQ
137 beq warm_reset
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100138
139 /* Cold reset */
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100140 mov x0, #0
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100141 ret
142
Vikram Kanigiri96377452014-04-24 11:02:16 +0100143warm_reset:
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100144 /* ---------------------------------------------------------------------
145 * A mailbox is maintained in the trusted SRAM. It is flushed out of the
146 * caches after every update using normal memory so it is safe to read
147 * it here with SO attributes.
148 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100149 */
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100150 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100151 ldr x0, [x0]
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000152 cbz x0, _panic_handler
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100153 ret
154
155 /* ---------------------------------------------------------------------
156 * The power controller indicates this is a warm reset but the mailbox
157 * is empty. This should never happen!
158 * ---------------------------------------------------------------------
159 */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000160_panic_handler:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000161 no_ret plat_panic_handler
Soby Mathewfec4eb72015-07-01 16:16:20 +0100162endfunc plat_get_my_entrypoint
Vikram Kanigiri96377452014-04-24 11:02:16 +0100163
Soby Matheweb3bbf12015-06-08 12:32:50 +0100164 /* -----------------------------------------------------
165 * unsigned int plat_is_my_cpu_primary (void);
166 *
167 * Find out whether the current cpu is the primary
168 * cpu.
169 * -----------------------------------------------------
170 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100171func plat_is_my_cpu_primary
172 mrs x0, mpidr_el1
Juan Castillob3dbeb02014-07-16 15:53:43 +0100173 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
174 cmp x0, #FVP_PRIMARY_CPU
Soby Matheweb3bbf12015-06-08 12:32:50 +0100175 cset w0, eq
Juan Castillob3dbeb02014-07-16 15:53:43 +0100176 ret
Soby Mathewfec4eb72015-07-01 16:16:20 +0100177endfunc plat_is_my_cpu_primary