Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __SOC_CSS_DEF_H__ |
| 8 | #define __SOC_CSS_DEF_H__ |
| 9 | |
| 10 | #include <common_def.h> |
Scott Branden | bf404c0 | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 11 | #include <utils_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 12 | |
| 13 | |
| 14 | /* |
| 15 | * Definitions common to all ARM CSS SoCs |
| 16 | */ |
| 17 | |
| 18 | /* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ |
| 19 | #define SOC_CSS_DEVICE_BASE 0x40000000 |
| 20 | #define SOC_CSS_DEVICE_SIZE 0x40000000 |
| 21 | #define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 |
| 22 | |
| 23 | /* PL011 UART related constants */ |
| 24 | #define SOC_CSS_UART0_BASE 0x7ff80000 |
| 25 | #define SOC_CSS_UART1_BASE 0x7ff70000 |
| 26 | |
| 27 | #define SOC_CSS_UART0_CLK_IN_HZ 7273800 |
| 28 | #define SOC_CSS_UART1_CLK_IN_HZ 7273800 |
| 29 | |
| 30 | /* SoC NIC-400 Global Programmers View (GPV) */ |
| 31 | #define SOC_CSS_NIC400_BASE 0x7fd00000 |
| 32 | |
| 33 | #define SOC_CSS_NIC400_USB_EHCI 0 |
| 34 | #define SOC_CSS_NIC400_TLX_MASTER 1 |
| 35 | #define SOC_CSS_NIC400_USB_OHCI 2 |
| 36 | #define SOC_CSS_NIC400_PL354_SMC 3 |
| 37 | /* |
| 38 | * The apb4_bridge controls access to: |
| 39 | * - the PCIe configuration registers |
| 40 | * - the MMU units for USB, HDLCD and DMA |
| 41 | */ |
| 42 | #define SOC_CSS_NIC400_APB4_BRIDGE 4 |
| 43 | |
Juan Castillo | bfb7fa6 | 2016-01-22 11:05:57 +0000 | [diff] [blame] | 44 | /* Non-volatile counters */ |
| 45 | #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 |
| 46 | #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) |
| 47 | #define TFW_NVCTR_SIZE 4 |
| 48 | #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) |
| 49 | #define NTFW_CTR_SIZE 4 |
| 50 | |
Juan Castillo | 31a68f0 | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 51 | /* Keys */ |
| 52 | #define SOC_KEYS_BASE 0x7fe80000 |
| 53 | #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) |
| 54 | #define TZ_PUB_KEY_HASH_SIZE 32 |
| 55 | #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) |
| 56 | #define HU_KEY_SIZE 16 |
| 57 | #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) |
| 58 | #define END_KEY_SIZE 32 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 59 | |
| 60 | #define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ |
| 61 | SOC_CSS_DEVICE_BASE, \ |
| 62 | SOC_CSS_DEVICE_SIZE, \ |
| 63 | MT_DEVICE | MT_RW | MT_SECURE) |
| 64 | |
| 65 | |
| 66 | /* |
| 67 | * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. |
| 68 | */ |
| 69 | #define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 |
| 70 | #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) |
| 71 | |
| 72 | /* |
| 73 | * Required platform porting definitions common to all ARM CSS SoCs |
| 74 | */ |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 75 | #if JUNO_AARCH32_EL3_RUNTIME |
| 76 | /* |
| 77 | * Following change is required to initialize TZC |
| 78 | * for enabling access to the HI_VECTOR (0xFFFF0000) |
| 79 | * location needed for JUNO AARCH32 support. |
| 80 | */ |
| 81 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) |
| 82 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 83 | /* 2MB used for SCP DDR retraining */ |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 84 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 85 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 86 | |
| 87 | #endif /* __SOC_CSS_DEF_H__ */ |