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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __SOC_CSS_DEF_H__
32#define __SOC_CSS_DEF_H__
33
34#include <common_def.h>
35#include <xlat_tables.h>
36
37
38/*
39 * Definitions common to all ARM CSS SoCs
40 */
41
42/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
43#define SOC_CSS_DEVICE_BASE 0x40000000
44#define SOC_CSS_DEVICE_SIZE 0x40000000
45#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000
46
47/* PL011 UART related constants */
48#define SOC_CSS_UART0_BASE 0x7ff80000
49#define SOC_CSS_UART1_BASE 0x7ff70000
50
51#define SOC_CSS_UART0_CLK_IN_HZ 7273800
52#define SOC_CSS_UART1_CLK_IN_HZ 7273800
53
54/* SoC NIC-400 Global Programmers View (GPV) */
55#define SOC_CSS_NIC400_BASE 0x7fd00000
56
57#define SOC_CSS_NIC400_USB_EHCI 0
58#define SOC_CSS_NIC400_TLX_MASTER 1
59#define SOC_CSS_NIC400_USB_OHCI 2
60#define SOC_CSS_NIC400_PL354_SMC 3
61/*
62 * The apb4_bridge controls access to:
63 * - the PCIe configuration registers
64 * - the MMU units for USB, HDLCD and DMA
65 */
66#define SOC_CSS_NIC400_APB4_BRIDGE 4
67
68
69#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \
70 SOC_CSS_DEVICE_BASE, \
71 SOC_CSS_DEVICE_SIZE, \
72 MT_DEVICE | MT_RW | MT_SECURE)
73
74
75/*
76 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
77 */
78#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5
79#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
80
81/*
82 * Required platform porting definitions common to all ARM CSS SoCs
83 */
84
85/* 2MB used for SCP DDR retraining */
86#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000)
87
88
89#endif /* __SOC_CSS_DEF_H__ */