Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <assert.h> |
| 10 | #include <console.h> |
| 11 | #include <debug.h> |
| 12 | #include <marvell_def.h> |
| 13 | #include <marvell_plat_priv.h> |
| 14 | #include <plat_marvell.h> |
| 15 | #include <platform.h> |
| 16 | |
| 17 | #ifdef USE_CCI |
| 18 | #include <cci.h> |
| 19 | #endif |
| 20 | |
| 21 | /* |
| 22 | * The next 3 constants identify the extents of the code, RO data region and the |
| 23 | * limit of the BL31 image. These addresses are used by the MMU setup code and |
| 24 | * therefore they must be page-aligned. It is the responsibility of the linker |
| 25 | * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols |
| 26 | * refer to page-aligned addresses. |
| 27 | */ |
| 28 | #define BL31_END (unsigned long)(&__BL31_END__) |
| 29 | |
| 30 | /* |
| 31 | * Placeholder variables for copying the arguments that have been passed to |
| 32 | * BL31 from BL2. |
| 33 | */ |
| 34 | static entry_point_info_t bl32_image_ep_info; |
| 35 | static entry_point_info_t bl33_image_ep_info; |
| 36 | |
| 37 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Konstantin Porotchkin | acb1dc1 | 2018-08-19 10:07:35 +0300 | [diff] [blame] | 38 | #pragma weak bl31_early_platform_setup2 |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 39 | #pragma weak bl31_platform_setup |
| 40 | #pragma weak bl31_plat_arch_setup |
| 41 | #pragma weak bl31_plat_get_next_image_ep_info |
| 42 | #pragma weak plat_get_syscnt_freq2 |
| 43 | |
| 44 | /***************************************************************************** |
| 45 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 46 | * the security state specified. BL33 corresponds to the non-secure image type |
| 47 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 48 | * if the image does not exist. |
| 49 | ***************************************************************************** |
| 50 | */ |
| 51 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 52 | { |
| 53 | entry_point_info_t *next_image_info; |
| 54 | |
| 55 | assert(sec_state_is_valid(type)); |
| 56 | next_image_info = (type == NON_SECURE) |
| 57 | ? &bl33_image_ep_info : &bl32_image_ep_info; |
| 58 | |
| 59 | return next_image_info; |
| 60 | } |
| 61 | |
| 62 | /***************************************************************************** |
| 63 | * Perform any BL31 early platform setup common to ARM standard platforms. |
| 64 | * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 |
| 65 | * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be |
| 66 | * done before the MMU is initialized so that the memory layout can be used |
| 67 | * while creating page tables. BL2 has flushed this information to memory, so |
| 68 | * we are guaranteed to pick up good data. |
| 69 | ***************************************************************************** |
| 70 | */ |
| 71 | void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2, |
Konstantin Porotchkin | acb1dc1 | 2018-08-19 10:07:35 +0300 | [diff] [blame] | 72 | uintptr_t soc_fw_config, |
| 73 | uintptr_t hw_config, |
| 74 | void *plat_params_from_bl2) |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 75 | { |
| 76 | /* Initialize the console to provide early debug support */ |
| 77 | console_init(PLAT_MARVELL_BOOT_UART_BASE, |
| 78 | PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, |
| 79 | MARVELL_CONSOLE_BAUDRATE); |
| 80 | |
| 81 | #if RESET_TO_BL31 |
| 82 | /* There are no parameters from BL2 if BL31 is a reset vector */ |
| 83 | assert(from_bl2 == NULL); |
| 84 | assert(plat_params_from_bl2 == NULL); |
| 85 | |
| 86 | #ifdef BL32_BASE |
| 87 | /* Populate entry point information for BL32 */ |
| 88 | SET_PARAM_HEAD(&bl32_image_ep_info, |
| 89 | PARAM_EP, |
| 90 | VERSION_1, |
| 91 | 0); |
| 92 | SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
| 93 | bl32_image_ep_info.pc = BL32_BASE; |
| 94 | bl32_image_ep_info.spsr = marvell_get_spsr_for_bl32_entry(); |
| 95 | #endif /* BL32_BASE */ |
| 96 | |
| 97 | /* Populate entry point information for BL33 */ |
| 98 | SET_PARAM_HEAD(&bl33_image_ep_info, |
| 99 | PARAM_EP, |
| 100 | VERSION_1, |
| 101 | 0); |
| 102 | /* |
| 103 | * Tell BL31 where the non-trusted software image |
| 104 | * is located and the entry state information |
| 105 | */ |
| 106 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
| 107 | bl33_image_ep_info.spsr = marvell_get_spsr_for_bl33_entry(); |
| 108 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| 109 | |
| 110 | #else |
| 111 | /* |
| 112 | * Check params passed from BL2 should not be NULL, |
| 113 | */ |
| 114 | assert(from_bl2 != NULL); |
| 115 | assert(from_bl2->h.type == PARAM_BL31); |
| 116 | assert(from_bl2->h.version >= VERSION_1); |
| 117 | /* |
| 118 | * In debug builds, we pass a special value in 'plat_params_from_bl2' |
| 119 | * to verify platform parameters from BL2 to BL31. |
| 120 | * In release builds, it's not used. |
| 121 | */ |
| 122 | assert(((unsigned long long)plat_params_from_bl2) == |
| 123 | MARVELL_BL31_PLAT_PARAM_VAL); |
| 124 | |
| 125 | /* |
| 126 | * Copy BL32 (if populated by BL2) and BL33 entry point information. |
| 127 | * They are stored in Secure RAM, in BL2's address space. |
| 128 | */ |
| 129 | if (from_bl2->bl32_ep_info) |
| 130 | bl32_image_ep_info = *from_bl2->bl32_ep_info; |
| 131 | bl33_image_ep_info = *from_bl2->bl33_ep_info; |
| 132 | #endif |
| 133 | } |
| 134 | |
Konstantin Porotchkin | acb1dc1 | 2018-08-19 10:07:35 +0300 | [diff] [blame] | 135 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 136 | u_register_t arg2, u_register_t arg3) |
| 137 | |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 138 | { |
Konstantin Porotchkin | acb1dc1 | 2018-08-19 10:07:35 +0300 | [diff] [blame] | 139 | marvell_bl31_early_platform_setup((void *)arg0, arg1, arg2, |
| 140 | (void *)arg3); |
Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 141 | |
| 142 | #ifdef USE_CCI |
| 143 | /* |
| 144 | * Initialize CCI for this cluster during cold boot. |
| 145 | * No need for locks as no other CPU is active. |
| 146 | */ |
| 147 | plat_marvell_interconnect_init(); |
| 148 | |
| 149 | /* |
| 150 | * Enable CCI coherency for the primary CPU's cluster. |
| 151 | * Platform specific PSCI code will enable coherency for other |
| 152 | * clusters. |
| 153 | */ |
| 154 | plat_marvell_interconnect_enter_coherency(); |
| 155 | #endif |
| 156 | } |
| 157 | |
| 158 | /***************************************************************************** |
| 159 | * Perform any BL31 platform setup common to ARM standard platforms |
| 160 | ***************************************************************************** |
| 161 | */ |
| 162 | void marvell_bl31_platform_setup(void) |
| 163 | { |
| 164 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 165 | plat_marvell_gic_driver_init(); |
| 166 | plat_marvell_gic_init(); |
| 167 | |
| 168 | /* For Armada-8k-plus family, the SoC includes more than |
| 169 | * a single AP die, but the default die that boots is AP #0. |
| 170 | * For other families there is only one die (#0). |
| 171 | * Initialize psci arch from die 0 |
| 172 | */ |
| 173 | marvell_psci_arch_init(0); |
| 174 | } |
| 175 | |
| 176 | /***************************************************************************** |
| 177 | * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM |
| 178 | * standard platforms |
| 179 | ***************************************************************************** |
| 180 | */ |
| 181 | void marvell_bl31_plat_runtime_setup(void) |
| 182 | { |
| 183 | /* Initialize the runtime console */ |
| 184 | console_init(PLAT_MARVELL_BL31_RUN_UART_BASE, |
| 185 | PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ, |
| 186 | MARVELL_CONSOLE_BAUDRATE); |
| 187 | } |
| 188 | |
| 189 | void bl31_platform_setup(void) |
| 190 | { |
| 191 | marvell_bl31_platform_setup(); |
| 192 | } |
| 193 | |
| 194 | void bl31_plat_runtime_setup(void) |
| 195 | { |
| 196 | marvell_bl31_plat_runtime_setup(); |
| 197 | } |
| 198 | |
| 199 | /***************************************************************************** |
| 200 | * Perform the very early platform specific architectural setup shared between |
| 201 | * ARM standard platforms. This only does basic initialization. Later |
| 202 | * architectural setup (bl31_arch_setup()) does not do anything platform |
| 203 | * specific. |
| 204 | ***************************************************************************** |
| 205 | */ |
| 206 | void marvell_bl31_plat_arch_setup(void) |
| 207 | { |
| 208 | marvell_setup_page_tables(BL31_BASE, |
| 209 | BL31_END - BL31_BASE, |
| 210 | BL_CODE_BASE, |
| 211 | BL_CODE_END, |
| 212 | BL_RO_DATA_BASE, |
| 213 | BL_RO_DATA_END |
| 214 | #if USE_COHERENT_MEM |
| 215 | , BL_COHERENT_RAM_BASE, |
| 216 | BL_COHERENT_RAM_END |
| 217 | #endif |
| 218 | ); |
| 219 | |
| 220 | #if BL31_CACHE_DISABLE |
| 221 | enable_mmu_el3(DISABLE_DCACHE); |
| 222 | INFO("Cache is disabled in BL3\n"); |
| 223 | #else |
| 224 | enable_mmu_el3(0); |
| 225 | #endif |
| 226 | } |
| 227 | |
| 228 | void bl31_plat_arch_setup(void) |
| 229 | { |
| 230 | marvell_bl31_plat_arch_setup(); |
| 231 | } |
| 232 | |
| 233 | unsigned int plat_get_syscnt_freq2(void) |
| 234 | { |
| 235 | return PLAT_REF_CLK_IN_HZ; |
| 236 | } |