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Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Yann Gautier66386952018-07-05 16:49:51 +02006/dts-v1/;
7
8#include "stm32mp157c.dtsi"
9#include "stm32mp157caa-pinctrl.dtsi"
10
11/ {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010012 model = "STMicroelectronics STM32MP157C eval daughter";
Yann Gautier66386952018-07-05 16:49:51 +020013 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
14
15 chosen {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010016 stdout-path = "serial0:115200n8";
Yann Gautier66386952018-07-05 16:49:51 +020017 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010018
19 aliases {
20 serial0 = &uart4;
21 };
22};
23
24&clk_hse {
25 st,digbypass;
Yann Gautier66386952018-07-05 16:49:51 +020026};
27
28&i2c4 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&i2c4_pins_a>;
31 i2c-scl-rising-time-ns = <185>;
32 i2c-scl-falling-time-ns = <20>;
33 status = "okay";
34
Yann Gautiera45433b2019-01-16 18:31:00 +010035 pmic: stpmic@33 {
36 compatible = "st,stpmic1";
Yann Gautier66386952018-07-05 16:49:51 +020037 reg = <0x33>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010038 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
Yann Gautier66386952018-07-05 16:49:51 +020041 status = "okay";
42
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010043 st,main-control-register = <0x04>;
44 st,vin-control-register = <0xc0>;
45 st,usb-control-register = <0x30>;
Yann Gautier66386952018-07-05 16:49:51 +020046
47 regulators {
Yann Gautiera45433b2019-01-16 18:31:00 +010048 compatible = "st,stpmic1-regulators";
Yann Gautier66386952018-07-05 16:49:51 +020049
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010050 ldo1-supply = <&v3v3>;
51 ldo2-supply = <&v3v3>;
52 ldo3-supply = <&vdd_ddr>;
53 ldo5-supply = <&v3v3>;
54 ldo6-supply = <&v3v3>;
55
56 vddcore: buck1 {
57 regulator-name = "vddcore";
Yann Gautierf3928f62019-02-14 11:15:03 +010058 regulator-min-microvolt = <1200000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010059 regulator-max-microvolt = <1350000>;
60 regulator-always-on;
61 regulator-initial-mode = <0>;
62 regulator-over-current-protection;
63 };
64
65 vdd_ddr: buck2 {
66 regulator-name = "vdd_ddr";
67 regulator-min-microvolt = <1350000>;
68 regulator-max-microvolt = <1350000>;
69 regulator-always-on;
70 regulator-initial-mode = <0>;
71 regulator-over-current-protection;
72 };
73
74 vdd: buck3 {
75 regulator-name = "vdd";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 st,mask-reset;
80 regulator-initial-mode = <0>;
81 regulator-over-current-protection;
82 };
83
Yann Gautier66386952018-07-05 16:49:51 +020084 v3v3: buck4 {
85 regulator-name = "v3v3";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010088 regulator-always-on;
Yann Gautier66386952018-07-05 16:49:51 +020089 regulator-over-current-protection;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010090 regulator-initial-mode = <0>;
91 };
92
93 vdda: ldo1 {
94 regulator-name = "vdda";
95 regulator-min-microvolt = <2900000>;
96 regulator-max-microvolt = <2900000>;
97 };
Yann Gautier66386952018-07-05 16:49:51 +020098
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010099 v2v8: ldo2 {
100 regulator-name = "v2v8";
101 regulator-min-microvolt = <2800000>;
102 regulator-max-microvolt = <2800000>;
Yann Gautier66386952018-07-05 16:49:51 +0200103 };
104
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100105 vtt_ddr: ldo3 {
106 regulator-name = "vtt_ddr";
107 regulator-min-microvolt = <500000>;
108 regulator-max-microvolt = <750000>;
109 regulator-always-on;
110 regulator-over-current-protection;
111 };
112
113 vdd_usb: ldo4 {
114 regulator-name = "vdd_usb";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 };
118
Yann Gautier66386952018-07-05 16:49:51 +0200119 vdd_sd: ldo5 {
120 regulator-name = "vdd_sd";
121 regulator-min-microvolt = <2900000>;
122 regulator-max-microvolt = <2900000>;
123 regulator-boot-on;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100124 };
Yann Gautier66386952018-07-05 16:49:51 +0200125
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100126 v1v8: ldo6 {
127 regulator-name = "v1v8";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 };
131
132 vref_ddr: vref_ddr {
133 regulator-name = "vref_ddr";
134 regulator-always-on;
135 regulator-over-current-protection;
Yann Gautier66386952018-07-05 16:49:51 +0200136 };
137 };
138 };
139};
140
141&iwdg2 {
Yann Gautier66386952018-07-05 16:49:51 +0200142 timeout-sec = <32>;
143 status = "okay";
144};
145
146&rng1 {
147 status = "okay";
148};
149
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100150&rtc {
151 status = "okay";
152};
153
Yann Gautier66386952018-07-05 16:49:51 +0200154&sdmmc1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
157 broken-cd;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100158 st,sig-dir;
159 st,neg-edge;
160 st,use-ckin;
Yann Gautier66386952018-07-05 16:49:51 +0200161 bus-width = <4>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100162 vmmc-supply = <&vdd_sd>;
Yann Gautier66386952018-07-05 16:49:51 +0200163 sd-uhs-sdr12;
164 sd-uhs-sdr25;
165 sd-uhs-sdr50;
166 sd-uhs-ddr50;
167 sd-uhs-sdr104;
168 status = "okay";
169};
170
171&sdmmc2 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
174 non-removable;
175 no-sd;
176 no-sdio;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100177 st,neg-edge;
Yann Gautier66386952018-07-05 16:49:51 +0200178 bus-width = <8>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100179 vmmc-supply = <&v3v3>;
180 vqmmc-supply = <&v3v3>;
181 mmc-ddr-3_3v;
Yann Gautier66386952018-07-05 16:49:51 +0200182 status = "okay";
183};
184
185&uart4 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&uart4_pins_a>;
Yann Gautier66386952018-07-05 16:49:51 +0200188 status = "okay";
189};
190
191/* ATF Specific */
192#include <dt-bindings/clock/stm32mp1-clksrc.h>
193#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
194
195/ {
196 aliases {
197 gpio0 = &gpioa;
198 gpio1 = &gpiob;
199 gpio2 = &gpioc;
200 gpio3 = &gpiod;
201 gpio4 = &gpioe;
202 gpio5 = &gpiof;
203 gpio6 = &gpiog;
204 gpio7 = &gpioh;
205 gpio8 = &gpioi;
206 gpio9 = &gpioj;
207 gpio10 = &gpiok;
208 gpio25 = &gpioz;
209 i2c3 = &i2c4;
210 };
211
212 soc {
213 stgen: stgen@5C008000 {
214 compatible = "st,stm32-stgen";
215 reg = <0x5C008000 0x1000>;
216 status = "okay";
217 };
218 };
219};
220
221/* CLOCK init */
222&rcc {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100223 secure-status = "disabled";
Yann Gautier66386952018-07-05 16:49:51 +0200224 st,clksrc = <
225 CLK_MPU_PLL1P
226 CLK_AXI_PLL2P
Yann Gautiered342322019-02-15 17:33:27 +0100227 CLK_MCU_PLL3P
Yann Gautier66386952018-07-05 16:49:51 +0200228 CLK_PLL12_HSE
229 CLK_PLL3_HSE
230 CLK_PLL4_HSE
231 CLK_RTC_LSE
232 CLK_MCO1_DISABLED
233 CLK_MCO2_DISABLED
234 >;
235
236 st,clkdiv = <
237 1 /*MPU*/
238 0 /*AXI*/
Yann Gautiered342322019-02-15 17:33:27 +0100239 0 /*MCU*/
Yann Gautier66386952018-07-05 16:49:51 +0200240 1 /*APB1*/
241 1 /*APB2*/
242 1 /*APB3*/
243 1 /*APB4*/
244 2 /*APB5*/
245 23 /*RTC*/
246 0 /*MCO1*/
247 0 /*MCO2*/
248 >;
249
250 st,pkcs = <
251 CLK_CKPER_HSE
252 CLK_FMC_ACLK
253 CLK_QSPI_ACLK
254 CLK_ETH_DISABLED
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100255 CLK_SDMMC12_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200256 CLK_DSI_DSIPLL
257 CLK_STGEN_HSE
258 CLK_USBPHY_HSE
259 CLK_SPI2S1_PLL3Q
260 CLK_SPI2S23_PLL3Q
261 CLK_SPI45_HSI
262 CLK_SPI6_HSI
263 CLK_I2C46_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100264 CLK_SDMMC3_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200265 CLK_USBO_USBPHY
266 CLK_ADC_CKPER
267 CLK_CEC_LSE
268 CLK_I2C12_HSI
269 CLK_I2C35_HSI
270 CLK_UART1_HSI
271 CLK_UART24_HSI
272 CLK_UART35_HSI
273 CLK_UART6_HSI
274 CLK_UART78_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100275 CLK_SPDIF_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200276 CLK_FDCAN_PLL4Q
277 CLK_SAI1_PLL3Q
278 CLK_SAI2_PLL3Q
279 CLK_SAI3_PLL3Q
280 CLK_SAI4_PLL3Q
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100281 CLK_RNG1_LSI
282 CLK_RNG2_LSI
Yann Gautier66386952018-07-05 16:49:51 +0200283 CLK_LPTIM1_PCLK1
284 CLK_LPTIM23_PCLK3
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100285 CLK_LPTIM45_LSE
Yann Gautier66386952018-07-05 16:49:51 +0200286 >;
287
288 /* VCO = 1300.0 MHz => P = 650 (CPU) */
289 pll1: st,pll@0 {
290 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
291 frac = < 0x800 >;
292 };
293
294 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
295 pll2: st,pll@1 {
296 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
297 frac = < 0x1400 >;
298 };
299
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100300 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
Yann Gautier66386952018-07-05 16:49:51 +0200301 pll3: st,pll@2 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100302 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
303 frac = < 0x1a04 >;
Yann Gautier66386952018-07-05 16:49:51 +0200304 };
305
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100306 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
Yann Gautier66386952018-07-05 16:49:51 +0200307 pll4: st,pll@3 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100308 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
Yann Gautier66386952018-07-05 16:49:51 +0200309 };
310};
311
312/delete-node/ &clk_csi;