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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Jeenu Viswambharanb6982c02018-03-22 08:57:52 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef GIC_COMMON_H
8#define GIC_COMMON_H
Achin Gupta92712a52015-09-03 14:18:02 +01009
Jeenu Viswambharan837cc9c2018-08-02 10:14:12 +010010#include <utils_def.h>
11
Achin Gupta92712a52015-09-03 14:18:02 +010012/*******************************************************************************
13 * GIC Distributor interface general definitions
14 ******************************************************************************/
15/* Constants to categorise interrupts */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010016#define MIN_SGI_ID U(0)
17#define MIN_SEC_SGI_ID U(8)
18#define MIN_PPI_ID U(16)
19#define MIN_SPI_ID U(32)
20#define MAX_SPI_ID U(1019)
Soby Mathew327548c2017-07-13 15:19:51 +010021
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010022#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1))
Soby Mathew327548c2017-07-13 15:19:51 +010023#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
Achin Gupta92712a52015-09-03 14:18:02 +010024
25/* Mask for the priority field common to all GIC interfaces */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010026#define GIC_PRI_MASK U(0xff)
Achin Gupta92712a52015-09-03 14:18:02 +010027
Jeenu Viswambharan4684bce2017-09-22 08:32:09 +010028/* Mask for the configuration field common to all GIC interfaces */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010029#define GIC_CFG_MASK U(0x3)
Jeenu Viswambharan4684bce2017-09-22 08:32:09 +010030
Achin Gupta92712a52015-09-03 14:18:02 +010031/* Constant to indicate a spurious interrupt in all GIC versions */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010032#define GIC_SPURIOUS_INTERRUPT U(1023)
Achin Gupta92712a52015-09-03 14:18:02 +010033
Jeenu Viswambharanb6982c02018-03-22 08:57:52 +000034/* Interrupt configurations: 2-bit fields with LSB reserved */
35#define GIC_INTR_CFG_LEVEL (0 << 1)
36#define GIC_INTR_CFG_EDGE (1 << 1)
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010037
Jeenu Viswambharan83a189e2018-11-07 11:46:36 +000038/* Highest possible interrupt priorities */
Jeenu Viswambharan837cc9c2018-08-02 10:14:12 +010039#define GIC_HIGHEST_SEC_PRIORITY U(0x00)
Jeenu Viswambharan837cc9c2018-08-02 10:14:12 +010040#define GIC_HIGHEST_NS_PRIORITY U(0x80)
Achin Gupta92712a52015-09-03 14:18:02 +010041
42/*******************************************************************************
43 * GIC Distributor interface register offsets that are common to GICv3 & GICv2
44 ******************************************************************************/
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010045#define GICD_CTLR U(0x0)
46#define GICD_TYPER U(0x4)
47#define GICD_IIDR U(0x8)
48#define GICD_IGROUPR U(0x80)
49#define GICD_ISENABLER U(0x100)
50#define GICD_ICENABLER U(0x180)
51#define GICD_ISPENDR U(0x200)
52#define GICD_ICPENDR U(0x280)
53#define GICD_ISACTIVER U(0x300)
54#define GICD_ICACTIVER U(0x380)
55#define GICD_IPRIORITYR U(0x400)
56#define GICD_ICFGR U(0xc00)
57#define GICD_NSACR U(0xe00)
Achin Gupta92712a52015-09-03 14:18:02 +010058
59/* GICD_CTLR bit definitions */
60#define CTLR_ENABLE_G0_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010061#define CTLR_ENABLE_G0_MASK U(0x1)
62#define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +010063
64
65/*******************************************************************************
66 * GIC Distributor interface register constants that are common to GICv3 & GICv2
67 ******************************************************************************/
68#define PIDR2_ARCH_REV_SHIFT 4
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010069#define PIDR2_ARCH_REV_MASK U(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +010070
71/* GICv3 revision as reported by the PIDR2 register */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010072#define ARCH_REV_GICV3 U(0x3)
Achin Gupta92712a52015-09-03 14:18:02 +010073/* GICv2 revision as reported by the PIDR2 register */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010074#define ARCH_REV_GICV2 U(0x2)
Etienne Carriere0a8c3532017-11-05 22:57:38 +010075/* GICv1 revision as reported by the PIDR2 register */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010076#define ARCH_REV_GICV1 U(0x1)
Achin Gupta92712a52015-09-03 14:18:02 +010077
78#define IGROUPR_SHIFT 5
79#define ISENABLER_SHIFT 5
80#define ICENABLER_SHIFT ISENABLER_SHIFT
81#define ISPENDR_SHIFT 5
82#define ICPENDR_SHIFT ISPENDR_SHIFT
83#define ISACTIVER_SHIFT 5
84#define ICACTIVER_SHIFT ISACTIVER_SHIFT
85#define IPRIORITYR_SHIFT 2
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010086#define ITARGETSR_SHIFT 2
Achin Gupta92712a52015-09-03 14:18:02 +010087#define ICFGR_SHIFT 4
88#define NSACR_SHIFT 4
89
90/* GICD_TYPER shifts and masks */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010091#define TYPER_IT_LINES_NO_SHIFT U(0)
92#define TYPER_IT_LINES_NO_MASK U(0x1f)
Achin Gupta92712a52015-09-03 14:18:02 +010093
94/* Value used to initialize Normal world interrupt priorities four at a time */
95#define GICD_IPRIORITYR_DEF_VAL \
96 (GIC_HIGHEST_NS_PRIORITY | \
97 (GIC_HIGHEST_NS_PRIORITY << 8) | \
98 (GIC_HIGHEST_NS_PRIORITY << 16) | \
99 (GIC_HIGHEST_NS_PRIORITY << 24))
100
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000101#endif /* GIC_COMMON_H */