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git01.mediatek.com / filogic / atf / 11a5bf0ec4ceefdb2cf7c3acec8e87787b7b3025 / . / plat / intel / soc / agilex5 / platform.mk
blob: 409c7b130f6caffa306fa4f44dc535b845674ea1 [file] [log] [blame]
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]1#
2# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
Sieu Mun Tang6848bd62024-07-20 00:43:43 +0800[diff] [blame]4# Copyright (c) 2024, Altera Corporation. All rights reserved.
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]5#
6# SPDX-License-Identifier: BSD-3-Clause
7#
8include lib/xlat_tables_v2/xlat_tables.mk
9PLAT_INCLUDES := \
10 -Iplat/intel/soc/agilex5/include/ \
11 -Iplat/intel/soc/common/drivers/ \
Sieu Mun Tang6848bd62024-07-20 00:43:43 +0800[diff] [blame]12 -Iplat/intel/soc/common/lib/sha/ \
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]13 -Iplat/intel/soc/common/include/
14
15# GIC-600 configuration
16GICV3_SUPPORT_GIC600 := 1
17# Include GICv3 driver files
18include drivers/arm/gic/v3/gicv3.mk
19AGX5_GICv3_SOURCES := \
20 ${GICV3_SOURCES} \
21 plat/common/plat_gicv3.c
22
23PLAT_BL_COMMON_SOURCES := \
24 ${AGX5_GICv3_SOURCES} \
25 drivers/cadence/combo_phy/cdns_combo_phy.c \
26 drivers/cadence/emmc/cdns_sdmmc.c \
27 drivers/cadence/nand/cdns_nand.c \
28 drivers/delay_timer/delay_timer.c \
29 drivers/delay_timer/generic_delay_timer.c \
30 drivers/ti/uart/aarch64/16550_console.S \
31 plat/intel/soc/common/aarch64/platform_common.c \
32 plat/intel/soc/common/aarch64/plat_helpers.S \
33 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
34 plat/intel/soc/common/drivers/combophy/combophy.c \
35 plat/intel/soc/common/drivers/sdmmc/sdmmc.c \
36 plat/intel/soc/common/drivers/ddr/ddr.c \
37 plat/intel/soc/common/drivers/nand/nand.c \
Sieu Mun Tang6848bd62024-07-20 00:43:43 +0800[diff] [blame]38 plat/intel/soc/common/lib/sha/sha.c \
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]39 plat/intel/soc/common/socfpga_delay_timer.c
40
41BL2_SOURCES += \
42 common/desc_image_load.c \
43 lib/xlat_tables_v2/aarch64/enable_mmu.S \
44 lib/xlat_tables_v2/xlat_tables_context.c \
45 lib/xlat_tables_v2/xlat_tables_core.c \
46 lib/xlat_tables_v2/aarch64/xlat_tables_arch.c \
47 lib/xlat_tables_v2/xlat_tables_utils.c \
48 drivers/mmc/mmc.c \
49 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
50 drivers/io/io_storage.c \
51 drivers/io/io_block.c \
52 drivers/io/io_fip.c \
53 drivers/io/io_mtd.c \
54 drivers/partition/partition.c \
55 drivers/partition/gpt.c \
56 drivers/synopsys/emmc/dw_mmc.c \
57 lib/cpus/aarch64/cortex_a55.S \
58 lib/cpus/aarch64/cortex_a76.S \
59 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
60 plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \
61 plat/intel/soc/agilex5/soc/agilex5_mmc.c \
62 plat/intel/soc/agilex5/soc/agilex5_pinmux.c \
63 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
64 plat/intel/soc/common/bl2_plat_mem_params_desc.c \
65 plat/intel/soc/common/socfpga_image_load.c \
Mahesh Raoc2715992023-08-22 17:26:23 +0800[diff] [blame]66 plat/intel/soc/common/socfpga_ros.c \
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]67 plat/intel/soc/common/socfpga_storage.c \
68 plat/intel/soc/common/socfpga_vab.c \
69 plat/intel/soc/common/soc/socfpga_emac.c \
70 plat/intel/soc/common/soc/socfpga_firewall.c \
71 plat/intel/soc/common/soc/socfpga_handoff.c \
72 plat/intel/soc/common/soc/socfpga_mailbox.c \
73 plat/intel/soc/common/soc/socfpga_reset_manager.c \
74 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
75 plat/intel/soc/agilex5/bl2_plat_setup.c \
76 plat/intel/soc/common/drivers/wdt/watchdog.c
77
78include lib/zlib/zlib.mk
79PLAT_INCLUDES += -Ilib/zlib
80BL2_SOURCES += $(ZLIB_SOURCES)
81
82BL31_SOURCES += \
83 drivers/arm/cci/cci.c \
84 ${XLAT_TABLES_LIB_SRCS} \
85 lib/cpus/aarch64/aem_generic.S \
86 lib/cpus/aarch64/cortex_a55.S \
87 lib/cpus/aarch64/cortex_a76.S \
88 plat/common/plat_psci_common.c \
89 plat/intel/soc/agilex5/bl31_plat_setup.c \
Jit Loon Limffa06e72023-07-07 17:15:26 +0800[diff] [blame]90 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]91 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
92 plat/intel/soc/common/socfpga_psci.c \
93 plat/intel/soc/common/socfpga_sip_svc.c \
94 plat/intel/soc/common/socfpga_sip_svc_v2.c \
95 plat/intel/soc/common/socfpga_topology.c \
96 plat/intel/soc/common/sip/socfpga_sip_ecc.c \
97 plat/intel/soc/common/sip/socfpga_sip_fcs.c \
98 plat/intel/soc/common/soc/socfpga_mailbox.c \
99 plat/intel/soc/common/soc/socfpga_reset_manager.c
100
101# Configs for A76 and A55
102HW_ASSISTED_COHERENCY := 1
103USE_COHERENT_MEM := 0
104CTX_INCLUDE_AARCH32_REGS := 0
105ERRATA_A55_1530923 := 1
106
Jit Loon Limc5a3e3a2023-10-16 00:19:34 +0800[diff] [blame]107# Don't have the Linux kernel as a BL33 image by default
108ARM_LINUX_KERNEL_AS_BL33 := 0
109$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
110$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]111$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
112
Sieu Mun Tang6848bd62024-07-20 00:43:43 +0800[diff] [blame]113# Configs for VAB Authentication
114SOCFPGA_SECURE_VAB_AUTH := 0
115$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH))
116$(eval $(call add_define,SOCFPGA_SECURE_VAB_AUTH))
117
Jit Loon Lim4c249f12023-05-17 12:26:11 +0800[diff] [blame]118PROGRAMMABLE_RESET_ADDRESS := 0
119RESET_TO_BL2 := 1
Sieu Mun Tang6848bd62024-07-20 00:43:43 +0800[diff] [blame]120BL2_INV_DCACHE := 0