blob: 426418377e828cec45a01ed9ae92b7fe12e1103e [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <arch_helpers.h>
32#include <cci.h>
33#include <mmio.h>
34#include <plat_arm.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010035#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000036#include <xlat_tables.h>
37
38
39static const int cci_map[] = {
40 PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX,
41 PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX
42};
43
44/* Weak definitions may be overridden in specific ARM standard platform */
45#pragma weak plat_get_ns_image_entrypoint
46
47
48/*******************************************************************************
49 * Macro generating the code for the function setting up the pagetables as per
50 * the platform memory map & initialize the mmu, for the given exception level
51 ******************************************************************************/
52#if USE_COHERENT_MEM
53#define DEFINE_CONFIGURE_MMU_EL(_el) \
54 void arm_configure_mmu_el##_el(unsigned long total_base, \
55 unsigned long total_size, \
56 unsigned long ro_start, \
57 unsigned long ro_limit, \
58 unsigned long coh_start, \
59 unsigned long coh_limit) \
60 { \
61 mmap_add_region(total_base, total_base, \
62 total_size, \
63 MT_MEMORY | MT_RW | MT_SECURE); \
64 mmap_add_region(ro_start, ro_start, \
65 ro_limit - ro_start, \
66 MT_MEMORY | MT_RO | MT_SECURE); \
67 mmap_add_region(coh_start, coh_start, \
68 coh_limit - coh_start, \
69 MT_DEVICE | MT_RW | MT_SECURE); \
70 mmap_add(plat_arm_mmap); \
71 init_xlat_tables(); \
72 \
73 enable_mmu_el##_el(0); \
74 }
75#else
76#define DEFINE_CONFIGURE_MMU_EL(_el) \
77 void arm_configure_mmu_el##_el(unsigned long total_base, \
78 unsigned long total_size, \
79 unsigned long ro_start, \
80 unsigned long ro_limit) \
81 { \
82 mmap_add_region(total_base, total_base, \
83 total_size, \
84 MT_MEMORY | MT_RW | MT_SECURE); \
85 mmap_add_region(ro_start, ro_start, \
86 ro_limit - ro_start, \
87 MT_MEMORY | MT_RO | MT_SECURE); \
88 mmap_add(plat_arm_mmap); \
89 init_xlat_tables(); \
90 \
91 enable_mmu_el##_el(0); \
92 }
93#endif
94
95/* Define EL1 and EL3 variants of the function initialising the MMU */
96DEFINE_CONFIGURE_MMU_EL(1)
97DEFINE_CONFIGURE_MMU_EL(3)
98
99
100unsigned long plat_get_ns_image_entrypoint(void)
101{
102 return PLAT_ARM_NS_IMAGE_OFFSET;
103}
104
105/*******************************************************************************
106 * Gets SPSR for BL32 entry
107 ******************************************************************************/
108uint32_t arm_get_spsr_for_bl32_entry(void)
109{
110 /*
111 * The Secure Payload Dispatcher service is responsible for
112 * setting the SPSR prior to entry into the BL3-2 image.
113 */
114 return 0;
115}
116
117/*******************************************************************************
118 * Gets SPSR for BL33 entry
119 ******************************************************************************/
120uint32_t arm_get_spsr_for_bl33_entry(void)
121{
122 unsigned long el_status;
123 unsigned int mode;
124 uint32_t spsr;
125
126 /* Figure out what mode we enter the non-secure world in */
127 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
128 el_status &= ID_AA64PFR0_ELX_MASK;
129
130 mode = (el_status) ? MODE_EL2 : MODE_EL1;
131
132 /*
133 * TODO: Consider the possibility of specifying the SPSR in
134 * the FIP ToC and allowing the platform to have a say as
135 * well.
136 */
137 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
138 return spsr;
139}
140
141
142void arm_cci_init(void)
143{
144 cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
145}
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100146
147/*******************************************************************************
148 * Configures access to the system counter timer module.
149 ******************************************************************************/
150void arm_configure_sys_timer(void)
151{
152 unsigned int reg_val;
153
154 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
155 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
156 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
157 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
158
159 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
160 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
161}