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Oliver Swede8fed2fe2019-11-11 11:11:06 +00001#
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +01002# Copyright (c) 2020, Arm Limited. All rights reserved.
Oliver Swede8fed2fe2019-11-11 11:11:06 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Andre Przywaraeec45eb2020-01-24 15:02:27 +00007include lib/libfdt/libfdt.mk
8
Oliver Swede8fed2fe2019-11-11 11:11:06 +00009RESET_TO_BL31 := 1
10ifeq (${RESET_TO_BL31}, 0)
11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
12endif
13
Oliver Swede3769b3f2019-12-16 14:08:27 +000014ifeq (${ENABLE_PIE}, 1)
15override SEPARATE_CODE_AND_RODATA := 1
16endif
17
Oliver Swede8fed2fe2019-11-11 11:11:06 +000018CTX_INCLUDE_AARCH32_REGS := 0
19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
21endif
22
23ifeq (${TRUSTED_BOARD_BOOT}, 1)
24$(error "TRUSTED_BOARD_BOOT must be disabled")
25endif
26
Andre Przywarad9b95cc2020-07-08 13:01:00 +010027PRELOADED_BL33_BASE := 0x80080000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000028
Andre Przywarad9b95cc2020-07-08 13:01:00 +010029FPGA_PRELOADED_DTB_BASE := 0x80070000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000030$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
Oliver Swede8fed2fe2019-11-11 11:11:06 +000031
Andre Przywara01767932020-07-07 10:40:46 +010032FPGA_PRELOADED_CMD_LINE := 0x1000
33$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
34
Oliver Swede8fed2fe2019-11-11 11:11:06 +000035# Treating this as a memory-constrained port for now
36USE_COHERENT_MEM := 0
37
Oliver Swede7fbb9b52020-01-15 10:20:09 +000038# This can be overridden depending on CPU(s) used in the FPGA image
Oliver Swede8fed2fe2019-11-11 11:11:06 +000039HW_ASSISTED_COHERENCY := 1
40
Andre Przywara8b505252020-04-09 10:10:09 +010041PL011_GENERIC_UART := 1
42
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010043SUPPORT_UNKNOWN_MPID ?= 1
44
Oliver Swede7fbb9b52020-01-15 10:20:09 +000045FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
46
47# select a different set of CPU files, depending on whether we compile for
48# hardware assisted coherency cores or not
49ifeq (${HW_ASSISTED_COHERENCY}, 0)
50# Cores used without DSU
51 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
52 lib/cpus/aarch64/cortex_a53.S \
53 lib/cpus/aarch64/cortex_a57.S \
54 lib/cpus/aarch64/cortex_a72.S \
55 lib/cpus/aarch64/cortex_a73.S
56else
57# AArch64-only cores
58 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
59 lib/cpus/aarch64/cortex_a76ae.S \
60 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -050061 lib/cpus/aarch64/cortex_a78.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010062 lib/cpus/aarch64/neoverse_n_common.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000063 lib/cpus/aarch64/neoverse_n1.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010064 lib/cpus/aarch64/neoverse_n2.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000065 lib/cpus/aarch64/neoverse_e1.S \
Jimmy Brisson958a0b12020-09-30 15:28:03 -050066 lib/cpus/aarch64/neoverse_v1.S \
Jimmy Brisson7cc90c42020-09-30 15:34:51 -050067 lib/cpus/aarch64/cortex_a78_ae.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000068 lib/cpus/aarch64/cortex_a65.S \
Andre Przywaracb167672020-06-25 13:10:38 +010069 lib/cpus/aarch64/cortex_a65ae.S \
70 lib/cpus/aarch64/cortex_klein.S \
71 lib/cpus/aarch64/cortex_matterhorn.S
72
Oliver Swede7fbb9b52020-01-15 10:20:09 +000073# AArch64/AArch32 cores
74 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
75 lib/cpus/aarch64/cortex_a75.S
76endif
Oliver Swede8fed2fe2019-11-11 11:11:06 +000077
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010078ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
79# Add support for unknown/invalid MPIDs (aarch64 only)
80$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
81 FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
82endif
83
Andre Przywarae1cc1302020-03-25 15:50:38 +000084# Allow detection of GIC-600
85GICV3_SUPPORT_GIC600 := 1
Manish Pandeyb21cad72020-04-03 18:59:20 +010086
87# Include GICv3 driver files
88include drivers/arm/gic/v3/gicv3.mk
89
90FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
Oliver Swedeb51da812019-12-03 14:08:21 +000091 plat/common/plat_gicv3.c \
92 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede8fed2fe2019-11-11 11:11:06 +000093
Andre Przywaraeb5cb802020-08-03 12:54:58 +010094FDT_SOURCES := fdts/arm_fpga.dts
95
Oliver Swede8fed2fe2019-11-11 11:11:06 +000096PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
97
98PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
99
Andre Przywaraeec45eb2020-01-24 15:02:27 +0000100BL31_SOURCES += common/fdt_wrappers.c \
Javier Almansa Sobrino3bcf3c82020-06-04 19:01:48 +0100101 common/fdt_fixup.c \
Andre Przywaraeec45eb2020-01-24 15:02:27 +0000102 drivers/delay_timer/delay_timer.c \
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000103 drivers/delay_timer/generic_delay_timer.c \
104 drivers/arm/pl011/${ARCH}/pl011_console.S \
105 plat/common/plat_psci_common.c \
106 plat/arm/board/arm_fpga/fpga_pm.c \
107 plat/arm/board/arm_fpga/fpga_topology.c \
108 plat/arm/board/arm_fpga/fpga_console.c \
109 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
110 ${FPGA_CPU_LIBS} \
111 ${FPGA_GIC_SOURCES}
112
Andre Przywara586de5e2020-08-03 13:06:38 +0100113$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31))
Andre Przywara6228e432020-09-16 17:13:33 +0100114$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31))
115
116bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld
117 $(ECHO) " LD $@"
118 $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf
Andre Przywara586de5e2020-08-03 13:06:38 +0100119
Andre Przywara6228e432020-09-16 17:13:33 +0100120all: bl31.axf