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developer28d70382019-12-19 15:58:20 +08001/*
developerbdeb0ba2022-07-08 14:48:56 +08002 * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
developer28d70382019-12-19 15:58:20 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLAT_MT_CIRQ_H
8#define PLAT_MT_CIRQ_H
9
developerb63f6b22020-11-06 09:20:25 +080010#include <stdint.h>
developer8273a602021-03-25 11:26:46 +080011#include <platform_def.h>
developerb63f6b22020-11-06 09:20:25 +080012
13enum {
14 IRQ_MASK_HEADER = 0xF1F1F1F1,
15 IRQ_MASK_FOOTER = 0xF2F2F2F2
16};
17
18struct mtk_irq_mask {
19 uint32_t header; /* for error checking */
20 uint32_t mask0;
21 uint32_t mask1;
22 uint32_t mask2;
23 uint32_t mask3;
24 uint32_t mask4;
25 uint32_t mask5;
26 uint32_t mask6;
27 uint32_t mask7;
28 uint32_t mask8;
29 uint32_t mask9;
30 uint32_t mask10;
31 uint32_t mask11;
32 uint32_t mask12;
33 uint32_t footer; /* for error checking */
34};
35
developer28d70382019-12-19 15:58:20 +080036/*
37 * Define hardware register
38 */
developerb63f6b22020-11-06 09:20:25 +080039#define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000))
40#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080))
41#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100))
42#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180))
43#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200))
44#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280))
45#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300))
46#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380))
47#define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400))
48#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480))
49#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500))
50#define CIRQ_CON (SYS_CIRQ_BASE + U(0x600))
developer28d70382019-12-19 15:58:20 +080051
52/*
53 * Register placement
54 */
55#define CIRQ_CON_EN_BITS U(0)
56#define CIRQ_CON_EDGE_ONLY_BITS U(1)
57#define CIRQ_CON_FLUSH_BITS U(2)
developer28d70382019-12-19 15:58:20 +080058#define CIRQ_CON_SW_RST_BITS U(20)
developerb63f6b22020-11-06 09:20:25 +080059#define CIRQ_CON_EVENT_BITS U(31)
developer28d70382019-12-19 15:58:20 +080060#define CIRQ_CON_BITS_MASK U(0x7)
61
62/*
63 * Register setting
64 */
65#define CIRQ_CON_EN U(0x1)
66#define CIRQ_CON_EDGE_ONLY U(0x1)
developer28d70382019-12-19 15:58:20 +080067#define CIRQ_CON_FLUSH U(0x1)
developerb63f6b22020-11-06 09:20:25 +080068#define CIRQ_SW_RESET U(0x1)
developer28d70382019-12-19 15:58:20 +080069
70/*
71 * Define constant
72 */
73#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
developer28d70382019-12-19 15:58:20 +080074
developerb63f6b22020-11-06 09:20:25 +080075#define MT_CIRQ_POL_NEG U(0)
76#define MT_CIRQ_POL_POS U(1)
developer28d70382019-12-19 15:58:20 +080077
developerb63f6b22020-11-06 09:20:25 +080078#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START))
79#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START))
80
81/* GIC sensitive */
82#define SENS_EDGE U(0x2)
83#define SENS_LEVEL U(0x1)
84
developer28d70382019-12-19 15:58:20 +080085
86/*
87 * Define function prototypes.
88 */
developerb63f6b22020-11-06 09:20:25 +080089int mt_cirq_test(void);
90void mt_cirq_dump_reg(void);
91int mt_irq_mask_restore(struct mtk_irq_mask *mask);
92int mt_irq_mask_all(struct mtk_irq_mask *mask);
developer28d70382019-12-19 15:58:20 +080093void mt_cirq_clone_gic(void);
developerb63f6b22020-11-06 09:20:25 +080094void mt_cirq_enable(void);
developer28d70382019-12-19 15:58:20 +080095void mt_cirq_flush(void);
developerb63f6b22020-11-06 09:20:25 +080096void mt_cirq_disable(void);
97void mt_irq_unmask_for_sleep_ex(uint32_t irq);
developer28d70382019-12-19 15:58:20 +080098void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
developerb63f6b22020-11-06 09:20:25 +080099void mt_cirq_sw_reset(void);
100
101struct cirq_reg {
102 uint32_t reg_num;
103 uint32_t used;
104 uint32_t mask;
105 uint32_t pol;
106 uint32_t sen;
107 uint32_t pending;
108 uint32_t the_link;
109};
110
111struct cirq_events {
112 uint32_t num_reg;
113 uint32_t spi_start;
114 uint32_t num_of_events;
115 uint32_t *wakeup_events;
116 struct cirq_reg table[CIRQ_REG_NUM];
117 uint32_t dist_base;
118 uint32_t cirq_base;
119 uint32_t used_reg_head;
120};
developer28d70382019-12-19 15:58:20 +0800121
developerb63f6b22020-11-06 09:20:25 +0800122#endif /* PLAT_MT_CIRQ_H */