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developer28d70382019-12-19 15:58:20 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLAT_MT_CIRQ_H
8#define PLAT_MT_CIRQ_H
9
10#define SYS_CIRQ_BASE U(0x10204000)
11#define CIRQ_IRQ_NUM U(439)
12#define CIRQ_SPI_START U(96)
13/*
14 * Define hardware register
15 */
16#define CIRQ_STA_BASE U(0x000)
17#define CIRQ_ACK_BASE U(0x080)
18#define CIRQ_MASK_BASE U(0x100)
19#define CIRQ_MASK_SET_BASE U(0x180)
20#define CIRQ_MASK_CLR_BASE U(0x200)
21#define CIRQ_SENS_BASE U(0x280)
22#define CIRQ_SENS_SET_BASE U(0x300)
23#define CIRQ_SENS_CLR_BASE U(0x380)
24#define CIRQ_POL_BASE U(0x400)
25#define CIRQ_POL_SET_BASE U(0x480)
26#define CIRQ_POL_CLR_BASE U(0x500)
27#define CIRQ_CON U(0x600)
28
29/*
30 * Register placement
31 */
32#define CIRQ_CON_EN_BITS U(0)
33#define CIRQ_CON_EDGE_ONLY_BITS U(1)
34#define CIRQ_CON_FLUSH_BITS U(2)
35#define CIRQ_CON_EVENT_BITS U(31)
36#define CIRQ_CON_SW_RST_BITS U(20)
37#define CIRQ_CON_BITS_MASK U(0x7)
38
39/*
40 * Register setting
41 */
42#define CIRQ_CON_EN U(0x1)
43#define CIRQ_CON_EDGE_ONLY U(0x1)
44#define CIRQ_SW_RESET U(0x1)
45#define CIRQ_CON_FLUSH U(0x1)
46
47/*
48 * Define constant
49 */
50#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
51#define MT_CIRQ_POL_NEG U(0)
52#define MT_CIRQ_POL_POS U(1)
53#define MT_CIRQ_EDGE_SENSITIVE U(0)
54#define MT_CIRQ_LEVEL_SENSITIVE U(1)
55
56/*
57 * Define macro
58 */
59#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (CIRQ_SPI_START))
60#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (CIRQ_SPI_START))
61
62/*
63 * Define cirq events
64 */
65struct cirq_events {
66 uint32_t spi_start;
67 uint32_t num_of_events;
68 uint32_t *wakeup_events;
69};
70
71/*
72 * Define function prototypes.
73 */
74void mt_cirq_enable(void);
75void mt_cirq_disable(void);
76void mt_cirq_clone_gic(void);
77void mt_cirq_flush(void);
78void mt_cirq_sw_reset(void);
79void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
80void mt_cirq_dump_reg(void);
81
82#endif /* PLAT_MT_CIRQ_H */