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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +02002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautierc7374052019-06-04 18:02:37 +020025#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010026#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010027#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010028#endif
29
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020030#if !STM32MP_USE_STM32IMAGE
31#include "stm32mp1_fip_def.h"
32#else /* STM32MP_USE_STM32IMAGE */
33#include "stm32mp1_stm32image_def.h"
34#endif /* STM32MP_USE_STM32IMAGE */
35
Yann Gautier4b0c72a2018-07-16 10:54:09 +020036/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020037 * CHIP ID
38 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010039#if STM32MP13
40#define STM32MP1_CHIP_ID U(0x501)
41
42#define STM32MP135C_PART_NB U(0x05010000)
43#define STM32MP135A_PART_NB U(0x05010001)
44#define STM32MP133C_PART_NB U(0x050100C0)
45#define STM32MP133A_PART_NB U(0x050100C1)
46#define STM32MP131C_PART_NB U(0x050106C8)
47#define STM32MP131A_PART_NB U(0x050106C9)
48#define STM32MP135F_PART_NB U(0x05010800)
49#define STM32MP135D_PART_NB U(0x05010801)
50#define STM32MP133F_PART_NB U(0x050108C0)
51#define STM32MP133D_PART_NB U(0x050108C1)
52#define STM32MP131F_PART_NB U(0x05010EC8)
53#define STM32MP131D_PART_NB U(0x05010EC9)
54#endif
55#if STM32MP15
Yann Gautiera0a6ff62021-05-10 16:05:18 +020056#define STM32MP1_CHIP_ID U(0x500)
57
Yann Gautierc7374052019-06-04 18:02:37 +020058#define STM32MP157C_PART_NB U(0x05000000)
59#define STM32MP157A_PART_NB U(0x05000001)
60#define STM32MP153C_PART_NB U(0x05000024)
61#define STM32MP153A_PART_NB U(0x05000025)
62#define STM32MP151C_PART_NB U(0x0500002E)
63#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020064#define STM32MP157F_PART_NB U(0x05000080)
65#define STM32MP157D_PART_NB U(0x05000081)
66#define STM32MP153F_PART_NB U(0x050000A4)
67#define STM32MP153D_PART_NB U(0x050000A5)
68#define STM32MP151F_PART_NB U(0x050000AE)
69#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautier16188f32020-02-12 15:38:34 +010070#endif
Yann Gautierc7374052019-06-04 18:02:37 +020071
72#define STM32MP1_REV_B U(0x2000)
Yann Gautier0fd6e232021-08-25 14:40:12 +020073#if STM32MP13
74#define STM32MP1_REV_Z U(0x1001)
75#endif
76#if STM32MP15
Lionel Debieve2d64b532019-06-25 10:40:37 +020077#define STM32MP1_REV_Z U(0x2001)
Yann Gautier0fd6e232021-08-25 14:40:12 +020078#endif
Yann Gautierc7374052019-06-04 18:02:37 +020079
80/*******************************************************************************
81 * PACKAGE ID
82 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010083#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +020084#define PKG_AA_LFBGA448 U(4)
85#define PKG_AB_LFBGA354 U(3)
86#define PKG_AC_TFBGA361 U(2)
87#define PKG_AD_TFBGA257 U(1)
Yann Gautier16188f32020-02-12 15:38:34 +010088#endif
Yann Gautierc7374052019-06-04 18:02:37 +020089
90/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020091 * STM32MP1 memory map related constants
92 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020093#define STM32MP_ROM_BASE U(0x00000000)
94#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier3c93a252021-09-15 15:12:57 +020095#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020096
Yann Gautier15e84832020-02-03 17:48:07 +010097#if STM32MP13
98#define STM32MP_SYSRAM_BASE U(0x2FFE0000)
99#define STM32MP_SYSRAM_SIZE U(0x00020000)
100#define SRAM1_BASE U(0x30000000)
101#define SRAM1_SIZE U(0x00004000)
102#define SRAM2_BASE U(0x30004000)
103#define SRAM2_SIZE U(0x00002000)
104#define SRAM3_BASE U(0x30006000)
105#define SRAM3_SIZE U(0x00002000)
Yann Gautier84d994b2020-04-14 18:08:50 +0200106#define SRAMS_BASE SRAM1_BASE
107#define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier15e84832020-02-03 17:48:07 +0100108#endif /* STM32MP13 */
109#if STM32MP15
Yann Gautiera2e2a302019-02-14 11:13:39 +0100110#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
111#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier15e84832020-02-03 17:48:07 +0100112#endif /* STM32MP15 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200113
Etienne Carriere72369b12019-12-08 08:17:56 +0100114#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
115#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
116 STM32MP_SYSRAM_SIZE - \
117 STM32MP_NS_SYSRAM_SIZE)
118
Etienne Carriere34f0e932020-07-16 17:36:18 +0200119#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
120#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
121
Etienne Carriere72369b12019-12-08 08:17:56 +0100122#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
123#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
124 STM32MP_NS_SYSRAM_SIZE)
125
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200126/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100127#define STM32MP_DDR_BASE U(0xC0000000)
128#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200129
130/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -0700131#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200132enum ddr_type {
133 STM32MP_DDR3,
134 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +0200135 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200136};
137#endif
138
139/* Section used inside TF binaries */
Yann Gautier84d994b2020-04-14 18:08:50 +0200140#if STM32MP13
141/* 512 Octets reserved for header */
142#define STM32MP_HEADER_RESERVED_SIZE U(0x200)
143
144#define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
145
146#define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
147#endif
148#if STM32MP15
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200149#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200150/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100151#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautiera1ee9ed2020-09-17 11:30:18 +0200152/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
153#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200154
Etienne Carriere72369b12019-12-08 08:17:56 +0100155#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100156 STM32MP_PARAM_LOAD_SIZE + \
157 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200158
Etienne Carriere72369b12019-12-08 08:17:56 +0100159#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100160 (STM32MP_PARAM_LOAD_SIZE + \
161 STM32MP_HEADER_SIZE))
Yann Gautier84d994b2020-04-14 18:08:50 +0200162#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200163
Yann Gautierebc765f2020-01-16 18:50:51 +0100164/* BL2 and BL32/sp_min require finer granularity tables */
165#if defined(IMAGE_BL2)
166#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
167#endif
168
169#if defined(IMAGE_BL32)
170#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
171#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200172
173/*
174 * MAX_MMAP_REGIONS is usually:
175 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
176 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200177#if defined(IMAGE_BL2)
Yann Gautierebc765f2020-01-16 18:50:51 +0100178 #if STM32MP_USB_PROGRAMMER
179 #define MAX_MMAP_REGIONS 8
180 #else
181 #define MAX_MMAP_REGIONS 7
182 #endif
Yann Gautier9d135e42018-07-16 19:36:06 +0200183#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200184
Yann Gautiera2e2a302019-02-14 11:13:39 +0100185#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200186#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200187
Lionel Debieve402a46b2019-11-04 12:28:15 +0100188/* Define maximum page size for NAND devices */
189#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
190
191/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200192 * STM32MP1 device/io map related constants (used for MMU)
193 ******************************************************************************/
194#define STM32MP1_DEVICE1_BASE U(0x40000000)
195#define STM32MP1_DEVICE1_SIZE U(0x40000000)
196
197#define STM32MP1_DEVICE2_BASE U(0x80000000)
198#define STM32MP1_DEVICE2_SIZE U(0x40000000)
199
200/*******************************************************************************
201 * STM32MP1 RCC
202 ******************************************************************************/
203#define RCC_BASE U(0x50000000)
204
205/*******************************************************************************
206 * STM32MP1 PWR
207 ******************************************************************************/
208#define PWR_BASE U(0x50001000)
209
210/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100211 * STM32MP1 GPIO
212 ******************************************************************************/
213#define GPIOA_BASE U(0x50002000)
214#define GPIOB_BASE U(0x50003000)
215#define GPIOC_BASE U(0x50004000)
216#define GPIOD_BASE U(0x50005000)
217#define GPIOE_BASE U(0x50006000)
218#define GPIOF_BASE U(0x50007000)
219#define GPIOG_BASE U(0x50008000)
220#define GPIOH_BASE U(0x50009000)
221#define GPIOI_BASE U(0x5000A000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100222#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100223#define GPIOJ_BASE U(0x5000B000)
224#define GPIOK_BASE U(0x5000C000)
225#define GPIOZ_BASE U(0x54004000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100226#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100227#define GPIO_BANK_OFFSET U(0x1000)
228
229/* Bank IDs used in GPIO driver API */
230#define GPIO_BANK_A U(0)
231#define GPIO_BANK_B U(1)
232#define GPIO_BANK_C U(2)
233#define GPIO_BANK_D U(3)
234#define GPIO_BANK_E U(4)
235#define GPIO_BANK_F U(5)
236#define GPIO_BANK_G U(6)
237#define GPIO_BANK_H U(7)
238#define GPIO_BANK_I U(8)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100239#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100240#define GPIO_BANK_J U(9)
241#define GPIO_BANK_K U(10)
242#define GPIO_BANK_Z U(25)
243
244#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100245#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100246
247/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200248 * STM32MP1 UART
249 ******************************************************************************/
250#define USART1_BASE U(0x5C000000)
251#define USART2_BASE U(0x4000E000)
252#define USART3_BASE U(0x4000F000)
253#define UART4_BASE U(0x40010000)
254#define UART5_BASE U(0x40011000)
255#define USART6_BASE U(0x44003000)
256#define UART7_BASE U(0x40018000)
257#define UART8_BASE U(0x40019000)
Yann Gautier038bff22019-01-17 19:17:47 +0100258
259/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100260#define STM32MP_DEBUG_USART_BASE UART4_BASE
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100261#if STM32MP13
262/* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
263#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
264#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
265#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
266#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
267#define DEBUG_UART_TX_GPIO_PORT 6
268#define DEBUG_UART_TX_GPIO_ALTERNATE 8
269#define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
270#define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
271#endif /* STM32MP13 */
272#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100273/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100274#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100275#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
276#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
277#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
278#define DEBUG_UART_TX_GPIO_PORT 11
279#define DEBUG_UART_TX_GPIO_ALTERNATE 6
280#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
281#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100282#endif /* STM32MP15 */
Yann Gautier038bff22019-01-17 19:17:47 +0100283#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
284#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200285#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
286#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200287
288/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200289 * STM32MP1 ETZPC
290 ******************************************************************************/
291#define STM32MP1_ETZPC_BASE U(0x5C007000)
292
293/* ETZPC TZMA IDs */
294#define STM32MP1_ETZPC_TZMA_ROM U(0)
295#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
296
297#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
298
299/* ETZPC DECPROT IDs */
300#define STM32MP1_ETZPC_STGENC_ID 0
301#define STM32MP1_ETZPC_BKPSRAM_ID 1
302#define STM32MP1_ETZPC_IWDG1_ID 2
303#define STM32MP1_ETZPC_USART1_ID 3
304#define STM32MP1_ETZPC_SPI6_ID 4
305#define STM32MP1_ETZPC_I2C4_ID 5
306#define STM32MP1_ETZPC_RNG1_ID 7
307#define STM32MP1_ETZPC_HASH1_ID 8
308#define STM32MP1_ETZPC_CRYP1_ID 9
309#define STM32MP1_ETZPC_DDRCTRL_ID 10
310#define STM32MP1_ETZPC_DDRPHYC_ID 11
311#define STM32MP1_ETZPC_I2C6_ID 12
312#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
313
314#define STM32MP1_ETZPC_TIM2_ID 16
315#define STM32MP1_ETZPC_TIM3_ID 17
316#define STM32MP1_ETZPC_TIM4_ID 18
317#define STM32MP1_ETZPC_TIM5_ID 19
318#define STM32MP1_ETZPC_TIM6_ID 20
319#define STM32MP1_ETZPC_TIM7_ID 21
320#define STM32MP1_ETZPC_TIM12_ID 22
321#define STM32MP1_ETZPC_TIM13_ID 23
322#define STM32MP1_ETZPC_TIM14_ID 24
323#define STM32MP1_ETZPC_LPTIM1_ID 25
324#define STM32MP1_ETZPC_WWDG1_ID 26
325#define STM32MP1_ETZPC_SPI2_ID 27
326#define STM32MP1_ETZPC_SPI3_ID 28
327#define STM32MP1_ETZPC_SPDIFRX_ID 29
328#define STM32MP1_ETZPC_USART2_ID 30
329#define STM32MP1_ETZPC_USART3_ID 31
330#define STM32MP1_ETZPC_UART4_ID 32
331#define STM32MP1_ETZPC_UART5_ID 33
332#define STM32MP1_ETZPC_I2C1_ID 34
333#define STM32MP1_ETZPC_I2C2_ID 35
334#define STM32MP1_ETZPC_I2C3_ID 36
335#define STM32MP1_ETZPC_I2C5_ID 37
336#define STM32MP1_ETZPC_CEC_ID 38
337#define STM32MP1_ETZPC_DAC_ID 39
338#define STM32MP1_ETZPC_UART7_ID 40
339#define STM32MP1_ETZPC_UART8_ID 41
340#define STM32MP1_ETZPC_MDIOS_ID 44
341#define STM32MP1_ETZPC_TIM1_ID 48
342#define STM32MP1_ETZPC_TIM8_ID 49
343#define STM32MP1_ETZPC_USART6_ID 51
344#define STM32MP1_ETZPC_SPI1_ID 52
345#define STM32MP1_ETZPC_SPI4_ID 53
346#define STM32MP1_ETZPC_TIM15_ID 54
347#define STM32MP1_ETZPC_TIM16_ID 55
348#define STM32MP1_ETZPC_TIM17_ID 56
349#define STM32MP1_ETZPC_SPI5_ID 57
350#define STM32MP1_ETZPC_SAI1_ID 58
351#define STM32MP1_ETZPC_SAI2_ID 59
352#define STM32MP1_ETZPC_SAI3_ID 60
353#define STM32MP1_ETZPC_DFSDM_ID 61
354#define STM32MP1_ETZPC_TT_FDCAN_ID 62
355#define STM32MP1_ETZPC_LPTIM2_ID 64
356#define STM32MP1_ETZPC_LPTIM3_ID 65
357#define STM32MP1_ETZPC_LPTIM4_ID 66
358#define STM32MP1_ETZPC_LPTIM5_ID 67
359#define STM32MP1_ETZPC_SAI4_ID 68
360#define STM32MP1_ETZPC_VREFBUF_ID 69
361#define STM32MP1_ETZPC_DCMI_ID 70
362#define STM32MP1_ETZPC_CRC2_ID 71
363#define STM32MP1_ETZPC_ADC_ID 72
364#define STM32MP1_ETZPC_HASH2_ID 73
365#define STM32MP1_ETZPC_RNG2_ID 74
366#define STM32MP1_ETZPC_CRYP2_ID 75
367#define STM32MP1_ETZPC_SRAM1_ID 80
368#define STM32MP1_ETZPC_SRAM2_ID 81
369#define STM32MP1_ETZPC_SRAM3_ID 82
370#define STM32MP1_ETZPC_SRAM4_ID 83
371#define STM32MP1_ETZPC_RETRAM_ID 84
372#define STM32MP1_ETZPC_OTG_ID 85
373#define STM32MP1_ETZPC_SDMMC3_ID 86
374#define STM32MP1_ETZPC_DLYBSD3_ID 87
375#define STM32MP1_ETZPC_DMA1_ID 88
376#define STM32MP1_ETZPC_DMA2_ID 89
377#define STM32MP1_ETZPC_DMAMUX_ID 90
378#define STM32MP1_ETZPC_FMC_ID 91
379#define STM32MP1_ETZPC_QSPI_ID 92
380#define STM32MP1_ETZPC_DLYBQ_ID 93
381#define STM32MP1_ETZPC_ETH_ID 94
382#define STM32MP1_ETZPC_RSV_ID 95
383
384#define STM32MP_ETZPC_MAX_ID 96
385
386/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200387 * STM32MP1 TZC (TZ400)
388 ******************************************************************************/
389#define STM32MP1_TZC_BASE U(0x5C006000)
390
Yann Gautier256c6b92020-10-21 18:15:12 +0200391#if STM32MP13
392#define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
393#endif
394#if STM32MP15
Yann Gautier2f974232020-09-17 12:25:05 +0200395#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
396 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier256c6b92020-10-21 18:15:12 +0200397#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200398
399/*******************************************************************************
400 * STM32MP1 SDMMC
401 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100402#define STM32MP_SDMMC1_BASE U(0x58005000)
403#define STM32MP_SDMMC2_BASE U(0x58007000)
404#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200405
Yann Gautier4baf5822019-05-09 13:25:52 +0200406#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
407#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
408#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
409#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
410#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200411
412/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100413 * STM32MP1 BSEC / OTP
414 ******************************************************************************/
415#define STM32MP1_OTP_MAX_ID 0x5FU
416#define STM32MP1_UPPER_OTP_START 0x20U
417
418#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
419
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100420/* OTP labels */
421#define CFG0_OTP "cfg0_otp"
422#define PART_NUMBER_OTP "part_number_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100423#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100424#define PACKAGE_OTP "package_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100425#endif
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100426#define HW2_OTP "hw2_otp"
427#define NAND_OTP "nand_otp"
Yann Gautier5c1dab32019-04-17 15:12:58 +0200428#define MONOTONIC_OTP "monotonic_otp"
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100429#define UID_OTP "uid_otp"
430#define BOARD_ID_OTP "board_id"
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100431
432/* OTP mask */
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100433/* CFG0 */
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100434#if STM32MP13
435#define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
436#define CFG0_OTP_MODE_SHIFT 0
437#define CFG0_OPEN_DEVICE 0x17U
438#define CFG0_CLOSED_DEVICE 0x3FU
439#define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
440#define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
441#endif
442#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100443#define CFG0_CLOSED_DEVICE BIT(6)
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100444#endif
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100445
Yann Gautierc7374052019-06-04 18:02:37 +0200446/* PART NUMBER */
Yann Gautier16188f32020-02-12 15:38:34 +0100447#if STM32MP13
448#define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
449#endif
450#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200451#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
Yann Gautier16188f32020-02-12 15:38:34 +0100452#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200453#define PART_NUMBER_OTP_PART_SHIFT 0
454
455/* PACKAGE */
Yann Gautier16188f32020-02-12 15:38:34 +0100456#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200457#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
458#define PACKAGE_OTP_PKG_SHIFT 27
Yann Gautier16188f32020-02-12 15:38:34 +0100459#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200460
Yann Gautier091eab52019-06-04 18:06:34 +0200461/* IWDG OTP */
462#define HW2_OTP_IWDG_HW_POS U(3)
463#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
464#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
465
Yann Gautier3edc7c32019-05-20 19:17:08 +0200466/* HW2 OTP */
467#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
468
Lionel Debieve402a46b2019-11-04 12:28:15 +0100469/* NAND OTP */
470/* NAND parameter storage flag */
471#define NAND_PARAM_STORED_IN_OTP BIT(31)
472
473/* NAND page size in bytes */
474#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
475#define NAND_PAGE_SIZE_SHIFT 29
476#define NAND_PAGE_SIZE_2K U(0)
477#define NAND_PAGE_SIZE_4K U(1)
478#define NAND_PAGE_SIZE_8K U(2)
479
480/* NAND block size in pages */
481#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
482#define NAND_BLOCK_SIZE_SHIFT 27
483#define NAND_BLOCK_SIZE_64_PAGES U(0)
484#define NAND_BLOCK_SIZE_128_PAGES U(1)
485#define NAND_BLOCK_SIZE_256_PAGES U(2)
486
487/* NAND number of block (in unit of 256 blocs) */
488#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
489#define NAND_BLOCK_NB_SHIFT 19
490#define NAND_BLOCK_NB_UNIT U(256)
491
492/* NAND bus width in bits */
493#define NAND_WIDTH_MASK BIT(18)
494#define NAND_WIDTH_SHIFT 18
495
496/* NAND number of ECC bits per 512 bytes */
497#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
498#define NAND_ECC_BIT_NB_SHIFT 15
499#define NAND_ECC_BIT_NB_UNSET U(0)
500#define NAND_ECC_BIT_NB_1_BITS U(1)
501#define NAND_ECC_BIT_NB_4_BITS U(2)
502#define NAND_ECC_BIT_NB_8_BITS U(3)
503#define NAND_ECC_ON_DIE U(4)
504
Lionel Debieve186b0462019-09-24 18:30:12 +0200505/* NAND number of planes */
506#define NAND_PLANE_BIT_NB_MASK BIT(14)
507
Yann Gautier5c1dab32019-04-17 15:12:58 +0200508/* MONOTONIC OTP */
509#define MAX_MONOTONIC_VALUE 32
510
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200511/* UID OTP */
512#define UID_WORD_NB U(3)
513
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100514/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200515 * STM32MP1 TAMP
516 ******************************************************************************/
517#define TAMP_BASE U(0x5C00A000)
518#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
519
Julius Werner53456fc2019-07-09 13:49:11 -0700520#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Nicolas Toromanoffbb82b1b2022-02-09 12:26:31 +0100521static inline uintptr_t tamp_bkpr(uint32_t idx)
Yann Gautier41934662018-07-20 11:36:05 +0200522{
523 return TAMP_BKP_REGISTER_BASE + (idx << 2);
524}
525#endif
526
527/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200528 * STM32MP1 USB
529 ******************************************************************************/
530#define USB_OTG_BASE U(0x49000000)
531
532/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200533 * STM32MP1 DDRCTRL
534 ******************************************************************************/
535#define DDRCTRL_BASE U(0x5A003000)
536
537/*******************************************************************************
538 * STM32MP1 DDRPHYC
539 ******************************************************************************/
540#define DDRPHYC_BASE U(0x5A004000)
541
542/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200543 * STM32MP1 IWDG
544 ******************************************************************************/
545#define IWDG_MAX_INSTANCE U(2)
546#define IWDG1_INST U(0)
547#define IWDG2_INST U(1)
548
549#define IWDG1_BASE U(0x5C003000)
550#define IWDG2_BASE U(0x5A002000)
551
552/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200553 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200554 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200555#define BSEC_BASE U(0x5C005000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100556#if STM32MP13
557#define CRYP_BASE U(0x54002000)
558#endif
559#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200560#define CRYP1_BASE U(0x54001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100561#endif
Yann Gautier091eab52019-06-04 18:06:34 +0200562#define DBGMCU_BASE U(0x50081000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100563#if STM32MP13
564#define HASH_BASE U(0x54003000)
565#endif
566#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200567#define HASH1_BASE U(0x54002000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100568#endif
569#if STM32MP13
570#define I2C3_BASE U(0x4C004000)
571#define I2C4_BASE U(0x4C005000)
572#define I2C5_BASE U(0x4C006000)
573#endif
574#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200575#define I2C4_BASE U(0x5C002000)
576#define I2C6_BASE U(0x5c009000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100577#endif
578#if STM32MP13
579#define RNG_BASE U(0x54004000)
580#endif
581#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200582#define RNG1_BASE U(0x54003000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100583#endif
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200584#define RTC_BASE U(0x5c004000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100585#if STM32MP13
586#define SPI4_BASE U(0x4C002000)
587#define SPI5_BASE U(0x4C003000)
588#endif
589#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200590#define SPI6_BASE U(0x5c001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100591#endif
Yann Gautiera18f61b2020-05-05 17:58:40 +0200592#define STGEN_BASE U(0x5c008000)
593#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200594
595/*******************************************************************************
Yann Gautier434fa2d2021-03-23 15:25:04 +0100596 * STM32MP13 SAES
597 ******************************************************************************/
598#define SAES_BASE U(0x54005000)
599
600/*******************************************************************************
601 * STM32MP13 PKA
602 ******************************************************************************/
603#define PKA_BASE U(0x54006000)
604
605/*******************************************************************************
Yann Gautierb1279e72021-12-15 13:16:15 +0100606 * REGULATORS
607 ******************************************************************************/
608/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
609#define PLAT_NB_RDEVS U(19)
Lionel Debieve84cbde32021-04-15 08:27:28 +0200610/* 2 FIXED */
611#define PLAT_NB_FIXED_REGS U(2)
Yann Gautierb1279e72021-12-15 13:16:15 +0100612
613/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100614 * Device Tree defines
615 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200616#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +0200617#define DT_DDR_COMPAT "st,stm32mp1-ddr"
Yann Gautier091eab52019-06-04 18:06:34 +0200618#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Nicolas Le Bayone4ac5582019-09-10 10:26:50 +0200619#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200620#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100621#if STM32MP13
622#define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
623#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
624#endif
625#if STM32MP15
Yann Gautier4d429472019-02-14 11:15:20 +0100626#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Lionel Debieve3c0fbfe2020-12-15 10:35:59 +0100627#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100628#endif
Yann Gautier006bb512021-01-20 14:10:57 +0100629#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
Yann Gautier4d429472019-02-14 11:15:20 +0100630
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200631#endif /* STM32MP1_DEF_H */