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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7c6df5b2018-01-15 14:43:42 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch.h>
8#include <arm_def.h>
Daniel Boulby45a2c9e2018-07-06 16:54:44 +01009#include <assert.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000010#include <bl1.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000012#include <plat_arm.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000013#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010014#include <platform_def.h>
Juan Castillob6132f12015-10-06 14:01:35 +010015#include <sp805.h>
Sandrine Bailleux28ee10f2016-06-15 15:44:27 +010016#include <utils.h>
Antonio Nino Diaz61aff002018-10-19 16:52:22 +010017#include <xlat_tables_compat.h>
18
Sandrine Bailleuxd7c47502015-10-02 09:32:35 +010019#include "../../../bl1/bl1_private.h"
Dan Handley9df48042015-03-19 18:58:55 +000020
Dan Handley9df48042015-03-19 18:58:55 +000021/* Weak definitions may be overridden in specific ARM standard platform */
22#pragma weak bl1_early_platform_setup
23#pragma weak bl1_plat_arch_setup
24#pragma weak bl1_platform_setup
25#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000026#pragma weak bl1_plat_prepare_exit
Sathees Balya22576072018-09-03 17:41:13 +010027#pragma weak bl1_plat_get_next_image_id
28#pragma weak plat_arm_bl1_fwu_needed
Dan Handley9df48042015-03-19 18:58:55 +000029
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010030#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
31 bl1_tzram_layout.total_base, \
32 bl1_tzram_layout.total_size, \
33 MT_MEMORY | MT_RW | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010034/*
35 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
36 * otherwise one region is defined containing both
37 */
38#if SEPARATE_CODE_AND_RODATA
39#define MAP_BL1_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010040 BL_CODE_BASE, \
41 BL1_CODE_END - BL_CODE_BASE, \
Daniel Boulby4e97abd2018-07-16 14:09:15 +010042 MT_CODE | MT_SECURE), \
43 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010044 BL1_RO_DATA_BASE, \
45 BL1_RO_DATA_END \
46 - BL_RO_DATA_BASE, \
47 MT_RO_DATA | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010048#else
49#define MAP_BL1_RO MAP_REGION_FLAT( \
50 BL_CODE_BASE, \
51 BL1_CODE_END - BL_CODE_BASE, \
52 MT_CODE | MT_SECURE)
53#endif
Dan Handley9df48042015-03-19 18:58:55 +000054
55/* Data structure which holds the extents of the trusted SRAM for BL1*/
56static meminfo_t bl1_tzram_layout;
57
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020058struct meminfo *bl1_plat_sec_mem_layout(void)
Dan Handley9df48042015-03-19 18:58:55 +000059{
60 return &bl1_tzram_layout;
61}
62
63/*******************************************************************************
64 * BL1 specific platform actions shared between ARM standard platforms.
65 ******************************************************************************/
66void arm_bl1_early_platform_setup(void)
67{
Dan Handley9df48042015-03-19 18:58:55 +000068
Juan Castillob6132f12015-10-06 14:01:35 +010069#if !ARM_DISABLE_TRUSTED_WDOG
70 /* Enable watchdog */
71 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
72#endif
73
Dan Handley9df48042015-03-19 18:58:55 +000074 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010075 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000076
77 /* Allow BL1 to see the whole Trusted RAM */
78 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
79 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
Dan Handley9df48042015-03-19 18:58:55 +000080}
81
82void bl1_early_platform_setup(void)
83{
84 arm_bl1_early_platform_setup();
85
86 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000087 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000088 * No need for locks as no other CPU is active.
89 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000090 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000091 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000092 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000093 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000094 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +000095}
96
97/******************************************************************************
98 * Perform the very early platform specific architecture setup shared between
99 * ARM standard platforms. This only does basic initialization. Later
100 * architectural setup (bl1_arch_setup()) does not do anything platform
101 * specific.
102 *****************************************************************************/
103void arm_bl1_plat_arch_setup(void)
104{
Soby Mathewb9856482018-09-18 11:42:42 +0100105#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
106 /*
107 * Ensure ARM platforms don't use coherent memory in BL1 unless
108 * cryptocell integration is enabled.
109 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100110 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000111#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100112
113 const mmap_region_t bl_regions[] = {
114 MAP_BL1_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100115 MAP_BL1_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100116#if USE_ROMLIB
117 ARM_MAP_ROMLIB_CODE,
118 ARM_MAP_ROMLIB_DATA,
Soby Mathewb9856482018-09-18 11:42:42 +0100119#endif
120#if ARM_CRYPTOCELL_INTEG
121 ARM_MAP_BL_COHERENT_RAM,
122#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100123 {0}
124 };
125
Roberto Vargas344ff022018-10-19 16:44:18 +0100126 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100127#ifdef AARCH32
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100128 enable_mmu_svc_mon(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100129#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100130 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100131#endif /* AARCH32 */
Roberto Vargase3adc372018-05-23 09:27:06 +0100132
133 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000134}
135
136void bl1_plat_arch_setup(void)
137{
138 arm_bl1_plat_arch_setup();
139}
140
141/*
142 * Perform the platform specific architecture setup shared between
143 * ARM standard platforms.
144 */
145void arm_bl1_platform_setup(void)
146{
147 /* Initialise the IO layer and register platform IO devices */
148 plat_arm_io_setup();
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000149 arm_load_tb_fw_config();
John Tsichritzisc34341a2018-07-30 13:41:52 +0100150#if TRUSTED_BOARD_BOOT
151 /* Share the Mbed TLS heap info with other images */
152 arm_bl1_set_mbedtls_heap();
153#endif /* TRUSTED_BOARD_BOOT */
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100154
Soby Mathewd969a7e2018-06-11 16:40:36 +0100155 /*
156 * Allow access to the System counter timer module and program
157 * counter frequency for non secure images during FWU
158 */
159 arm_configure_sys_timer();
160 write_cntfrq_el0(plat_get_syscnt_freq2());
Dan Handley9df48042015-03-19 18:58:55 +0000161}
162
163void bl1_platform_setup(void)
164{
165 arm_bl1_platform_setup();
166}
167
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000168void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
169{
Juan Castillob6132f12015-10-06 14:01:35 +0100170#if !ARM_DISABLE_TRUSTED_WDOG
171 /* Disable watchdog before leaving BL1 */
172 sp805_stop(ARM_SP805_TWDG_BASE);
173#endif
174
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000175#ifdef EL3_PAYLOAD_BASE
176 /*
177 * Program the EL3 payload's entry point address into the CPUs mailbox
178 * in order to release secondary CPUs from their holding pen and make
179 * them jump there.
180 */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100181 plat_arm_program_trusted_mailbox(ep_info->pc);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000182 dsbsy();
183 sev();
184#endif
185}
Soby Mathew94273572018-03-07 11:32:04 +0000186
Sathees Balya22576072018-09-03 17:41:13 +0100187/*
188 * On Arm platforms, the FWU process is triggered when the FIP image has
189 * been tampered with.
190 */
191int plat_arm_bl1_fwu_needed(void)
192{
193 return (arm_io_is_toc_valid() != 1);
194}
195
Soby Mathew94273572018-03-07 11:32:04 +0000196/*******************************************************************************
197 * The following function checks if Firmware update is needed,
198 * by checking if TOC in FIP image is valid or not.
199 ******************************************************************************/
200unsigned int bl1_plat_get_next_image_id(void)
201{
Sathees Balya22576072018-09-03 17:41:13 +0100202 if (plat_arm_bl1_fwu_needed() != 0)
Soby Mathew94273572018-03-07 11:32:04 +0000203 return NS_BL1U_IMAGE_ID;
204
205 return BL2_IMAGE_ID;
206}