blob: 77308965e9cf660449d44ba2d33ef255c7de6c41 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
32#include <gicv3.h>
33#include <platform.h>
34#include <platform_def.h>
Sandrine Bailleux7659a262016-07-05 09:55:03 +010035#include <utils.h>
Tony Xief6118cc2016-01-15 17:17:32 +080036
37/******************************************************************************
38 * The following functions are defined as weak to allow a platform to override
39 * the way the GICv3 driver is initialised and used.
40 *****************************************************************************/
41#pragma weak plat_rockchip_gic_driver_init
42#pragma weak plat_rockchip_gic_init
43#pragma weak plat_rockchip_gic_cpuif_enable
44#pragma weak plat_rockchip_gic_cpuif_disable
45#pragma weak plat_rockchip_gic_pcpu_init
46
47/* The GICv3 driver only needs to be initialized in EL3 */
48uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
49
50/* Array of Group1 secure interrupts to be configured by the gic driver */
51const unsigned int g1s_interrupt_array[] = {
52 PLAT_RK_G1S_IRQS
53};
54
55/* Array of Group0 interrupts to be configured by the gic driver */
56const unsigned int g0_interrupt_array[] = {
57 PLAT_RK_G0_IRQS
58};
59
60static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
61{
62 return (unsigned int)plat_core_pos_by_mpidr(mpidr);
63}
64
65const gicv3_driver_data_t rockchip_gic_data = {
66 .gicd_base = PLAT_RK_GICD_BASE,
67 .gicr_base = PLAT_RK_GICR_BASE,
68 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
69 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
70 .g0_interrupt_array = g0_interrupt_array,
71 .g1s_interrupt_array = g1s_interrupt_array,
72 .rdistif_num = PLATFORM_CORE_COUNT,
73 .rdistif_base_addrs = rdistif_base_addrs,
74 .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,
75};
76
77void plat_rockchip_gic_driver_init(void)
78{
79 /*
80 * The GICv3 driver is initialized in EL3 and does not need
81 * to be initialized again in SEL1. This is because the S-EL1
82 * can use GIC system registers to manage interrupts and does
83 * not need GIC interface base addresses to be configured.
84 */
85#if IMAGE_BL31
86 gicv3_driver_init(&rockchip_gic_data);
87#endif
88}
89
90/******************************************************************************
91 * RockChip common helper to initialize the GIC. Only invoked
92 * by BL31
93 *****************************************************************************/
94void plat_rockchip_gic_init(void)
95{
96 gicv3_distif_init();
97 gicv3_rdistif_init(plat_my_core_pos());
98 gicv3_cpuif_enable(plat_my_core_pos());
99}
100
101/******************************************************************************
102 * RockChip common helper to enable the GIC CPU interface
103 *****************************************************************************/
104void plat_rockchip_gic_cpuif_enable(void)
105{
106 gicv3_cpuif_enable(plat_my_core_pos());
107}
108
109/******************************************************************************
110 * RockChip common helper to disable the GIC CPU interface
111 *****************************************************************************/
112void plat_rockchip_gic_cpuif_disable(void)
113{
114 gicv3_cpuif_disable(plat_my_core_pos());
115}
116
117/******************************************************************************
118 * RockChip common helper to initialize the per-cpu redistributor interface
119 * in GICv3
120 *****************************************************************************/
121void plat_rockchip_gic_pcpu_init(void)
122{
123 gicv3_rdistif_init(plat_my_core_pos());
124}