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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
Manish V Badarkheb59efca2023-06-27 11:40:21 +010048- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded
49 SP nodes in tb_fw_config.
50
51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
53
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010054- ``BL2``: This is an optional build option which specifies the path to BL2
55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
56 built.
57
58- ``BL2U``: This is an optional build option which specifies the path to
59 BL2U image. In this case, the BL2U in TF-A will not be built.
60
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060061- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
63 entrypoint) or 1 (CPU reset to BL2 entrypoint).
64 The default value is 0.
65
66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3.
67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be
68 true in a 4-world system where RESET_TO_BL2 is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010069
Balint Dobszay719ba9c2021-03-26 16:23:18 +010070- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
72
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010073- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
75 the RW sections in RAM, while leaving the RO sections in place. This option
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060076 enable this use-case. For now, this option is only supported
77 when RESET_TO_BL2 is set to '1'.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010078
79- ``BL31``: This is an optional build option which specifies the path to
80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
81 be built.
82
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +020083- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If
85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010086
87- ``BL32``: This is an optional build option which specifies the path to
88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
89 be built.
90
91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
92 Trusted OS Extra1 image for the ``fip`` target.
93
94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
95 Trusted OS Extra2 image for the ``fip`` target.
96
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +020097- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If
99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100100
101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
102 ``fip`` target in case TF-A BL2 is used.
103
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +0200104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If
106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100107
108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
110 If enabled, it is needed to use a compiler that supports the option
111 ``-mbranch-protection``. Selects the branch protection features to use:
112- 0: Default value turns off all types of branch protection
113- 1: Enables all types of branch protection features
114- 2: Return address signing to its standard level
115- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100116- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100117
118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
119 and resulting PAuth/BTI features.
120
121 +-------+--------------+-------+-----+
122 | Value | GCC option | PAuth | BTI |
123 +=======+==============+=======+=====+
124 | 0 | none | N | N |
125 +-------+--------------+-------+-----+
126 | 1 | standard | Y | Y |
127 +-------+--------------+-------+-----+
128 | 2 | pac-ret | Y | N |
129 +-------+--------------+-------+-----+
130 | 3 | pac-ret+leaf | Y | N |
131 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100132 | 4 | bti | N | Y |
133 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100134
Manish Pandey34a305e2021-10-21 21:53:49 +0100135 This option defaults to 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100136 Note that Pointer Authentication is enabled for Non-secure world
137 irrespective of the value of this option if the CPU supports it.
138
139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
140 compilation of each build. It must be set to a C string (including quotes
141 where applicable). Defaults to a string that contains the time and date of
142 the compilation.
143
144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
145 build to be uniquely identified. Defaults to the current git commit id.
146
Grant Likely388248a2020-07-30 08:50:10 +0100147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
148
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100149- ``CFLAGS``: Extra user options appended on the compiler's command line in
150 addition to the options set by the build system.
151
152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
153 release several CPUs out of reset. It can take either 0 (several CPUs may be
154 brought up) or 1 (only one CPU will ever be brought up during cold reset).
155 Default is 0. If the platform always brings up a single CPU, there is no
156 need to distinguish between primary and secondary CPUs and the boot path can
157 be optimised. The ``plat_is_my_cpu_primary()`` and
158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
159 to be implemented in this case.
160
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
162 Defaults to ``tbbr``.
163
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
165 register state when an unexpected exception occurs during execution of
166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
167 this is only enabled for a debug build of the firmware.
168
169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
170 certificate generation tool to create new keys in case no valid keys are
171 present or specified. Allowed options are '0' or '1'. Default is '1'.
172
173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
174 the AArch32 system registers to be included when saving and restoring the
175 CPU context. The option must be set to 0 for AArch64-only platforms (that
176 is on hardware that does not implement AArch32, or at least not at EL1 and
177 higher ELs). Default value is 1.
178
179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
180 registers to be included when saving and restoring the CPU context. Default
181 is 0.
182
Arvind Ram Prakash4851b492023-10-06 14:35:21 -0500183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the
184 Memory System Resource Partitioning and Monitoring (MPAM)
185 registers to be included when saving and restoring the CPU context.
186 Default is '0'.
187
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000188- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
189 registers to be saved/restored when entering/exiting an EL2 execution
190 context. This flag can take values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000191 ``ENABLE_FEAT`` mechanism. Default value is 0.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000192
193- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
194 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
195 to be included when saving and restoring the CPU context as part of world
Andre Przywara9563c502023-11-23 16:40:13 +0000196 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000197 mechanism. Default value is 0.
198
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100199 Note that Pointer Authentication is enabled for Non-secure world irrespective
200 of the value of this flag if the CPU supports it.
201
202- ``DEBUG``: Chooses between a debug and release build. It can take either 0
203 (release) or 1 (debug) as values. 0 is the default.
204
Sumit Garg392e4df2019-11-15 10:43:00 +0530205- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
206 authenticated decryption algorithm to be used to decrypt firmware/s during
207 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
208 this flag is ``none`` to disable firmware decryption which is an optional
Manish Pandey34a305e2021-10-21 21:53:49 +0100209 feature as per TBBR.
Sumit Garg392e4df2019-11-15 10:43:00 +0530210
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100211- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
212 of the binary image. If set to 1, then only the ELF image is built.
213 0 is the default.
214
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000215- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded
216 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards.
Andre Przywara9563c502023-11-23 16:40:13 +0000217 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000218 mechanism. Default is ``0``.
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000219
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100220- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
221 Board Boot authentication at runtime. This option is meant to be enabled only
222 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
223 flag has to be enabled. 0 is the default.
224
225- ``E``: Boolean option to make warnings into errors. Default is 1.
226
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +0000227 When specifying higher warnings levels (``W=1`` and higher), this option
228 defaults to 0. This is done to encourage contributors to use them, as they
229 are expected to produce warnings that would otherwise fail the build. New
230 contributions are still expected to build with ``W=0`` and ``E=1`` (the
231 default).
232
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100233- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
234 the normal boot flow. It must specify the entry point address of the EL3
235 payload. Please refer to the "Booting an EL3 payload" section for more
236 details.
237
Chris Kay925fda42021-05-25 10:42:56 +0100238- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
239 (also known as group 1 counters). These are implementation-defined counters,
240 and as such require additional platform configuration. Default is 0.
241
Chris Kayf11909f2021-08-19 11:21:52 +0100242- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which
243 allows platforms with auxiliary counters to describe them via the
244 ``HW_CONFIG`` device tree blob. Default is 0.
245
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100246- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
247 are compiled out. For debug builds, this option defaults to 1, and calls to
248 ``assert()`` are left in place. For release builds, this option defaults to 0
249 and calls to ``assert()`` function are compiled out. This option can be set
250 independently of ``DEBUG``. It can also be used to hide any auxiliary code
251 that is only required for the assertion and does not fit in the assertion
252 itself.
253
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000254- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100255 dumps or not. It is supported in both AArch64 and AArch32. However, in
256 AArch32 the format of the frame records are not defined in the AAPCS and they
257 are defined by the implementation. This implementation of backtrace only
258 supports the format used by GCC when T32 interworking is disabled. For this
259 reason enabling this option in AArch32 will force the compiler to only
260 generate A32 code. This option is enabled by default only in AArch64 debug
261 builds, but this behaviour can be overridden in each platform's Makefile or
262 in the build command line.
263
Andre Przywara9563c502023-11-23 16:40:13 +0000264- ``ENABLE_FEAT``
265 The Arm architecture defines several architecture extension features,
266 named FEAT_xxx in the architecure manual. Some of those features require
267 setup code in higher exception levels, other features might be used by TF-A
268 code itself.
269 Most of the feature flags defined in the TF-A build system permit to take
270 the values 0, 1 or 2, with the following meaning:
271
272 ::
273
274 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time.
275 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time.
276 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime.
277
278 When setting the flag to 0, the feature is disabled during compilation,
279 and the compiler's optimisation stage and the linker will try to remove
280 as much of this code as possible.
281 If it is defined to 1, the code will use the feature unconditionally, so the
282 CPU is expected to support that feature. The FEATURE_DETECTION debug
283 feature, if enabled, will verify this.
284 If the feature flag is set to 2, support for the feature will be compiled
285 in, but its existence will be checked at runtime, so it works on CPUs with
286 or without the feature. This is mostly useful for platforms which either
287 support multiple different CPUs, or where the CPU is configured at runtime,
288 like in emulators.
289
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000290- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
291 extensions. This flag can take the values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000292 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000293 available on v8.4 onwards. Some v8.2 implementations also implement an AMU
294 and this option can be used to enable this feature on those systems as well.
295 This flag can take the values 0 to 2, the default is 0.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000296
297- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
298 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6
299 onwards. This flag can take the values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000300 ``ENABLE_FEAT`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000301
302- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
303 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
304 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an
305 optional feature available on Arm v8.0 onwards. This flag can take values
Andre Przywara9563c502023-11-23 16:40:13 +0000306 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000307 Default value is ``0``.
308
Sona Mathew3b84c962023-10-25 16:48:19 -0500309- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3``
310 extension. This feature is supported in AArch64 state only and is an optional
311 feature available in Arm v8.0 implementations.
312 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``.
313 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
314 mechanism. Default value is ``0``.
315
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000316- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
317 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
318 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
319 and upwards. This flag can take the values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000320 ``ENABLE_FEAT`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000321
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000322- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000323 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
324 Physical Offset register) during EL2 to EL3 context save/restore operations.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000325 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
Andre Przywara9563c502023-11-23 16:40:13 +0000326 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000327 mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000328
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000329- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000330 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000331 Read Trap Register) during EL2 to EL3 context save/restore operations.
332 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
Andre Przywara9563c502023-11-23 16:40:13 +0000333 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000334 mechanism. Default value is ``0``.
335
336- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
337 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
338 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
339 mandatory architectural feature and is enabled from v8.7 and upwards. This
Andre Przywara9563c502023-11-23 16:40:13 +0000340 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000341 mechanism. Default value is ``0``.
342
Govindraj Raja24d3a4e2023-12-21 13:57:49 -0600343- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension
Govindraj Rajad7b63ac2024-01-26 10:08:37 -0600344 if the platform wants to use this feature at EL0 ``ENABLE_FEAT_MTE`` is
345 required. This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
346 feature detection mechanism. Default value is ``0``.
347
348- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2
349 if the platform wants to use this feature and MTE2 is enabled at ELX.
350 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
351 mechanism. Default value is ``0``.
Govindraj Raja24d3a4e2023-12-21 13:57:49 -0600352
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000353- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for
354 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to
355 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural
356 feature available from v8.9 and upwards. This flag can take the values 0 to
Andre Przywara9563c502023-11-23 16:40:13 +0000357 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000358 ``0``.
359
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000360- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
361 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
362 permission fault for any privileged data access from EL1/EL2 to virtual
363 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a
364 mandatory architectural feature and is enabled from v8.1 and upwards. This
Andre Przywara9563c502023-11-23 16:40:13 +0000365 flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000366 mechanism. Default value is ``0``.
367
368- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
369 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
Andre Przywara9563c502023-11-23 16:40:13 +0000370 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400371 mechanism. Default value is ``0``.
372
373- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP``
374 extension. This feature is only supported in AArch64 state. This flag can
Andre Przywara9563c502023-11-23 16:40:13 +0000375 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400376 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
377 Armv8.5 onwards.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000378
Andre Przywara46880dc2022-11-17 16:42:09 +0000379- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
380 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
381 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
382 later CPUs. It is enabled from v8.5 and upwards and if needed can be
383 overidden from platforms explicitly.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000384
385- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
386 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
Andre Przywara9563c502023-11-23 16:40:13 +0000387 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000388 mechanism. Default is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000389
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100390- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed
391 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature
392 available on Arm v8.6. This flag can take values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000393 ``ENABLE_FEAT`` mechanism. Default is ``0``.
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100394
395 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets
396 delayed by the amount of value in ``TWED_DELAY``.
397
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000398- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization
399 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
400 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory
401 architectural feature and is enabled from v8.1 and upwards. It can take
Andre Przywara9563c502023-11-23 16:40:13 +0000402 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000403 Default value is ``0``.
johpow01f91e59f2021-08-04 19:38:18 -0500404
Mark Brownc37eee72023-03-14 20:13:03 +0000405- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to
406 allow access to TCR2_EL2 (extended translation control) from EL2 as
407 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a
408 mandatory architectural feature and is enabled from v8.9 and upwards. This
Andre Przywara9563c502023-11-23 16:40:13 +0000409 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Mark Brownc37eee72023-03-14 20:13:03 +0000410 mechanism. Default value is ``0``.
411
Mark Brown293a6612023-03-14 20:48:43 +0000412- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE
413 at EL2 and below, and context switch relevant registers. This flag
Andre Przywara9563c502023-11-23 16:40:13 +0000414 can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Mark Brown293a6612023-03-14 20:48:43 +0000415 mechanism. Default value is ``0``.
416
417- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE
418 at EL2 and below, and context switch relevant registers. This flag
Andre Przywara9563c502023-11-23 16:40:13 +0000419 can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Mark Brown293a6612023-03-14 20:48:43 +0000420 mechanism. Default value is ``0``.
421
422- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE
423 at EL2 and below, and context switch relevant registers. This flag
Andre Przywara9563c502023-11-23 16:40:13 +0000424 can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Mark Brown293a6612023-03-14 20:48:43 +0000425 mechanism. Default value is ``0``.
426
427- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE
428 at EL2 and below, and context switch relevant registers. This flag
Andre Przywara9563c502023-11-23 16:40:13 +0000429 can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Mark Brown293a6612023-03-14 20:48:43 +0000430 mechanism. Default value is ``0``.
431
Mark Brown326f2952023-03-14 21:33:04 +0000432- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to
433 allow use of Guarded Control Stack from EL2 as well as adding the GCS
434 registers to the EL2 context save/restore operations. This flag can take
Andre Przywara9563c502023-11-23 16:40:13 +0000435 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism.
Mark Brown326f2952023-03-14 21:33:04 +0000436 Default value is ``0``.
437
Sandrine Bailleux11427302019-12-17 09:38:08 +0100438- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600439 support in GCC for TF-A. This option is currently only supported for
440 AArch64. Default is 0.
441
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -0500442- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100443 feature. MPAM is an optional Armv8.4 extension that enables various memory
444 system components and resources to define partitions; software running at
445 various ELs can assign themselves to desired partition to control their
446 performance aspects.
447
Andre Przywara9563c502023-11-23 16:40:13 +0000448 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000449 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to
450 access their own MPAM registers without trapping into EL3. This option
451 doesn't make use of partitioning in EL3, however. Platform initialisation
452 code should configure and use partitions in EL3 as required. This option
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -0500453 defaults to ``2`` since MPAM is enabled by default for NS world only.
454 The flag is automatically disabled when the target
455 architecture is AArch32.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100456
Chris Kay03be39d2021-05-05 13:38:30 +0100457- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
458 Mitigation Mechanism supported by certain Arm cores, which allows the SoC
459 firmware to detect and limit high activity events to assist in SoC processor
460 power domain dynamic power budgeting and limit the triggering of whole-rail
461 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
462
463- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
464 allows platforms with cores supporting MPMM to describe them via the
465 ``HW_CONFIG`` device tree blob. Default is 0.
466
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100467- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
468 support within generic code in TF-A. This option is currently only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600469 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
470 in BL32 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100471
472- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
473 Measurement Framework(PMF). Default is 0.
474
475- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
476 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
477 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
478 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
479 software.
480
481- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
482 instrumentation which injects timestamp collection points into TF-A to
483 allow runtime performance to be measured. Currently, only PSCI is
484 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
485 as well. Default is 0.
486
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000487- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100488 extensions. This is an optional architectural feature for AArch64.
Andre Przywara9563c502023-11-23 16:40:13 +0000489 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000490 mechanism. The default is 2 but is automatically disabled when the target
491 architecture is AArch32.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100492
Jayanth Dodderi Chidanandd62c6812023-03-07 10:43:19 +0000493- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100494 (SVE) for the Non-secure world only. SVE is an optional architectural feature
495 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000496 to SIMD and floating-point functionality from the Secure world is disabled by
497 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100498 This is to avoid corruption of the Non-secure world data in the Z-registers
499 which are aliased by the SIMD and FP registers. The build option is not
500 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000501 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
502 enabled. This flag can take the values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +0000503 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000504 used on systems that have SPM_MM enabled. The default is 1.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100505
Max Shvetsovc4502772021-03-22 11:59:37 +0000506- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
507 SVE is an optional architectural feature for AArch64. Note that this option
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000508 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
509 automatically disabled when the target architecture is AArch32.
Max Shvetsovc4502772021-03-22 11:59:37 +0000510
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100511- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
512 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
513 default value is set to "none". "strong" is the recommended stack protection
514 level if this feature is desired. "none" disables the stack protection. For
515 all values other than "none", the ``plat_get_stack_protector_canary()``
516 platform hook needs to be implemented. The value is passed as the last
517 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
518
Sumit Gargc0c369c2019-11-15 18:47:53 +0530519- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
Manish Pandey34a305e2021-10-21 21:53:49 +0100520 flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530521
522- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
Manish Pandey34a305e2021-10-21 21:53:49 +0100523 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530524
525- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
526 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
Manish Pandey34a305e2021-10-21 21:53:49 +0100527 on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530528
529- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
530 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
Manish Pandey34a305e2021-10-21 21:53:49 +0100531 build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530532
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100533- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
534 deprecated platform APIs, helper functions or drivers within Trusted
535 Firmware as error. It can take the value 1 (flag the use of deprecated
536 APIs as error) or 0. The default is 0.
537
Rajasekaran Kalidoss46359002023-05-09 12:28:07 +0200538- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
539 configure an Arm® Ethos™-N NPU. To use this service the target platform's
540 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
541 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
542 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
543
544- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
545 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and
546 ``TRUSTED_BOARD_BOOT`` to be enabled.
547
548- ``ETHOSN_NPU_FW``: location of the NPU firmware binary
549 (```ethosn.bin```). This firmware image will be included in the FIP and
550 loaded at runtime.
551
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100552- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
553 targeted at EL3. When set ``0`` (default), no exceptions are expected or
Raghu Krishnamurthy669bf402022-07-25 14:44:33 -0700554 handled at EL3, and a panic will result. The exception to this rule is when
555 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
556 occuring during normal world execution, are trapped to EL3. Any exception
557 trapped during secure world execution are trapped to the SPMC. This is
558 supported only for AArch64 builds.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100559
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100560- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
561 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
562 Default value is 40 (LOG_LEVEL_INFO).
563
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100564- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
565 injection from lower ELs, and this build option enables lower ELs to use
566 Error Records accessed via System Registers to inject faults. This is
567 applicable only to AArch64 builds.
568
569 This feature is intended for testing purposes only, and is advisable to keep
570 disabled for production images.
571
572- ``FIP_NAME``: This is an optional build option which specifies the FIP
573 filename for the ``fip`` target. Default is ``fip.bin``.
574
575- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
576 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
577
Sumit Gargc0c369c2019-11-15 18:47:53 +0530578- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
579
580 ::
581
582 0: Encryption is done with Secret Symmetric Key (SSK) which is common
583 for a class of devices.
584 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
585 unique per device.
586
Manish Pandey34a305e2021-10-21 21:53:49 +0100587 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530588
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100589- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
590 tool to create certificates as per the Chain of Trust described in
591 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
592 include the certificates in the FIP and FWU_FIP. Default value is '0'.
593
594 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
595 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
596 the corresponding certificates, and to include those certificates in the
597 FIP and FWU_FIP.
598
599 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
600 images will not include support for Trusted Board Boot. The FIP will still
601 include the corresponding certificates. This FIP can be used to verify the
602 Chain of Trust on the host machine through other mechanisms.
603
604 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
605 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
606 will not include the corresponding certificates, causing a boot failure.
607
608- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
609 inherent support for specific EL3 type interrupts. Setting this build option
610 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500611 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
612 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100613 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
614 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
615 the Secure Payload interrupts needs to be synchronously handed over to Secure
616 EL1 for handling. The default value of this option is ``0``, which means the
617 Group 0 interrupts are assumed to be handled by Secure EL1.
618
Manish Pandey0e3379d2022-10-10 11:43:08 +0100619- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
620 Interrupts, resulting from errors in NS world, will be always trapped in
621 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
622 will be trapped in the current exception level (or in EL1 if the current
623 exception level is EL0).
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100624
625- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
626 software operations are required for CPUs to enter and exit coherency.
627 However, newer systems exist where CPUs' entry to and exit from coherency
628 is managed in hardware. Such systems require software to only initiate these
629 operations, and the rest is managed in hardware, minimizing active software
630 management. In such systems, this boolean option enables TF-A to carry out
631 build and run-time optimizations during boot and power management operations.
632 This option defaults to 0 and if it is enabled, then it implies
633 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
634
635 If this flag is disabled while the platform which TF-A is compiled for
636 includes cores that manage coherency in hardware, then a compilation error is
637 generated. This is based on the fact that a system cannot have, at the same
638 time, cores that manage coherency in hardware and cores that don't. In other
639 words, a platform cannot have, at the same time, cores that require
640 ``HW_ASSISTED_COHERENCY=1`` and cores that require
641 ``HW_ASSISTED_COHERENCY=0``.
642
643 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
644 translation library (xlat tables v2) must be used; version 1 of translation
645 library is not supported.
646
Varun Wadekar0a46eb12023-04-13 21:06:18 +0100647- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for
648 implementation defined system register accesses from lower ELs. Default
649 value is ``0``.
650
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000651- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000652 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000653 invert this behavior. Lower addresses will be printed at the top and higher
654 addresses at the bottom.
655
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100656- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
657 used for generating the PKCS keys and subsequent signing of the certificate.
Lionel Debievefefeffb2022-11-14 11:03:42 +0100658 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular``
659 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1
660 RSA 1.5 algorithm which is not TBBR compliant and is retained only for
661 compatibility. The default value of this flag is ``rsa`` which is the TBBR
662 compliant PKCS#1 RSA 2.1 scheme.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100663
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300664- ``KEY_SIZE``: This build flag enables the user to select the key size for
665 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
666 depend on the chosen algorithm and the cryptographic module.
667
Lionel Debievefefeffb2022-11-14 11:03:42 +0100668 +---------------------------+------------------------------------+
669 | KEY_ALG | Possible key sizes |
670 +===========================+====================================+
Sandrine Bailleux2f37ce62023-10-26 15:14:42 +0200671 | rsa | 1024 , 2048 (default), 3072, 4096 |
Lionel Debievefefeffb2022-11-14 11:03:42 +0100672 +---------------------------+------------------------------------+
laurenw-armc2a5dce2023-10-03 15:36:25 -0500673 | ecdsa | 256 (default), 384 |
Lionel Debievefefeffb2022-11-14 11:03:42 +0100674 +---------------------------+------------------------------------+
675 | ecdsa-brainpool-regular | unavailable |
676 +---------------------------+------------------------------------+
677 | ecdsa-brainpool-twisted | unavailable |
678 +---------------------------+------------------------------------+
679
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100680- ``HASH_ALG``: This build flag enables the user to select the secure hash
681 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
682 The default value of this flag is ``sha256``.
683
684- ``LDFLAGS``: Extra user options appended to the linkers' command line in
685 addition to the one set by the build system.
686
687- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
688 output compiled into the build. This should be one of the following:
689
690 ::
691
692 0 (LOG_LEVEL_NONE)
693 10 (LOG_LEVEL_ERROR)
694 20 (LOG_LEVEL_NOTICE)
695 30 (LOG_LEVEL_WARNING)
696 40 (LOG_LEVEL_INFO)
697 50 (LOG_LEVEL_VERBOSE)
698
699 All log output up to and including the selected log level is compiled into
700 the build. The default value is 40 in debug builds and 20 in release builds.
701
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000702- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Manish V Badarkhe92de80a2021-12-16 10:41:47 +0000703 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
704 provide trust that the code taking the measurements and recording them has
705 not been tampered with.
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200706
Manish Pandey34a305e2021-10-21 21:53:49 +0100707 This option defaults to 0.
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000708
Govindraj Raja81525652023-07-18 13:55:33 -0500709- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
710 options to the compiler. An example usage:
711
712 .. code:: make
713
714 MARCH_DIRECTIVE := -march=armv8.5-a
715
Bipin Ravie53e6ae2023-09-28 13:17:24 -0500716- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build
717 options to the compiler currently supporting only of the options.
718 GCC documentation:
719 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls
720
721 An example usage:
722
723 .. code:: make
724
725 HARDEN_SLS := 1
726
727 This option defaults to 0.
728
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100729- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +0200730 specifies a file that contains the Non-Trusted World private key in PEM
731 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it
732 will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100733
734- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
735 optional. It is only needed if the platform makefile specifies that it
736 is required in order to build the ``fwu_fip`` target.
737
738- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
739 contents upon world switch. It can take either 0 (don't save and restore) or
740 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
741 wants the timer registers to be saved and restored.
742
Manish V Badarkheb59efca2023-06-27 11:40:21 +0100743- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
744 tb_fw_config device tree. This flag is defined only when
745 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
746
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100747- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
748 for the BL image. It can be either 0 (include) or 1 (remove). The default
749 value is 0.
750
751- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
752 the underlying hardware is not a full PL011 UART but a minimally compliant
753 generic UART, which is a subset of the PL011. The driver will not access
754 any register that is not part of the SBSA generic UART specification.
755 Default value is 0 (a full PL011 compliant UART is present).
756
757- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
758 must be subdirectory of any depth under ``plat/``, and must contain a
759 platform makefile named ``platform.mk``. For example, to build TF-A for the
760 Arm Juno board, select PLAT=juno.
761
Juan Pablo Condeb5ec1382023-11-08 16:14:28 -0600762- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for
763 each core as well as the global context. The data includes the memory used
764 by each world and each privileged exception level. This build option is
765 applicable only for ``ARCH=aarch64`` builds. The default value is 0.
766
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100767- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
768 instead of the normal boot flow. When defined, it must specify the entry
769 point address for the preloaded BL33 image. This option is incompatible with
770 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
771 over ``PRELOADED_BL33_BASE``.
772
773- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
774 vector address can be programmed or is fixed on the platform. It can take
775 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
776 programmable reset address, it is expected that a CPU will start executing
777 code directly at the right address, both on a cold and warm reset. In this
778 case, there is no need to identify the entrypoint on boot and the boot path
779 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
780 does not need to be implemented in this case.
781
782- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
783 possible for the PSCI power-state parameter: original and extended State-ID
784 formats. This flag if set to 1, configures the generic PSCI layer to use the
785 extended format. The default value of this flag is 0, which means by default
786 the original power-state format is used by the PSCI implementation. This flag
787 should be specified by the platform makefile and it governs the return value
788 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
789 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
790 set to 1 as well.
791
Wing Li1e9b68a2023-01-26 18:33:36 -0800792- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
793 OS-initiated mode. This option defaults to 0.
794
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100795- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100796 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
Manish Pandey514a3012023-10-10 13:53:25 +0100797 or later CPUs. This flag can take the values 0 or 1. The default value is 0.
798 NOTE: This flag enables use of IESB capability to reduce entry latency into
799 EL3 even when RAS error handling is not performed on the platform. Hence this
800 flag is recommended to be turned on Armv8.2 and later CPUs.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100801
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100802- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
803 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
804 entrypoint) or 1 (CPU reset to BL31 entrypoint).
805 The default value is 0.
806
807- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
808 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
809 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
810 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
811
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +0200812- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
813 file that contains the ROT private key in PEM format or a PKCS11 URI and
814 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is
815 accepted and it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100816
817- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
818 certificate generation tool to save the keys used to establish the Chain of
819 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
820
821- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
822 If a SCP_BL2 image is present then this option must be passed for the ``fip``
823 target.
824
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +0200825- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
826 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI.
827 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100828
829- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
830 optional. It is only needed if the platform makefile specifies that it
831 is required in order to build the ``fwu_fip`` target.
832
833- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
834 Delegated Exception Interface to BL31 image. This defaults to ``0``.
835
836 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
837 set to ``1``.
838
839- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
840 isolated on separate memory pages. This is a trade-off between security and
841 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100842 pages" section in :ref:`Firmware Design`. This flag is disabled by default
843 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100844
Samuel Holland31a14e12018-10-17 21:40:18 -0500845- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
846 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
847 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000848 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500849 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
850 sections are placed in RAM immediately following the loaded firmware image.
851
Jiafei Pan0824b452022-02-24 10:47:33 +0800852- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
853 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
854 discontiguous from loaded firmware images. When set, the platform need to
855 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
856 flag is disabled by default and NOLOAD sections are placed in RAM immediately
857 following the loaded firmware image.
858
Jeremy Linton684a0792021-01-26 22:42:03 -0600859- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
860 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
861 UEFI+ACPI this can provide a certain amount of OS forward compatibility
862 with newer platforms that aren't ECAM compliant.
863
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100864- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
865 This build option is only valid if ``ARCH=aarch64``. The value should be
866 the path to the directory containing the SPD source, relative to
867 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100868 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
869 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
870 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100871
872- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
873 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
874 execution in BL1 just before handing over to BL31. At this point, all
875 firmware images have been loaded in memory, and the MMU and caches are
876 turned off. Refer to the "Debugging options" section for more details.
877
Marc Bonniciabaac162021-12-01 18:00:40 +0000878- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM
879 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
880 component runs at the EL3 exception level. The default value is ``0`` (
881 disabled). This configuration supports pre-Armv8.4 platforms (aka not
Olivier Deprezb6cd6702023-11-03 11:49:47 +0100882 implementing the ``FEAT_SEL2`` extension).
Marc Bonniciabaac162021-12-01 18:00:40 +0000883
Nishant Sharma9e719112023-06-27 00:36:01 +0100884- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when
885 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This
886 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled.
887
Jens Wiklanderba0ed3e2022-12-14 17:02:16 +0100888- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM
889 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to
890 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading
891 mechanism should be used.
892
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000893- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100894 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000895 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100896 extension. This is the default when enabling the SPM Dispatcher. When
897 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
Marc Bonniciabaac162021-12-01 18:00:40 +0000898 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations
899 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
900 extension).
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100901
Paul Beesleyfe975b42019-09-16 11:29:03 +0000902- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100903 Partition Manager (SPM) implementation. The default value is ``0``
904 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
905 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000906
Manish Pandey3f90ad72020-01-14 11:52:05 +0000907- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100908 description of secure partitions. The build system will parse this file and
909 package all secure partition blobs into the FIP. This file is not
910 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000911
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100912- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
913 secure interrupts (caught through the FIQ line). Platforms can enable
914 this directive if they need to handle such interruption. When enabled,
915 the FIQ are handled in monitor mode and non secure world is not allowed
916 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
917 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
918
Mark Brown64869972022-04-20 18:14:32 +0100919- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
920 Platforms can configure this if they need to lower the hardware
921 limit, for example due to asymmetric configuration or limitations of
922 software run at lower ELs. The default is the architectural maximum
923 of 2048 which should be suitable for most configurations, the
924 hardware will limit the effective VL to the maximum physically supported
925 VL.
926
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100927- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True
928 Random Number Generator Interface to BL31 image. This defaults to ``0``.
929
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100930- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
931 Boot feature. When set to '1', BL1 and BL2 images include support to load
932 and verify the certificates and images in a FIP, and BL1 includes support
933 for the Firmware Update. The default value is '0'. Generation and inclusion
934 of certificates in the FIP and FWU_FIP depends upon the value of the
935 ``GENERATE_COT`` option.
936
937 .. warning::
938 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
939 already exist in disk, they will be overwritten without further notice.
940
941- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
Robin van der Gracht06b5cdb2023-09-12 11:16:23 +0200942 specifies a file that contains the Trusted World private key in PEM
943 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and
944 it will be used to save the key.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100945
946- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
947 synchronous, (see "Initializing a BL32 Image" section in
948 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
949 synchronous method) or 1 (BL32 is initialized using asynchronous method).
950 Default is 0.
951
952- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
953 routing model which routes non-secure interrupts asynchronously from TSP
954 to EL3 causing immediate preemption of TSP. The EL3 is responsible
955 for saving and restoring the TSP context in this routing model. The
956 default routing model (when the value is 0) is to route non-secure
957 interrupts to TSP allowing it to save its context and hand over
958 synchronously to EL3 via an SMC.
959
960 .. note::
961 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
962 must also be set to ``1``.
963
Manish V Badarkheb59efca2023-06-27 11:40:21 +0100964- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
965 internal-trusted-storage) as SP in tb_fw_config device tree.
966
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100967- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
968 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set
969 this delay. It can take values in the range (0-15). Default value is ``0``
970 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed.
971 Platforms need to explicitly update this value based on their requirements.
972
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100973- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
974 linker. When the ``LINKER`` build variable points to the armlink linker,
975 this flag is enabled automatically. To enable support for armlink, platforms
976 will have to provide a scatter file for the BL image. Currently, Tegra
977 platforms use the armlink support to compile BL3-1 images.
978
979- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
980 memory region in the BL memory map or not (see "Use of Coherent memory in
981 TF-A" section in :ref:`Firmware Design`). It can take the value 1
982 (Coherent memory region is included) or 0 (Coherent memory region is
983 excluded). Default is 1.
984
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000985- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
986 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100987 configuration device tree, instead of static structure in the code base.
988
Manish V Badarkhead339892020-06-29 10:32:53 +0100989- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
990 at runtime using fconf. If this flag is enabled, COT descriptors are
991 statically captured in tb_fw_config file in the form of device tree nodes
992 and properties. Currently, COT descriptors used by BL2 are moved to the
993 device tree and COT descriptors used by BL1 are retained in the code
Manish Pandey34a305e2021-10-21 21:53:49 +0100994 base statically.
Manish V Badarkhead339892020-06-29 10:32:53 +0100995
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100996- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
997 runtime using firmware configuration framework. The platform specific SDEI
998 shared and private events configuration is retrieved from device tree rather
Manish Pandey34a305e2021-10-21 21:53:49 +0100999 than static C structures at compile time. This is only supported if
1000 SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +01001001
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -05001002- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
1003 and Group1 secure interrupts using the firmware configuration framework. The
1004 platform specific secure interrupt property descriptor is retrieved from
1005 device tree in runtime rather than depending on static C structure at compile
Manish Pandey34a305e2021-10-21 21:53:49 +01001006 time.
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -05001007
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001008- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
1009 This feature creates a library of functions to be placed in ROM and thus
1010 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
1011 is 0.
1012
1013- ``V``: Verbose build. If assigned anything other than 0, the build commands
1014 are printed. Default is 0.
1015
1016- ``VERSION_STRING``: String used in the log output for each TF-A image.
1017 Defaults to a string formed by concatenating the version number, build type
1018 and build string.
1019
1020- ``W``: Warning level. Some compiler warning options of interest have been
1021 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
1022 each level enabling more warning options. Default is 0.
1023
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001024 This option is closely related to the ``E`` option, which enables
1025 ``-Werror``.
1026
1027 - ``W=0`` (default)
1028
1029 Enables a wide assortment of warnings, most notably ``-Wall`` and
1030 ``-Wextra``, as well as various bad practices and things that are likely to
1031 result in errors. Includes some compiler specific flags. No warnings are
1032 expected at this level for any build.
1033
1034 - ``W=1``
1035
1036 Enables warnings we want the generic build to include but are too time
1037 consuming to fix at the moment. It re-enables warnings taken out for
1038 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected
1039 to eventually be merged into ``W=0``. Some warnings are expected on some
1040 builds, but new contributions should not introduce new ones.
1041
1042 - ``W=2`` (recommended)
1043
1044 Enables warnings we want the generic build to include but cannot be enabled
1045 due to external libraries. This level is expected to eventually be merged
1046 into ``W=0``. Lots of warnings are expected, primarily from external
1047 libraries like zlib and compiler-rt, but new controbutions should not
1048 introduce new ones.
1049
1050 - ``W=3``
1051
1052 Enables warnings that are informative but not necessary and generally too
1053 verbose and frequently ignored. A very large number of warnings are
1054 expected.
1055
1056 The exact set of warning flags depends on the compiler and TF-A warning
1057 level, however they are all succinctly set in the top-level Makefile. Please
1058 refer to the `GCC`_ or `Clang`_ documentation for more information on the
1059 individual flags.
1060
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001061- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
1062 the CPU after warm boot. This is applicable for platforms which do not
1063 require interconnect programming to enable cache coherency (eg: single
1064 cluster platforms). If this option is enabled, then warm boot path
1065 enables D-caches immediately after enabling MMU. This option defaults to 0.
1066
Manish V Badarkhe75c972a2020-03-22 05:06:38 +00001067- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
1068 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
1069 default value of this flag is ``no``. Note this option must be enabled only
1070 for ARM architecture greater than Armv8.5-A.
1071
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001072- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
1073 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
1074 The default value of this flag is ``0``.
1075
1076 ``AT`` speculative errata workaround disables stage1 page table walk for
1077 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
1078 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001079
1080 This boolean option enables errata for all below CPUs.
1081
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001082 +---------+--------------+-------------------------+
1083 | Errata | CPU | Workaround Define |
1084 +=========+==============+=========================+
1085 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
1086 +---------+--------------+-------------------------+
1087 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
1088 +---------+--------------+-------------------------+
1089 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
1090 +---------+--------------+-------------------------+
1091 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
1092 +---------+--------------+-------------------------+
1093 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
1094 +---------+--------------+-------------------------+
1095
1096 .. note::
1097 This option is enabled by build only if platform sets any of above defines
1098 mentioned in ’Workaround Define' column in the table.
1099 If this option is enabled for the EL3 software then EL2 software also must
1100 implement this workaround due to the behaviour of the errata mentioned
1101 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001102
Manish Pandey7c6fcb42022-09-27 14:30:34 +01001103- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
Varun Wadekar92234852020-06-12 10:11:28 -07001104 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
1105 This flag is disabled by default.
1106
Juan Pablo Conde52865522022-06-28 16:56:32 -04001107- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the
1108 host machine where a custom installation of OpenSSL is located, which is used
1109 to build the certificate generation, firmware encryption and FIP tools. If
1110 this option is not set, the default OS installation will be used.
Manish V Badarkhe3589b702020-07-29 10:58:44 +01001111
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -05001112- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
1113 functions that wait for an arbitrary time length (udelay and mdelay). The
1114 default value is 0.
1115
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001116- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record
1117 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1118 optional architectural feature for AArch64. This flag can take the values
Andre Przywara9563c502023-11-23 16:40:13 +00001119 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001120 and it is automatically disabled when the target architecture is AArch32.
johpow0181865962022-01-28 17:06:20 -06001121
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001122- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001123 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1124 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001125 feature for AArch64. This flag can take the values 0 to 2, to align with the
Andre Przywara9563c502023-11-23 16:40:13 +00001126 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001127 disabled when the target architecture is AArch32.
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001128
Andre Przywara44e33e02022-11-17 16:42:09 +00001129- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001130 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1131 but unused). This feature is available if trace unit such as ETMv4.x, and
Andre Przywara44e33e02022-11-17 16:42:09 +00001132 ETE(extending ETM feature) is implemented. This flag can take the values
Andre Przywara9563c502023-11-23 16:40:13 +00001133 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001134
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001135- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001136 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001137 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align
Andre Przywara9563c502023-11-23 16:40:13 +00001138 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001139
Okash Khawaja037b56e2022-11-04 12:38:01 +00001140- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine
1141 ``plat_can_cmo`` which will return zero if cache management operations should
1142 be skipped and non-zero otherwise. By default, this option is disabled which
1143 means platform hook won't be checked and CMOs will always be performed when
1144 related functions are called.
1145
Sona Mathew6315c582023-03-15 09:40:36 -05001146- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management
1147 firmware interface for the BL31 image. By default its disabled (``0``).
1148
1149- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the
1150 errata mitigation for platforms with a non-arm interconnect using the errata
1151 ABI. By default its disabled (``0``).
1152
Sandrine Bailleuxf57e2032023-10-11 08:38:00 +02001153- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console
1154 driver(s). By default it is disabled (``0``) because it constitutes an attack
1155 vector into TF-A by potentially allowing an attacker to inject arbitrary data.
1156 This option should only be enabled on a need basis if there is a use case for
1157 reading characters from the console.
1158
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001159GICv3 driver options
1160--------------------
1161
1162GICv3 driver files are included using directive:
1163
1164``include drivers/arm/gic/v3/gicv3.mk``
1165
1166The driver can be configured with the following options set in the platform
1167makefile:
1168
Andre Przywarae1cc1302020-03-25 15:50:38 +00001169- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
1170 Enabling this option will add runtime detection support for the
1171 GIC-600, so is safe to select even for a GIC500 implementation.
1172 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001173
Varun Wadekareea6dc12021-05-04 16:14:09 -07001174- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit
1175 for GIC-600 AE. Enabling this option will introduce support to initialize
1176 the FMU. Platforms should call the init function during boot to enable the
1177 FMU and its safety mechanisms. This option defaults to 0.
1178
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001179- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
1180 functionality. This option defaults to 0
1181
1182- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
1183 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
1184 functions. This is required for FVP platform which need to simulate GIC save
1185 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
1186
Alexei Fedorov19705932020-04-06 19:00:35 +01001187- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
1188 This option defaults to 0.
1189
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001190- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
1191 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
1192
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001193Debugging options
1194-----------------
1195
1196To compile a debug version and make the build more verbose use
1197
1198.. code:: shell
1199
1200 make PLAT=<platform> DEBUG=1 V=1 all
1201
Daniel Boulbydf83a832022-05-03 16:46:16 +01001202AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools
1203(for example Arm-DS) might not support this and may need an older version of
1204DWARF symbols to be emitted by GCC. This can be achieved by using the
1205``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting
1206the version to 4 is recommended for Arm-DS.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001207
1208When debugging logic problems it might also be useful to disable all compiler
1209optimizations by using ``-O0``.
1210
1211.. warning::
1212 Using ``-O0`` could cause output images to be larger and base addresses
1213 might need to be recalculated (see the **Memory layout on Arm development
1214 platforms** section in the :ref:`Firmware Design`).
1215
1216Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1217``LDFLAGS``:
1218
1219.. code:: shell
1220
1221 CFLAGS='-O0 -gdwarf-2' \
1222 make PLAT=<platform> DEBUG=1 V=1 all
1223
1224Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1225ignored as the linker is called directly.
1226
1227It is also possible to introduce an infinite loop to help in debugging the
1228post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1229``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
1230section. In this case, the developer may take control of the target using a
Daniel Boulbydf83a832022-05-03 16:46:16 +01001231debugger when indicated by the console output. When using Arm-DS, the following
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001232commands can be used:
1233
1234::
1235
1236 # Stop target execution
1237 interrupt
1238
1239 #
1240 # Prepare your debugging environment, e.g. set breakpoints
1241 #
1242
1243 # Jump over the debug loop
1244 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1245
1246 # Resume execution
1247 continue
1248
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001249.. _build_options_experimental:
1250
1251Experimental build options
1252---------------------------
1253
1254Common build options
1255~~~~~~~~~~~~~~~~~~~~
1256
1257- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
1258 for Measurement (DRTM). This feature has trust dependency on BL31 for taking
1259 the measurements and recording them as per `PSA DRTM specification`_. For
1260 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can
1261 be used and for the platforms which use ``RESET_TO_BL31`` platform owners
1262 should have mechanism to authenticate BL31. This option defaults to 0.
1263
1264- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm
1265 Management Extension. This flag can take the values 0 to 2, to align with
Andre Przywara9563c502023-11-23 16:40:13 +00001266 the ``ENABLE_FEAT`` mechanism. Default value is 0.
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001267
1268- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension
1269 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share
1270 registers so are enabled together. Using this option without
1271 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
1272 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
1273 superset of SVE. SME is an optional architectural feature for AArch64.
1274 At this time, this build option cannot be used on systems that have
1275 SPD=spmd/SPM_MM and atempting to build with this option will fail.
Andre Przywara9563c502023-11-23 16:40:13 +00001276 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001277 mechanism. Default is 0.
1278
1279- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension
1280 version 2 (SME2) for the non-secure world only. SME2 is an optional
1281 architectural feature for AArch64.
1282 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME
1283 accesses will still be trapped. This flag can take the values 0 to 2, to
Andre Przywara9563c502023-11-23 16:40:13 +00001284 align with the ``ENABLE_FEAT`` mechanism. Default is 0.
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001285
1286- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
1287 Extension for secure world. Used along with SVE and FPU/SIMD.
1288 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
1289 Default is 0.
1290
1291- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM
1292 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support
1293 for logical partitions in EL3, managed by the SPMD as defined in the
1294 FF-A v1.2 specification. This flag is disabled by default. This flag
1295 must not be used if ``SPMC_AT_EL3`` is enabled.
1296
1297- ``FEATURE_DETECTION``: Boolean option to enable the architectural features
Andre Przywara9563c502023-11-23 16:40:13 +00001298 verification mechanism. This is a debug feature that compares the
1299 architectural features enabled through the feature specific build flags
1300 (ENABLE_FEAT_xxx) with the features actually available on the CPU running,
1301 and reports any discrepancies.
1302 This flag will also enable errata ordering checking for ``DEBUG`` builds.
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001303
Andre Przywara9563c502023-11-23 16:40:13 +00001304 It is expected that this feature is only used for flexible platforms like
1305 software emulators, or for hardware platforms at bringup time, to verify
1306 that the configured feature set matches the CPU.
1307 The ``FEATURE_DETECTION`` macro is disabled by default.
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001308
1309- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support.
1310 The platform will use PSA compliant Crypto APIs during authentication and
1311 image measurement process by enabling this option. It uses APIs defined as
1312 per the `PSA Crypto API specification`_. This feature is only supported if
1313 using MbedTLS 3.x version. It is disabled (``0``) by default.
1314
1315- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware
1316 Handoff using Transfer List defined in `Firmware Handoff specification`_.
1317 This defaults to ``0``. Current implementation follows the Firmware Handoff
1318 specification v0.9.
1319
1320- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem
1321 interface through BL31 as a SiP SMC function.
1322 Default is disabled (0).
1323
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001324Firmware update options
Olivier Deprezb6cd6702023-11-03 11:49:47 +01001325~~~~~~~~~~~~~~~~~~~~~~~
1326
1327- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
1328 `PSA FW update specification`_. The default value is 0.
1329 PSA firmware update implementation has few limitations, such as:
1330
1331 - BL2 is not part of the protocol-updatable images. If BL2 needs to
1332 be updated, then it should be done through another platform-defined
1333 mechanism.
1334
1335 - It assumes the platform's hardware supports CRC32 instructions.
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001336
1337- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
1338 in defining the firmware update metadata structure. This flag is by default
1339 set to '2'.
1340
1341- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
1342 firmware bank. Each firmware bank must have the same number of images as per
1343 the `PSA FW update specification`_.
1344 This flag is used in defining the firmware update metadata structure. This
1345 flag is by default set to '1'.
1346
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001347--------------
1348
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06001349*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -06001350
1351.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001352.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Manish V Badarkhe8564f772022-02-14 18:31:16 +00001353.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001354.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
1355.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html
Raymond Mao98983392023-07-25 07:53:35 -07001356.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9
Manish V Badarkhe78e14f82023-09-06 09:08:28 +01001357.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/