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Jeenu Viswambharan5c503042017-05-26 14:15:40 +01001/*
Olivier Deprez73ad7312022-02-04 12:30:11 +01002 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SMMU_V3_H
8#define SMMU_V3_H
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01009
10#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Olivier Deprez73ad7312022-02-04 12:30:11 +010012#include <platform_def.h>
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010013
14/* SMMUv3 register offsets from device base */
Lucian Paul-Trifub666e712022-03-25 14:30:20 +000015#define SMMU_CR0 U(0x0020)
16#define SMMU_CR0ACK U(0x0024)
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010017#define SMMU_GBPA U(0x0044)
Antonio Nino Diazfeacba32018-08-21 16:12:29 +010018#define SMMU_S_IDR1 U(0x8004)
19#define SMMU_S_INIT U(0x803c)
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010020#define SMMU_S_GBPA U(0x8044)
21
Olivier Deprez73ad7312022-02-04 12:30:11 +010022/*
23 * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific.
24 * Currently defined as a command line model parameter.
25 */
26#if ENABLE_RME
27
28#define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET)
29#define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000)
30#define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008)
31#define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020)
32#define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024)
33#define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028)
34#define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030)
35#define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038)
36#define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040)
37#define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050)
38#define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058)
39
40#endif /* ENABLE_RME */
41
Lucian Paul-Trifub666e712022-03-25 14:30:20 +000042/* SMMU_CR0 and SMMU_CR0ACK register fields */
43#define SMMU_CR0_SMMUEN (1UL << 0)
44
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010045/* SMMU_GBPA register fields */
46#define SMMU_GBPA_UPDATE (1UL << 31)
47#define SMMU_GBPA_ABORT (1UL << 20)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010048
49/* SMMU_S_IDR1 register fields */
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010050#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010051
52/* SMMU_S_INIT register fields */
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010053#define SMMU_S_INIT_INV_ALL (1UL << 0)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010054
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010055/* SMMU_S_GBPA register fields */
56#define SMMU_S_GBPA_UPDATE (1UL << 31)
57#define SMMU_S_GBPA_ABORT (1UL << 20)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010058
Olivier Deprez73ad7312022-02-04 12:30:11 +010059/* SMMU_ROOT_IDR0 register fields */
60#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0)
61
62/* SMMU_ROOT_CR0 register fields */
63#define SMMU_ROOT_CR0_GPCEN (1UL << 1)
64#define SMMU_ROOT_CR0_ACCESSEN (1UL << 0)
65
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010066int smmuv3_init(uintptr_t smmu_base);
Alexei Fedorov896799a2019-05-09 12:14:40 +010067int smmuv3_security_init(uintptr_t smmu_base);
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010068
Lucian Paul-Trifub666e712022-03-25 14:30:20 +000069int smmuv3_ns_set_abort_all(uintptr_t smmu_base);
70
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000071#endif /* SMMU_V3_H */