Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef SGM_BASE_PLATFORM_DEF_H |
| 8 | #define SGM_BASE_PLATFORM_DEF_H |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <drivers/arm/tzc_common.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/board_css_def.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/arm/common/arm_def.h> |
| 15 | #include <plat/arm/css/common/css_def.h> |
| 16 | #include <plat/arm/soc/common/soc_css_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <plat/common/common_def.h> |
| 18 | |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 19 | /* CPU topology */ |
| 20 | #define PLAT_ARM_CLUSTER_COUNT 1 |
| 21 | #define PLAT_ARM_CLUSTER_CORE_COUNT 8 |
| 22 | #define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT |
| 23 | |
| 24 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 25 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
| 26 | PLAT_ARM_CLUSTER_COUNT + \ |
| 27 | PLATFORM_CORE_COUNT) |
| 28 | |
| 29 | /* |
| 30 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 31 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 32 | * as Group 0 interrupts. |
| 33 | */ |
| 34 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 35 | CSS_G1S_IRQ_PROPS(grp), \ |
| 36 | ARM_G1S_IRQ_PROPS(grp) |
| 37 | |
| 38 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 39 | |
| 40 | /* GIC related constants */ |
| 41 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 42 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 43 | #define PLAT_ARM_GICC_BASE 0x2c000000 |
| 44 | |
| 45 | #define CSS_GIC_SIZE 0x00200000 |
| 46 | |
| 47 | #define CSS_MAP_GIC_DEVICE MAP_REGION_FLAT( \ |
| 48 | PLAT_ARM_GICD_BASE, \ |
| 49 | CSS_GIC_SIZE, \ |
| 50 | MT_DEVICE | MT_RW | MT_SECURE) |
| 51 | |
| 52 | /* Platform ID address */ |
| 53 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
| 54 | #ifndef __ASSEMBLY__ |
| 55 | /* SSC_VERSION related accessors */ |
| 56 | /* Returns the part number of the platform */ |
| 57 | #define GET_PLAT_PART_NUM \ |
| 58 | GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) |
| 59 | /* Returns the configuration number of the platform */ |
| 60 | #define GET_PLAT_CONFIG_NUM \ |
| 61 | GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) |
| 62 | #endif /* __ASSEMBLY__ */ |
| 63 | |
| 64 | |
| 65 | /************************************************************************* |
| 66 | * Definitions common to all SGM CSS based platforms |
| 67 | *************************************************************************/ |
| 68 | |
| 69 | /* TZC-400 related constants */ |
| 70 | #define PLAT_ARM_TZC_BASE 0x2a500000 |
| 71 | #define TZC_NSAID_ALL_AP 0 /* Note: Same as default NSAID!! */ |
| 72 | #define TZC_NSAID_HDLCD0 2 |
| 73 | #define TZC_NSAID_HDLCD1 3 |
| 74 | #define TZC_NSAID_GPU 9 |
| 75 | #define TZC_NSAID_VIDEO 10 |
| 76 | #define TZC_NSAID_DISP0 11 |
| 77 | #define TZC_NSAID_DISP1 12 |
| 78 | |
| 79 | |
| 80 | /************************************************************************* |
| 81 | * Required platform porting definitions common to all SGM CSS based |
| 82 | * platforms |
| 83 | *************************************************************************/ |
| 84 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 85 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 86 | |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 87 | /* MHU related constants */ |
| 88 | #define PLAT_CSS_MHU_BASE 0x2b1f0000 |
Masahisa Kojima | 0d31688 | 2019-03-07 11:23:42 +0900 | [diff] [blame^] | 89 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 90 | |
| 91 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 92 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 |
| 93 | |
| 94 | #define PLAT_ARM_CCI_BASE 0x2a000000 |
| 95 | |
| 96 | /* Cluster to CCI slave mapping */ |
| 97 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 6 |
| 98 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 |
| 99 | |
| 100 | /* System timer related constants */ |
| 101 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 102 | |
| 103 | /* TZC related constants */ |
| 104 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 105 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP) | \ |
| 106 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0) | \ |
| 107 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1) | \ |
| 108 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU) | \ |
| 109 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO) | \ |
| 110 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0) | \ |
| 111 | TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1)) |
| 112 | |
| 113 | /* Display Processor register definitions to setup the NSAIDs */ |
| 114 | #define MALI_DP_BASE 0x2cc00000 |
| 115 | #define DP_NPROT_NSAID_OFFSET 0x1000c |
| 116 | #define W_NPROT_NSAID_SHIFT 24 |
| 117 | #define LS_NPORT_NSAID_SHIFT 12 |
| 118 | |
| 119 | /* |
| 120 | * Base address of the first memory region used for communication between AP |
| 121 | * and SCP. Used by the BootOverMHU and SCPI protocols. |
| 122 | */ |
| 123 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 124 | /* |
| 125 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 126 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 127 | * communication with the SCP. The configuration data is expected to be a |
| 128 | * 32-bit word on all CSS platforms. Part of this configuration is |
| 129 | * which CPU is the primary, according to the shift and mask definitions below. |
| 130 | */ |
| 131 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) |
| 132 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 133 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
| 134 | #endif |
| 135 | |
| 136 | /* |
| 137 | * tspd support is conditional so enable this for CSS sgm platforms. |
| 138 | */ |
| 139 | #define SPD_tspd |
| 140 | |
| 141 | /* |
| 142 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 143 | * SCP_BL2 size plus a little space for growth. |
| 144 | */ |
Dimitris Papastamos | a5d5486 | 2018-09-28 14:23:26 +0100 | [diff] [blame] | 145 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x15000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 146 | |
| 147 | /* |
| 148 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 149 | * SCP_BL2U size plus a little space for growth. |
| 150 | */ |
Dimitris Papastamos | a5d5486 | 2018-09-28 14:23:26 +0100 | [diff] [blame] | 151 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x15000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 152 | |
| 153 | /* |
| 154 | * Most platform porting definitions provided by included headers |
| 155 | */ |
| 156 | |
| 157 | /* |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 158 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 159 | * plat_arm_mmap array defined for each BL stage. |
| 160 | */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 161 | #if defined(IMAGE_BL31) |
| 162 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 163 | # define MAX_XLAT_TABLES 5 |
| 164 | #elif defined(IMAGE_BL32) |
| 165 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 166 | # define MAX_XLAT_TABLES 5 |
| 167 | #elif !USE_ROMLIB |
| 168 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 169 | # define MAX_XLAT_TABLES 5 |
| 170 | #else |
| 171 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 172 | # define MAX_XLAT_TABLES 6 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 173 | #endif |
| 174 | |
| 175 | /* |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 176 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 177 | * plus a little space for growth. |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 178 | */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 179 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 180 | |
| 181 | /* |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 182 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 183 | */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 184 | |
| 185 | #if USE_ROMLIB |
| 186 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 187 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 188 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 189 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 190 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 191 | #endif |
| 192 | |
| 193 | /* |
| 194 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 195 | * little space for growth. |
| 196 | */ |
| 197 | #if TRUSTED_BOARD_BOOT |
| 198 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 199 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 200 | # define PLAT_ARM_MAX_BL2_SIZE 0x11000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 201 | #endif |
| 202 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 203 | /* |
| 204 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 205 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 206 | * BL2 and BL1-RW |
| 207 | */ |
| 208 | #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 209 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 210 | /* |
| 211 | * Size of cacheable stacks |
| 212 | */ |
| 213 | #if defined(IMAGE_BL1) |
| 214 | # if TRUSTED_BOARD_BOOT |
| 215 | # define PLATFORM_STACK_SIZE 0x1000 |
| 216 | # else |
| 217 | # define PLATFORM_STACK_SIZE 0x440 |
| 218 | # endif |
| 219 | #elif defined(IMAGE_BL2) |
| 220 | # if TRUSTED_BOARD_BOOT |
| 221 | # define PLATFORM_STACK_SIZE 0x1000 |
| 222 | # else |
| 223 | # define PLATFORM_STACK_SIZE 0x400 |
| 224 | # endif |
| 225 | #elif defined(IMAGE_BL2U) |
| 226 | # define PLATFORM_STACK_SIZE 0x400 |
| 227 | #elif defined(IMAGE_BL31) |
| 228 | # define PLATFORM_STACK_SIZE 0x400 |
| 229 | #elif defined(IMAGE_BL32) |
| 230 | # define PLATFORM_STACK_SIZE 0x440 |
| 231 | #endif |
| 232 | |
Nariman Poushin | c703f90 | 2018-03-07 10:29:57 +0000 | [diff] [blame] | 233 | /******************************************************************************* |
| 234 | * Memprotect definitions |
| 235 | ******************************************************************************/ |
| 236 | /* PSCI memory protect definitions: |
| 237 | * This variable is stored in a non-secure flash because some ARM reference |
| 238 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 239 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 240 | */ |
| 241 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 242 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 243 | |
| 244 | /* System power domain level */ |
| 245 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 246 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 247 | #endif /* SGM_BASE_PLATFORM_DEF_H */ |