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johpow01a3810e82021-05-18 15:23:31 -05001/*
Bipin Ravi7dccf8f2022-12-22 14:19:59 -06002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
johpow01a3810e82021-05-18 15:23:31 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_x2.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
Bipin Ravi86499742022-01-18 01:59:06 -060013#include "wa_cve_2022_23960_bhb_vector.S"
johpow01a3810e82021-05-18 15:23:31 -050014
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
Bipin Ravi86499742022-01-18 01:59:06 -060025#if WORKAROUND_CVE_2022_23960
26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
27#endif /* WORKAROUND_CVE_2022_23960 */
28
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010029workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
johpow010afef362021-12-02 13:25:50 -060030 ldr x0, =0x6
31 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
32 ldr x0, =0xF3A08002
33 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
34 ldr x0, =0xFFF0F7FE
35 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
36 ldr x0, =0x40000001003ff
37 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010038workaround_reset_end cortex_x2, ERRATUM(2002765)
johpow010afef362021-12-02 13:25:50 -060039
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010040check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
johpow010afef362021-12-02 13:25:50 -060041
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010042workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +010043 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010044workaround_reset_end cortex_x2, ERRATUM(2017096)
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +010045
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010046check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +010047
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010048workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +010049 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
50 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010051workaround_reset_end cortex_x2, ERRATUM(2058056)
johpow01f6c37de2021-12-03 11:27:33 -060052
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010053check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
johpow01f6c37de2021-12-03 11:27:33 -060054
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010055workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
Bipin Ravi9ad54782022-01-20 00:42:05 -060056 /* Apply instruction patching sequence */
57 ldr x0, =0x3
58 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
59 ldr x0, =0xF3A08002
60 msr CORTEX_X2_IMP_CPUPOR_EL3, x0
61 ldr x0, =0xFFF0F7FE
62 msr CORTEX_X2_IMP_CPUPMR_EL3, x0
63 ldr x0, =0x10002001003FF
64 msr CORTEX_X2_IMP_CPUPCR_EL3, x0
65 ldr x0, =0x4
66 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
67 ldr x0, =0xBF200000
68 msr CORTEX_X2_IMP_CPUPOR_EL3, x0
69 ldr x0, =0xFFEF0000
70 msr CORTEX_X2_IMP_CPUPMR_EL3, x0
71 ldr x0, =0x10002001003F3
72 msr CORTEX_X2_IMP_CPUPCR_EL3, x0
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010073workaround_reset_end cortex_x2, ERRATUM(2081180)
Bipin Ravi9ad54782022-01-20 00:42:05 -060074
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010075check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
Bipin Ravi9ad54782022-01-20 00:42:05 -060076
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010077workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +010078 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +010079 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010080workaround_reset_end cortex_x2, ERRATUM(2083908)
Bipin Ravi78b72082022-02-06 01:29:31 -060081
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010082check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
Bipin Ravi78b72082022-02-06 01:29:31 -060083
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010084workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
Bipin Ravic6b65212022-03-08 10:37:43 -060085 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +010086 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010087workaround_reset_end cortex_x2, ERRATUM(2147715)
Bipin Ravic6b65212022-03-08 10:37:43 -060088
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010089check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
Bipin Ravic6b65212022-03-08 10:37:43 -060090
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +010091workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +010092 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +010093
94 /* Apply instruction patching sequence */
95 ldr x0, =0x5
96 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
97 ldr x0, =0x10F600E000
98 msr CORTEX_X2_IMP_CPUPOR_EL3, x0
99 ldr x0, =0x10FF80E000
100 msr CORTEX_X2_IMP_CPUPMR_EL3, x0
101 ldr x0, =0x80000000003FF
102 msr CORTEX_X2_IMP_CPUPCR_EL3, x0
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100103workaround_reset_end cortex_x2, ERRATUM(2216384)
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +0100104
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100105check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +0100106
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100107workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600108 /* Apply the workaround */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +0100109 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100110workaround_reset_end cortex_x2, ERRATUM(2282622)
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600111
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100112check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600113
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100114workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
Bipin Ravi4e315c32022-07-12 17:13:01 -0500115 /* Set bit 40 in CPUACTLR2_EL1 */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +0100116 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100117workaround_reset_end cortex_x2, ERRATUM(2371105)
Bipin Ravi4e315c32022-07-12 17:13:01 -0500118
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100119check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
Bipin Ravi86839eb2022-12-07 13:54:02 -0600120
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100121workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
Bipin Ravi86839eb2022-12-07 13:54:02 -0600122 /* dsb before isb of power down sequence */
123 dsb sy
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100124workaround_reset_end cortex_x2, ERRATUM(2768515)
Bipin Ravi86839eb2022-12-07 13:54:02 -0600125
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100126check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
Bipin Ravi86839eb2022-12-07 13:54:02 -0600127
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100128workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
129#if IMAGE_BL31
130 /*
131 * The Cortex-X2 generic vectors are overridden to apply errata
132 * mitigation on exception entry from lower ELs.
133 */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +0100134 override_vector_table wa_cve_vbar_cortex_x2
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100135#endif /* IMAGE_BL31 */
136workaround_reset_end cortex_x2, CVE(2022, 23960)
137
138check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
139
140/*
141 * ERRATA_DSU_2313941 :
142 * The errata is defined in dsu_helpers.S but applies to cortex_x2
143 * as well. Henceforth creating symbolic names to the already existing errata
144 * workaround functions to get them registered under the Errata Framework.
145 */
146.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941
147.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa
148add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
Jayanth Dodderi Chidanandb1987252023-04-14 10:43:27 +0100149
johpow01a3810e82021-05-18 15:23:31 -0500150 /* ----------------------------------------------------
151 * HW will do the cache maintenance while powering down
152 * ----------------------------------------------------
153 */
154func cortex_x2_core_pwr_dwn
155 /* ---------------------------------------------------
156 * Enable CPU power down bit in power control register
157 * ---------------------------------------------------
158 */
Jayanth Dodderi Chidanand0b327272023-04-14 11:33:48 +0100159 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
160
Bipin Ravi86839eb2022-12-07 13:54:02 -0600161#if ERRATA_X2_2768515
162 mov x15, x30
163 bl cpu_get_rev_var
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100164 bl erratum_cortex_x2_2768515_wa
Bipin Ravi86839eb2022-12-07 13:54:02 -0600165 mov x30, x15
166#endif /* ERRATA_X2_2768515 */
johpow01a3810e82021-05-18 15:23:31 -0500167 isb
168 ret
169endfunc cortex_x2_core_pwr_dwn
170
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100171errata_report_shim cortex_x2
johpow0115f10bd2021-12-01 17:40:39 -0600172
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100173cpu_reset_func_start cortex_x2
johpow01a3810e82021-05-18 15:23:31 -0500174 /* Disable speculative loads */
175 msr SSBS, xzr
Jayanth Dodderi Chidanandac7b1912023-04-14 11:26:16 +0100176cpu_reset_func_end cortex_x2
johpow01a3810e82021-05-18 15:23:31 -0500177
178 /* ---------------------------------------------
179 * This function provides Cortex X2 specific
180 * register information for crash reporting.
181 * It needs to return with x6 pointing to
182 * a list of register names in ascii and
183 * x8 - x15 having values of registers to be
184 * reported.
185 * ---------------------------------------------
186 */
187.section .rodata.cortex_x2_regs, "aS"
188cortex_x2_regs: /* The ascii list of register names to be reported */
189 .asciz "cpuectlr_el1", ""
190
191func cortex_x2_cpu_reg_dump
192 adr x6, cortex_x2_regs
193 mrs x8, CORTEX_X2_CPUECTLR_EL1
194 ret
195endfunc cortex_x2_cpu_reg_dump
196
197declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
198 cortex_x2_reset_func, \
199 cortex_x2_core_pwr_dwn