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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(bl2_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010015 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010016}
17
18
19SECTIONS
20{
21 . = BL2_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000023 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010024
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010025#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
28 *bl2_entrypoint.o(.text*)
29 *(.text*)
30 *(.vectors)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000031 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032 __TEXT_END__ = .;
33 } >RAM
34
35 .rodata . : {
36 __RODATA_START__ = .;
37 *(.rodata*)
38
39 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
40 . = ALIGN(8);
41 __PARSER_LIB_DESCS_START__ = .;
42 KEEP(*(.img_parser_lib_descs))
43 __PARSER_LIB_DESCS_END__ = .;
44
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000045 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010046 __RODATA_END__ = .;
47 } >RAM
48#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049 ro . : {
50 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000051 *bl2_entrypoint.o(.text*)
52 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000053 *(.rodata*)
Juan Castillo8e55d932015-04-02 09:48:16 +010054
55 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
56 . = ALIGN(8);
57 __PARSER_LIB_DESCS_START__ = .;
58 KEEP(*(.img_parser_lib_descs))
59 __PARSER_LIB_DESCS_END__ = .;
60
Achin Guptab739f222014-01-18 16:50:09 +000061 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000062 __RO_END_UNALIGNED__ = .;
63 /*
64 * Memory page(s) mapped to this section will be marked as
65 * read-only, executable. No RW data from the next section must
66 * creep in. Ensure the rest of the current memory page is unused.
67 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000068 . = NEXT(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000069 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010070 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010071#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010072
Achin Guptae9c4a642015-09-11 16:03:13 +010073 /*
74 * Define a linker symbol to mark start of the RW memory area for this
75 * image.
76 */
77 __RW_START__ = . ;
78
Douglas Raillard306593d2017-02-24 18:14:15 +000079 /*
80 * .data must be placed at a lower address than the stacks if the stack
81 * protector is enabled. Alternatively, the .data.stack_protector_canary
82 * section can be placed independently of the main .data section.
83 */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000084 .data . : {
85 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000086 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000087 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010088 } >RAM
89
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000090 stacks (NOLOAD) : {
91 __STACKS_START__ = .;
92 *(tzfw_normal_stacks)
93 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 } >RAM
95
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000096 /*
97 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +000098 * Its base address should be 16-byte aligned for better performance of the
99 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000100 */
101 .bss : ALIGN(16) {
102 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000103 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000105 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 } >RAM
107
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000108 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000109 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000110 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000111 * the .bss section. The tables are initialized to zero by the translation
112 * tables library.
Achin Guptaa0cd9892014-02-09 13:30:38 +0000113 */
114 xlat_table (NOLOAD) : {
115 *(xlat_table)
116 } >RAM
117
Soby Mathew2ae20432015-01-08 18:02:44 +0000118#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000119 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000120 * The base address of the coherent memory section must be page-aligned (4K)
121 * to guarantee that the coherent data are stored on their own pages and
122 * are not mixed with normal data. This is required to set up the correct
123 * memory attributes for the coherent data page tables.
124 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000125 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000126 __COHERENT_RAM_START__ = .;
127 *(tzfw_coherent_mem)
128 __COHERENT_RAM_END_UNALIGNED__ = .;
129 /*
130 * Memory page(s) mapped to this section will be marked
131 * as device memory. No other unexpected data must creep in.
132 * Ensure the rest of the current memory page is unused.
133 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000134 . = NEXT(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000135 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000137#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100138
Achin Guptae9c4a642015-09-11 16:03:13 +0100139 /*
140 * Define a linker symbol to mark end of the RW memory area for this
141 * image.
142 */
143 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000144 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000146 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000147
148#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000149 __COHERENT_RAM_UNALIGNED_SIZE__ =
150 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000151#endif
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100152
153 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154}