Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 1 | /* |
Heyi Guo | 3a579ae | 2020-05-19 11:50:40 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 9 | #include <arch.h> |
| 10 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <common/debug.h> |
| 12 | #include <common/interrupt_props.h> |
| 13 | #include <drivers/arm/gicv3.h> |
| 14 | #include <lib/spinlock.h> |
| 15 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 16 | #include "gicv3_private.h" |
| 17 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 18 | const gicv3_driver_data_t *gicv3_driver_data; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 19 | |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 20 | /* |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 21 | * Spinlock to guard registers needing read-modify-write. APIs protected by this |
| 22 | * spinlock are used either at boot time (when only a single CPU is active), or |
| 23 | * when the system is fully coherent. |
| 24 | */ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 25 | static spinlock_t gic_lock; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 26 | |
| 27 | /* |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 28 | * Redistributor power operations are weakly bound so that they can be |
| 29 | * overridden |
| 30 | */ |
| 31 | #pragma weak gicv3_rdistif_off |
| 32 | #pragma weak gicv3_rdistif_on |
| 33 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 34 | /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ |
| 35 | static bool is_sgi_ppi(unsigned int id); |
| 36 | |
| 37 | /* |
| 38 | * Helper macros to save and restore GICR and GICD registers |
| 39 | * corresponding to their numbers to and from the context |
| 40 | */ |
| 41 | #define RESTORE_GICR_REG(base, ctx, name, i) \ |
| 42 | gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) |
| 43 | |
| 44 | #define SAVE_GICR_REG(base, ctx, name, i) \ |
| 45 | (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 46 | |
| 47 | /* Helper macros to save and restore GICD registers to and from the context */ |
| 48 | #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ |
| 49 | do { \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 50 | for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ |
| 51 | int_id += (1U << REG##R_SHIFT)) { \ |
| 52 | gicd_write_##reg((base), int_id, \ |
| 53 | (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ |
| 54 | REG##R_SHIFT]); \ |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 55 | } \ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 56 | } while (false) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 57 | |
| 58 | #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ |
| 59 | do { \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 60 | for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ |
| 61 | int_id += (1U << REG##R_SHIFT)) { \ |
| 62 | (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ |
| 63 | REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ |
| 64 | } \ |
| 65 | } while (false) |
| 66 | |
| 67 | #if GIC_EXT_INTID |
| 68 | #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ |
| 69 | do { \ |
| 70 | for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ |
| 71 | int_id += (1U << REG##R_SHIFT)) { \ |
| 72 | gicd_write_##reg((base), int_id, \ |
Heyi Guo | efa2107 | 2021-01-14 22:16:18 +0800 | [diff] [blame] | 73 | (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ |
| 74 | round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 75 | >> REG##R_SHIFT]); \ |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 76 | } \ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 77 | } while (false) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 78 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 79 | #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ |
| 80 | do { \ |
| 81 | for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ |
| 82 | int_id += (1U << REG##R_SHIFT)) { \ |
Heyi Guo | efa2107 | 2021-01-14 22:16:18 +0800 | [diff] [blame] | 83 | (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ |
| 84 | round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 85 | >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ |
| 86 | } \ |
| 87 | } while (false) |
| 88 | #else |
| 89 | #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) |
| 90 | #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) |
| 91 | #endif /* GIC_EXT_INTID */ |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 92 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 93 | /******************************************************************************* |
| 94 | * This function initialises the ARM GICv3 driver in EL3 with provided platform |
| 95 | * inputs. |
| 96 | ******************************************************************************/ |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 97 | void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 98 | { |
| 99 | unsigned int gic_version; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 100 | unsigned int gicv2_compat; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 101 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 102 | assert(plat_driver_data != NULL); |
| 103 | assert(plat_driver_data->gicd_base != 0U); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 104 | assert(plat_driver_data->rdistif_num != 0U); |
| 105 | assert(plat_driver_data->rdistif_base_addrs != NULL); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 106 | |
| 107 | assert(IS_IN_EL3()); |
| 108 | |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 109 | assert((plat_driver_data->interrupt_props_num != 0U) ? |
| 110 | (plat_driver_data->interrupt_props != NULL) : 1); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 111 | |
| 112 | /* Check for system register support */ |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 113 | #ifndef __aarch64__ |
| 114 | assert((read_id_pfr1() & |
| 115 | (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); |
| 116 | #else |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 117 | assert((read_id_aa64pfr0_el1() & |
| 118 | (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 119 | #endif /* !__aarch64__ */ |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 120 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 121 | gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 122 | gic_version >>= PIDR2_ARCH_REV_SHIFT; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 123 | gic_version &= PIDR2_ARCH_REV_MASK; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 124 | |
Alexei Fedorov | 1970593 | 2020-04-06 19:00:35 +0100 | [diff] [blame] | 125 | /* Check GIC version */ |
| 126 | #if GIC_ENABLE_V4_EXTN |
| 127 | assert(gic_version == ARCH_REV_GICV4); |
| 128 | |
| 129 | /* GICv4 supports Direct Virtual LPI injection */ |
| 130 | assert((gicd_read_typer(plat_driver_data->gicd_base) |
| 131 | & TYPER_DVIS) != 0); |
| 132 | #else |
| 133 | assert(gic_version == ARCH_REV_GICV3); |
| 134 | #endif |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 135 | /* |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 136 | * Find out whether the GIC supports the GICv2 compatibility mode. |
| 137 | * The ARE_S bit resets to 0 if supported |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 138 | */ |
| 139 | gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); |
| 140 | gicv2_compat >>= CTLR_ARE_S_SHIFT; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 141 | gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 142 | |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 143 | if (plat_driver_data->gicr_base != 0U) { |
| 144 | /* |
| 145 | * Find the base address of each implemented Redistributor interface. |
| 146 | * The number of interfaces should be equal to the number of CPUs in the |
| 147 | * system. The memory for saving these addresses has to be allocated by |
| 148 | * the platform port |
| 149 | */ |
| 150 | gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, |
| 151 | plat_driver_data->rdistif_num, |
| 152 | plat_driver_data->gicr_base, |
| 153 | plat_driver_data->mpidr_to_core_pos); |
| 154 | #if !HW_ASSISTED_COHERENCY |
| 155 | /* |
| 156 | * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. |
| 157 | */ |
| 158 | flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), |
| 159 | plat_driver_data->rdistif_num * |
| 160 | sizeof(*(plat_driver_data->rdistif_base_addrs))); |
| 161 | #endif |
| 162 | } |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 163 | gicv3_driver_data = plat_driver_data; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 164 | |
Soby Mathew | 7264513 | 2017-02-14 10:11:52 +0000 | [diff] [blame] | 165 | /* |
| 166 | * The GIC driver data is initialized by the primary CPU with caches |
| 167 | * enabled. When the secondary CPU boots up, it initializes the |
| 168 | * GICC/GICR interface with the caches disabled. Hence flush the |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 169 | * driver data to ensure coherency. This is not required if the |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 170 | * platform has HW_ASSISTED_COHERENCY enabled. |
Soby Mathew | 7264513 | 2017-02-14 10:11:52 +0000 | [diff] [blame] | 171 | */ |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 172 | #if !HW_ASSISTED_COHERENCY |
| 173 | flush_dcache_range((uintptr_t)&gicv3_driver_data, |
| 174 | sizeof(gicv3_driver_data)); |
| 175 | flush_dcache_range((uintptr_t)gicv3_driver_data, |
| 176 | sizeof(*gicv3_driver_data)); |
Soby Mathew | 7264513 | 2017-02-14 10:11:52 +0000 | [diff] [blame] | 177 | #endif |
Alexei Fedorov | 1970593 | 2020-04-06 19:00:35 +0100 | [diff] [blame] | 178 | INFO("GICv%u with%s legacy support detected.\n", gic_version, |
| 179 | (gicv2_compat == 0U) ? "" : "out"); |
| 180 | INFO("ARM GICv%u driver initialized in EL3\n", gic_version); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | /******************************************************************************* |
| 184 | * This function initialises the GIC distributor interface based upon the data |
| 185 | * provided by the platform while initialising the driver. |
| 186 | ******************************************************************************/ |
Daniel Boulby | 844b487 | 2018-09-18 13:36:39 +0100 | [diff] [blame] | 187 | void __init gicv3_distif_init(void) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 188 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 189 | unsigned int bitmap; |
Yatharth Kochar | 3f00a89 | 2016-09-06 11:48:05 +0100 | [diff] [blame] | 190 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 191 | assert(gicv3_driver_data != NULL); |
| 192 | assert(gicv3_driver_data->gicd_base != 0U); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 193 | |
| 194 | assert(IS_IN_EL3()); |
| 195 | |
| 196 | /* |
| 197 | * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring |
| 198 | * the ARE_S bit. The Distributor might generate a system error |
| 199 | * otherwise. |
| 200 | */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 201 | gicd_clr_ctlr(gicv3_driver_data->gicd_base, |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 202 | CTLR_ENABLE_G0_BIT | |
| 203 | CTLR_ENABLE_G1S_BIT | |
| 204 | CTLR_ENABLE_G1NS_BIT, |
| 205 | RWP_TRUE); |
| 206 | |
| 207 | /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 208 | gicd_set_ctlr(gicv3_driver_data->gicd_base, |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 209 | CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); |
| 210 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 211 | /* Set the default attribute of all (E)SPIs */ |
Daniel Boulby | 4e83abb | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 212 | gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 213 | |
Antonio Nino Diaz | 29b9f5b | 2018-09-24 17:23:24 +0100 | [diff] [blame] | 214 | bitmap = gicv3_secure_spis_config_props( |
| 215 | gicv3_driver_data->gicd_base, |
| 216 | gicv3_driver_data->interrupt_props, |
| 217 | gicv3_driver_data->interrupt_props_num); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 218 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 219 | /* Enable the secure (E)SPIs now that they have been configured */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 220 | gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | /******************************************************************************* |
| 224 | * This function initialises the GIC Redistributor interface of the calling CPU |
| 225 | * (identified by the 'proc_num' parameter) based upon the data provided by the |
| 226 | * platform while initialising the driver. |
| 227 | ******************************************************************************/ |
| 228 | void gicv3_rdistif_init(unsigned int proc_num) |
| 229 | { |
| 230 | uintptr_t gicr_base; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 231 | unsigned int bitmap; |
Jeenu Viswambharan | 88d8f45 | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 232 | uint32_t ctlr; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 233 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 234 | assert(gicv3_driver_data != NULL); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 235 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 236 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
| 237 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | 88d8f45 | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 238 | |
| 239 | ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 240 | assert((ctlr & CTLR_ARE_S_BIT) != 0U); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 241 | |
| 242 | assert(IS_IN_EL3()); |
| 243 | |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 244 | /* Power on redistributor */ |
| 245 | gicv3_rdistif_on(proc_num); |
| 246 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 247 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 248 | assert(gicr_base != 0U); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 249 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 250 | /* Set the default attribute of all SGIs and (E)PPIs */ |
Daniel Boulby | 4e83abb | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 251 | gicv3_ppi_sgi_config_defaults(gicr_base); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 252 | |
Antonio Nino Diaz | 29b9f5b | 2018-09-24 17:23:24 +0100 | [diff] [blame] | 253 | bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, |
| 254 | gicv3_driver_data->interrupt_props, |
| 255 | gicv3_driver_data->interrupt_props_num); |
Jeenu Viswambharan | 88d8f45 | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 256 | |
| 257 | /* Enable interrupt groups as required, if not already */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 258 | if ((ctlr & bitmap) != bitmap) { |
Jeenu Viswambharan | 88d8f45 | 2017-11-07 08:38:23 +0000 | [diff] [blame] | 259 | gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 260 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | /******************************************************************************* |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 264 | * Functions to perform power operations on GIC Redistributor |
| 265 | ******************************************************************************/ |
| 266 | void gicv3_rdistif_off(unsigned int proc_num) |
| 267 | { |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | void gicv3_rdistif_on(unsigned int proc_num) |
| 271 | { |
Jeenu Viswambharan | 76647d5 | 2016-12-09 11:03:15 +0000 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | /******************************************************************************* |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 275 | * This function enables the GIC CPU interface of the calling CPU using only |
| 276 | * system register accesses. |
| 277 | ******************************************************************************/ |
| 278 | void gicv3_cpuif_enable(unsigned int proc_num) |
| 279 | { |
| 280 | uintptr_t gicr_base; |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 281 | u_register_t scr_el3; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 282 | unsigned int icc_sre_el3; |
| 283 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 284 | assert(gicv3_driver_data != NULL); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 285 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 286 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 287 | assert(IS_IN_EL3()); |
| 288 | |
| 289 | /* Mark the connected core as awake */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 290 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 291 | gicv3_rdistif_mark_core_awake(gicr_base); |
| 292 | |
| 293 | /* Disable the legacy interrupt bypass */ |
| 294 | icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; |
| 295 | |
| 296 | /* |
| 297 | * Enable system register access for EL3 and allow lower exception |
| 298 | * levels to configure the same for themselves. If the legacy mode is |
| 299 | * not supported, the SRE bit is RAO/WI |
| 300 | */ |
| 301 | icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); |
| 302 | write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); |
| 303 | |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 304 | scr_el3 = read_scr_el3(); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 305 | |
| 306 | /* |
| 307 | * Switch to NS state to write Non secure ICC_SRE_EL1 and |
| 308 | * ICC_SRE_EL2 registers. |
| 309 | */ |
| 310 | write_scr_el3(scr_el3 | SCR_NS_BIT); |
| 311 | isb(); |
| 312 | |
| 313 | write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); |
| 314 | write_icc_sre_el1(ICC_SRE_SRE_BIT); |
| 315 | isb(); |
| 316 | |
| 317 | /* Switch to secure state. */ |
| 318 | write_scr_el3(scr_el3 & (~SCR_NS_BIT)); |
| 319 | isb(); |
| 320 | |
James kung | 05403eb | 2019-05-31 15:40:05 +0800 | [diff] [blame] | 321 | /* Write the secure ICC_SRE_EL1 register */ |
| 322 | write_icc_sre_el1(ICC_SRE_SRE_BIT); |
| 323 | isb(); |
| 324 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 325 | /* Program the idle priority in the PMR */ |
| 326 | write_icc_pmr_el1(GIC_PRI_MASK); |
| 327 | |
| 328 | /* Enable Group0 interrupts */ |
| 329 | write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); |
| 330 | |
| 331 | /* Enable Group1 Secure interrupts */ |
| 332 | write_icc_igrpen1_el3(read_icc_igrpen1_el3() | |
| 333 | IGRPEN1_EL3_ENABLE_G1S_BIT); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 334 | isb(); |
Ming Huang | 94e1976 | 2021-06-04 16:23:22 +0800 | [diff] [blame] | 335 | /* Add DSB to ensure visibility of System register writes */ |
| 336 | dsb(); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | /******************************************************************************* |
| 340 | * This function disables the GIC CPU interface of the calling CPU using |
| 341 | * only system register accesses. |
| 342 | ******************************************************************************/ |
| 343 | void gicv3_cpuif_disable(unsigned int proc_num) |
| 344 | { |
| 345 | uintptr_t gicr_base; |
| 346 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 347 | assert(gicv3_driver_data != NULL); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 348 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 349 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 350 | |
| 351 | assert(IS_IN_EL3()); |
| 352 | |
| 353 | /* Disable legacy interrupt bypass */ |
| 354 | write_icc_sre_el3(read_icc_sre_el3() | |
| 355 | (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); |
| 356 | |
| 357 | /* Disable Group0 interrupts */ |
| 358 | write_icc_igrpen0_el1(read_icc_igrpen0_el1() & |
| 359 | ~IGRPEN1_EL1_ENABLE_G0_BIT); |
| 360 | |
Sudeep Holla | 869e3db | 2016-08-04 16:14:50 +0100 | [diff] [blame] | 361 | /* Disable Group1 Secure and Non-Secure interrupts */ |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 362 | write_icc_igrpen1_el3(read_icc_igrpen1_el3() & |
Sudeep Holla | 869e3db | 2016-08-04 16:14:50 +0100 | [diff] [blame] | 363 | ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | |
| 364 | IGRPEN1_EL3_ENABLE_G1S_BIT)); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 365 | |
| 366 | /* Synchronise accesses to group enable registers */ |
| 367 | isb(); |
Ming Huang | 94e1976 | 2021-06-04 16:23:22 +0800 | [diff] [blame] | 368 | /* Add DSB to ensure visibility of System register writes */ |
| 369 | dsb(); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 370 | |
| 371 | /* Mark the connected core as asleep */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 372 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 373 | assert(gicr_base != 0U); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 374 | gicv3_rdistif_mark_core_asleep(gicr_base); |
| 375 | } |
| 376 | |
| 377 | /******************************************************************************* |
| 378 | * This function returns the id of the highest priority pending interrupt at |
| 379 | * the GIC cpu interface. |
| 380 | ******************************************************************************/ |
| 381 | unsigned int gicv3_get_pending_interrupt_id(void) |
| 382 | { |
| 383 | unsigned int id; |
| 384 | |
| 385 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 386 | id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 387 | |
| 388 | /* |
| 389 | * If the ID is special identifier corresponding to G1S or G1NS |
| 390 | * interrupt, then read the highest pending group 1 interrupt. |
| 391 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 392 | if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 393 | return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 394 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 395 | |
| 396 | return id; |
| 397 | } |
| 398 | |
| 399 | /******************************************************************************* |
| 400 | * This function returns the type of the highest priority pending interrupt at |
| 401 | * the GIC cpu interface. The return values can be one of the following : |
| 402 | * PENDING_G1S_INTID : The interrupt type is secure Group 1. |
| 403 | * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. |
| 404 | * 0 - 1019 : The interrupt type is secure Group 0. |
| 405 | * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with |
| 406 | * sufficient priority to be signaled |
| 407 | ******************************************************************************/ |
| 408 | unsigned int gicv3_get_pending_interrupt_type(void) |
| 409 | { |
| 410 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 411 | return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | /******************************************************************************* |
| 415 | * This function returns the type of the interrupt id depending upon the group |
| 416 | * this interrupt has been configured under by the interrupt controller i.e. |
| 417 | * group0 or group1 Secure / Non Secure. The return value can be one of the |
| 418 | * following : |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 419 | * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt |
| 420 | * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt |
| 421 | * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 422 | * interrupt. |
| 423 | ******************************************************************************/ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 424 | unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 425 | { |
| 426 | unsigned int igroup, grpmodr; |
| 427 | uintptr_t gicr_base; |
| 428 | |
| 429 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 430 | assert(gicv3_driver_data != NULL); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 431 | |
| 432 | /* Ensure the parameters are valid */ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 433 | assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 434 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 435 | |
| 436 | /* All LPI interrupts are Group 1 non secure */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 437 | if (id >= MIN_LPI_ID) { |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 438 | return INTR_GROUP1NS; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 439 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 440 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 441 | /* Check interrupt ID */ |
| 442 | if (is_sgi_ppi(id)) { |
| 443 | /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ |
Andrew F. Davis | 25a17a2 | 2018-08-30 14:30:54 -0500 | [diff] [blame] | 444 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 445 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 446 | igroup = gicr_get_igroupr(gicr_base, id); |
| 447 | grpmodr = gicr_get_igrpmodr(gicr_base, id); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 448 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 449 | /* SPIs: 32-1019, ESPIs: 4096-5119 */ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 450 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 451 | igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); |
| 452 | grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | /* |
| 456 | * If the IGROUP bit is set, then it is a Group 1 Non secure |
| 457 | * interrupt |
| 458 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 459 | if (igroup != 0U) { |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 460 | return INTR_GROUP1NS; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 461 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 462 | |
| 463 | /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 464 | if (grpmodr != 0U) { |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 465 | return INTR_GROUP1S; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 466 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 467 | |
| 468 | /* Else it is a Group 0 Secure interrupt */ |
Soby Mathew | 5c5c36b | 2015-12-03 14:12:54 +0000 | [diff] [blame] | 469 | return INTR_GROUP0; |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 470 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 471 | |
| 472 | /***************************************************************************** |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 473 | * Function to save and disable the GIC ITS register context. The power |
| 474 | * management of GIC ITS is implementation-defined and this function doesn't |
| 475 | * save any memory structures required to support ITS. As the sequence to save |
| 476 | * this state is implementation defined, it should be executed in platform |
| 477 | * specific code. Calling this function alone and then powering down the GIC and |
| 478 | * ITS without implementing the aforementioned platform specific code will |
| 479 | * corrupt the ITS state. |
| 480 | * |
| 481 | * This function must be invoked after the GIC CPU interface is disabled. |
| 482 | *****************************************************************************/ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 483 | void gicv3_its_save_disable(uintptr_t gits_base, |
| 484 | gicv3_its_ctx_t * const its_ctx) |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 485 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 486 | unsigned int i; |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 487 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 488 | assert(gicv3_driver_data != NULL); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 489 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 490 | assert(its_ctx != NULL); |
| 491 | assert(gits_base != 0U); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 492 | |
| 493 | its_ctx->gits_ctlr = gits_read_ctlr(gits_base); |
| 494 | |
| 495 | /* Disable the ITS */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 496 | gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 497 | |
| 498 | /* Wait for quiescent state */ |
| 499 | gits_wait_for_quiescent_bit(gits_base); |
| 500 | |
| 501 | its_ctx->gits_cbaser = gits_read_cbaser(gits_base); |
| 502 | its_ctx->gits_cwriter = gits_read_cwriter(gits_base); |
| 503 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 504 | for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 505 | its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 506 | } |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | /***************************************************************************** |
| 510 | * Function to restore the GIC ITS register context. The power |
| 511 | * management of GIC ITS is implementation defined and this function doesn't |
| 512 | * restore any memory structures required to support ITS. The assumption is |
| 513 | * that these structures are in memory and are retained during system suspend. |
| 514 | * |
| 515 | * This must be invoked before the GIC CPU interface is enabled. |
| 516 | *****************************************************************************/ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 517 | void gicv3_its_restore(uintptr_t gits_base, |
| 518 | const gicv3_its_ctx_t * const its_ctx) |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 519 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 520 | unsigned int i; |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 521 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 522 | assert(gicv3_driver_data != NULL); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 523 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 524 | assert(its_ctx != NULL); |
| 525 | assert(gits_base != 0U); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 526 | |
| 527 | /* Assert that the GITS is disabled and quiescent */ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 528 | assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); |
| 529 | assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 530 | |
| 531 | gits_write_cbaser(gits_base, its_ctx->gits_cbaser); |
| 532 | gits_write_cwriter(gits_base, its_ctx->gits_cwriter); |
| 533 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 534 | for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 535 | gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 536 | } |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 537 | |
| 538 | /* Restore the ITS CTLR but leave the ITS disabled */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 539 | gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | /***************************************************************************** |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 543 | * Function to save the GIC Redistributor register context. This function |
| 544 | * must be invoked after CPU interface disable and prior to Distributor save. |
| 545 | *****************************************************************************/ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 546 | void gicv3_rdistif_save(unsigned int proc_num, |
| 547 | gicv3_redist_ctx_t * const rdist_ctx) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 548 | { |
| 549 | uintptr_t gicr_base; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 550 | unsigned int i, ppi_regs_num, regs_num; |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 551 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 552 | assert(gicv3_driver_data != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 553 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 554 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 555 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 556 | assert(rdist_ctx != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 557 | |
| 558 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
| 559 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 560 | #if GIC_EXT_INTID |
| 561 | /* Calculate number of PPI registers */ |
| 562 | ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> |
| 563 | TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; |
| 564 | /* All other values except PPInum [0-2] are reserved */ |
| 565 | if (ppi_regs_num > 3U) { |
| 566 | ppi_regs_num = 1U; |
| 567 | } |
| 568 | #else |
| 569 | ppi_regs_num = 1U; |
| 570 | #endif |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 571 | /* |
| 572 | * Wait for any write to GICR_CTLR to complete before trying to save any |
| 573 | * state. |
| 574 | */ |
| 575 | gicr_wait_for_pending_write(gicr_base); |
| 576 | |
| 577 | rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); |
| 578 | |
| 579 | rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); |
| 580 | rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); |
| 581 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 582 | /* 32 interrupt IDs per register */ |
| 583 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 584 | SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); |
| 585 | SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); |
| 586 | SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); |
| 587 | SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); |
| 588 | SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 589 | } |
| 590 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 591 | /* 16 interrupt IDs per GICR_ICFGR register */ |
| 592 | regs_num = ppi_regs_num << 1; |
| 593 | for (i = 0U; i < regs_num; ++i) { |
| 594 | SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); |
| 595 | } |
| 596 | |
| 597 | rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); |
| 598 | |
| 599 | /* 4 interrupt IDs per GICR_IPRIORITYR register */ |
| 600 | regs_num = ppi_regs_num << 3; |
| 601 | for (i = 0U; i < regs_num; ++i) { |
Alexei Fedorov | c7510c5 | 2020-04-07 18:16:18 +0100 | [diff] [blame] | 602 | rdist_ctx->gicr_ipriorityr[i] = |
| 603 | gicr_ipriorityr_read(gicr_base, i); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 604 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 605 | |
| 606 | /* |
| 607 | * Call the pre-save hook that implements the IMP DEF sequence that may |
| 608 | * be required on some GIC implementations. As this may need to access |
| 609 | * the Redistributor registers, we pass it proc_num. |
| 610 | */ |
| 611 | gicv3_distif_pre_save(proc_num); |
| 612 | } |
| 613 | |
| 614 | /***************************************************************************** |
| 615 | * Function to restore the GIC Redistributor register context. We disable |
| 616 | * LPI and per-cpu interrupts before we start restore of the Redistributor. |
| 617 | * This function must be invoked after Distributor restore but prior to |
| 618 | * CPU interface enable. The pending and active interrupts are restored |
| 619 | * after the interrupts are fully configured and enabled. |
| 620 | *****************************************************************************/ |
| 621 | void gicv3_rdistif_init_restore(unsigned int proc_num, |
| 622 | const gicv3_redist_ctx_t * const rdist_ctx) |
| 623 | { |
| 624 | uintptr_t gicr_base; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 625 | unsigned int i, ppi_regs_num, regs_num; |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 626 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 627 | assert(gicv3_driver_data != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 628 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 629 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 630 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 631 | assert(rdist_ctx != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 632 | |
| 633 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
| 634 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 635 | #if GIC_EXT_INTID |
| 636 | /* Calculate number of PPI registers */ |
| 637 | ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> |
| 638 | TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; |
| 639 | /* All other values except PPInum [0-2] are reserved */ |
| 640 | if (ppi_regs_num > 3U) { |
| 641 | ppi_regs_num = 1U; |
| 642 | } |
| 643 | #else |
| 644 | ppi_regs_num = 1U; |
| 645 | #endif |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 646 | /* Power on redistributor */ |
| 647 | gicv3_rdistif_on(proc_num); |
| 648 | |
| 649 | /* |
| 650 | * Call the post-restore hook that implements the IMP DEF sequence that |
| 651 | * may be required on some GIC implementations. As this may need to |
| 652 | * access the Redistributor registers, we pass it proc_num. |
| 653 | */ |
| 654 | gicv3_distif_post_restore(proc_num); |
| 655 | |
| 656 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 657 | * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. |
| 658 | * This is a more scalable approach as it avoids clearing the enable |
| 659 | * bits in the GICD_CTLR. |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 660 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 661 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 662 | gicr_write_icenabler(gicr_base, i, ~0U); |
| 663 | } |
| 664 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 665 | /* Wait for pending writes to GICR_ICENABLER */ |
| 666 | gicr_wait_for_pending_write(gicr_base); |
| 667 | |
| 668 | /* |
| 669 | * Disable the LPIs to avoid unpredictable behavior when writing to |
| 670 | * GICR_PROPBASER and GICR_PENDBASER. |
| 671 | */ |
| 672 | gicr_write_ctlr(gicr_base, |
| 673 | rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); |
| 674 | |
| 675 | /* Restore registers' content */ |
| 676 | gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); |
| 677 | gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); |
| 678 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 679 | /* 32 interrupt IDs per register */ |
| 680 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 681 | RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); |
| 682 | RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); |
| 683 | } |
| 684 | |
| 685 | /* 4 interrupt IDs per GICR_IPRIORITYR register */ |
| 686 | regs_num = ppi_regs_num << 3; |
| 687 | for (i = 0U; i < regs_num; ++i) { |
Alexei Fedorov | c7510c5 | 2020-04-07 18:16:18 +0100 | [diff] [blame] | 688 | gicr_ipriorityr_write(gicr_base, i, |
| 689 | rdist_ctx->gicr_ipriorityr[i]); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 690 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 691 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 692 | /* 16 interrupt IDs per GICR_ICFGR register */ |
| 693 | regs_num = ppi_regs_num << 1; |
| 694 | for (i = 0U; i < regs_num; ++i) { |
| 695 | RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 696 | } |
| 697 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 698 | gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); |
| 699 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 700 | /* Restore after group and priorities are set. |
| 701 | * 32 interrupt IDs per register |
| 702 | */ |
| 703 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 704 | RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); |
| 705 | RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); |
| 706 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 707 | |
| 708 | /* |
| 709 | * Wait for all writes to the Distributor to complete before enabling |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 710 | * the SGI and (E)PPIs. |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 711 | */ |
| 712 | gicr_wait_for_upstream_pending_write(gicr_base); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 713 | |
| 714 | /* 32 interrupt IDs per GICR_ISENABLER register */ |
| 715 | for (i = 0U; i < ppi_regs_num; ++i) { |
| 716 | RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); |
| 717 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 718 | |
| 719 | /* |
| 720 | * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case |
| 721 | * the first write to GICR_CTLR was still in flight (this write only |
| 722 | * restores GICR_CTLR.Enable_LPIs and no waiting is required for this |
| 723 | * bit). |
| 724 | */ |
| 725 | gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); |
| 726 | gicr_wait_for_pending_write(gicr_base); |
| 727 | } |
| 728 | |
| 729 | /***************************************************************************** |
| 730 | * Function to save the GIC Distributor register context. This function |
| 731 | * must be invoked after CPU interface disable and Redistributor save. |
| 732 | *****************************************************************************/ |
| 733 | void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) |
| 734 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 735 | assert(gicv3_driver_data != NULL); |
| 736 | assert(gicv3_driver_data->gicd_base != 0U); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 737 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 738 | assert(dist_ctx != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 739 | |
| 740 | uintptr_t gicd_base = gicv3_driver_data->gicd_base; |
Heyi Guo | 79bc7a7 | 2021-01-20 19:05:51 +0800 | [diff] [blame] | 741 | unsigned int num_ints = gicv3_get_spi_limit(gicd_base); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 742 | #if GIC_EXT_INTID |
Heyi Guo | 79bc7a7 | 2021-01-20 19:05:51 +0800 | [diff] [blame] | 743 | unsigned int num_eints = gicv3_get_espi_limit(gicd_base); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 744 | #endif |
Heyi Guo | 79bc7a7 | 2021-01-20 19:05:51 +0800 | [diff] [blame] | 745 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 746 | /* Wait for pending write to complete */ |
| 747 | gicd_wait_for_pending_write(gicd_base); |
| 748 | |
| 749 | /* Save the GICD_CTLR */ |
| 750 | dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); |
| 751 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 752 | /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 753 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); |
| 754 | |
| 755 | /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ |
| 756 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 757 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 758 | /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 759 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); |
| 760 | |
| 761 | /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ |
| 762 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 763 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 764 | /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 765 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); |
| 766 | |
| 767 | /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ |
| 768 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 769 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 770 | /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 771 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); |
| 772 | |
| 773 | /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ |
| 774 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 775 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 776 | /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 777 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); |
| 778 | |
| 779 | /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ |
| 780 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 781 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 782 | /* Save GICD_ICFGR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 783 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); |
| 784 | |
| 785 | /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ |
| 786 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 787 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 788 | /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 789 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); |
| 790 | |
| 791 | /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ |
| 792 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 793 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 794 | /* Save GICD_NSACR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 795 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); |
| 796 | |
| 797 | /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ |
| 798 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 799 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 800 | /* Save GICD_IROUTER for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 801 | SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); |
| 802 | |
| 803 | /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ |
| 804 | SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 805 | |
| 806 | /* |
| 807 | * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when |
| 808 | * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 |
| 809 | * driver. |
| 810 | */ |
| 811 | } |
| 812 | |
| 813 | /***************************************************************************** |
| 814 | * Function to restore the GIC Distributor register context. We disable G0, G1S |
| 815 | * and G1NS interrupt groups before we start restore of the Distributor. This |
| 816 | * function must be invoked prior to Redistributor restore and CPU interface |
| 817 | * enable. The pending and active interrupts are restored after the interrupts |
| 818 | * are fully configured and enabled. |
| 819 | *****************************************************************************/ |
| 820 | void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) |
| 821 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 822 | assert(gicv3_driver_data != NULL); |
| 823 | assert(gicv3_driver_data->gicd_base != 0U); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 824 | assert(IS_IN_EL3()); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 825 | assert(dist_ctx != NULL); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 826 | |
| 827 | uintptr_t gicd_base = gicv3_driver_data->gicd_base; |
| 828 | |
| 829 | /* |
| 830 | * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring |
| 831 | * the ARE_S bit. The Distributor might generate a system error |
| 832 | * otherwise. |
| 833 | */ |
| 834 | gicd_clr_ctlr(gicd_base, |
| 835 | CTLR_ENABLE_G0_BIT | |
| 836 | CTLR_ENABLE_G1S_BIT | |
| 837 | CTLR_ENABLE_G1NS_BIT, |
| 838 | RWP_TRUE); |
| 839 | |
| 840 | /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ |
| 841 | gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); |
| 842 | |
Heyi Guo | 79bc7a7 | 2021-01-20 19:05:51 +0800 | [diff] [blame] | 843 | unsigned int num_ints = gicv3_get_spi_limit(gicd_base); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 844 | #if GIC_EXT_INTID |
Heyi Guo | 79bc7a7 | 2021-01-20 19:05:51 +0800 | [diff] [blame] | 845 | unsigned int num_eints = gicv3_get_espi_limit(gicd_base); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 846 | #endif |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 847 | /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 848 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); |
| 849 | |
| 850 | /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ |
| 851 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 852 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 853 | /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 854 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); |
| 855 | |
| 856 | /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ |
| 857 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 858 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 859 | /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 860 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); |
| 861 | |
| 862 | /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ |
| 863 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 864 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 865 | /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 866 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); |
| 867 | |
| 868 | /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ |
| 869 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 870 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 871 | /* Restore GICD_NSACR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 872 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); |
| 873 | |
| 874 | /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ |
| 875 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 876 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 877 | /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 878 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); |
| 879 | |
| 880 | /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ |
| 881 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 882 | |
| 883 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 884 | * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after |
| 885 | * the interrupts are configured. |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 886 | */ |
| 887 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 888 | /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 889 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); |
| 890 | |
| 891 | /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ |
| 892 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 893 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 894 | /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 895 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); |
| 896 | |
| 897 | /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ |
| 898 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 899 | |
Alexei Fedorov | 68f2688 | 2019-09-13 15:47:13 +0100 | [diff] [blame] | 900 | /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 901 | RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); |
| 902 | |
| 903 | /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ |
| 904 | RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 905 | |
| 906 | /* Restore the GICD_CTLR */ |
| 907 | gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); |
| 908 | gicd_wait_for_pending_write(gicd_base); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 909 | } |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 910 | |
| 911 | /******************************************************************************* |
| 912 | * This function gets the priority of the interrupt the processor is currently |
| 913 | * servicing. |
| 914 | ******************************************************************************/ |
| 915 | unsigned int gicv3_get_running_priority(void) |
| 916 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 917 | return (unsigned int)read_icc_rpr_el1(); |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 918 | } |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 919 | |
| 920 | /******************************************************************************* |
| 921 | * This function checks if the interrupt identified by id is active (whether the |
| 922 | * state is either active, or active and pending). The proc_num is used if the |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 923 | * interrupt is SGI or (E)PPI and programs the corresponding Redistributor |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 924 | * interface. |
| 925 | ******************************************************************************/ |
| 926 | unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) |
| 927 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 928 | assert(gicv3_driver_data != NULL); |
| 929 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 930 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 931 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 932 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 933 | /* Check interrupt ID */ |
| 934 | if (is_sgi_ppi(id)) { |
| 935 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
| 936 | return gicr_get_isactiver( |
| 937 | gicv3_driver_data->rdistif_base_addrs[proc_num], id); |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 938 | } |
| 939 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 940 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
| 941 | return gicd_get_isactiver(gicv3_driver_data->gicd_base, id); |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 942 | } |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 943 | |
| 944 | /******************************************************************************* |
| 945 | * This function enables the interrupt identified by id. The proc_num |
| 946 | * is used if the interrupt is SGI or PPI, and programs the corresponding |
| 947 | * Redistributor interface. |
| 948 | ******************************************************************************/ |
| 949 | void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) |
| 950 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 951 | assert(gicv3_driver_data != NULL); |
| 952 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 953 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 954 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 955 | |
| 956 | /* |
| 957 | * Ensure that any shared variable updates depending on out of band |
| 958 | * interrupt trigger are observed before enabling interrupt. |
| 959 | */ |
| 960 | dsbishst(); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 961 | |
| 962 | /* Check interrupt ID */ |
| 963 | if (is_sgi_ppi(id)) { |
| 964 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
| 965 | gicr_set_isenabler( |
| 966 | gicv3_driver_data->rdistif_base_addrs[proc_num], id); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 967 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 968 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 969 | gicd_set_isenabler(gicv3_driver_data->gicd_base, id); |
| 970 | } |
| 971 | } |
| 972 | |
| 973 | /******************************************************************************* |
| 974 | * This function disables the interrupt identified by id. The proc_num |
| 975 | * is used if the interrupt is SGI or PPI, and programs the corresponding |
| 976 | * Redistributor interface. |
| 977 | ******************************************************************************/ |
| 978 | void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) |
| 979 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 980 | assert(gicv3_driver_data != NULL); |
| 981 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 982 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 983 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 984 | |
| 985 | /* |
| 986 | * Disable interrupt, and ensure that any shared variable updates |
| 987 | * depending on out of band interrupt trigger are observed afterwards. |
| 988 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 989 | |
| 990 | /* Check interrupt ID */ |
| 991 | if (is_sgi_ppi(id)) { |
| 992 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
| 993 | gicr_set_icenabler( |
| 994 | gicv3_driver_data->rdistif_base_addrs[proc_num], id); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 995 | |
| 996 | /* Write to clear enable requires waiting for pending writes */ |
| 997 | gicr_wait_for_pending_write( |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 998 | gicv3_driver_data->rdistif_base_addrs[proc_num]); |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 999 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1000 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1001 | gicd_set_icenabler(gicv3_driver_data->gicd_base, id); |
| 1002 | |
| 1003 | /* Write to clear enable requires waiting for pending writes */ |
| 1004 | gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); |
| 1005 | } |
| 1006 | |
| 1007 | dsbishst(); |
| 1008 | } |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1009 | |
| 1010 | /******************************************************************************* |
| 1011 | * This function sets the interrupt priority as supplied for the given interrupt |
| 1012 | * id. |
| 1013 | ******************************************************************************/ |
| 1014 | void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, |
| 1015 | unsigned int priority) |
| 1016 | { |
| 1017 | uintptr_t gicr_base; |
| 1018 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1019 | assert(gicv3_driver_data != NULL); |
| 1020 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1021 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1022 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1023 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1024 | /* Check interrupt ID */ |
| 1025 | if (is_sgi_ppi(id)) { |
| 1026 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1027 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
| 1028 | gicr_set_ipriorityr(gicr_base, id, priority); |
| 1029 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1030 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1031 | gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); |
| 1032 | } |
| 1033 | } |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1034 | |
| 1035 | /******************************************************************************* |
| 1036 | * This function assigns group for the interrupt identified by id. The proc_num |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1037 | * is used if the interrupt is SGI or (E)PPI, and programs the corresponding |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1038 | * Redistributor interface. The group can be any of GICV3_INTR_GROUP* |
| 1039 | ******************************************************************************/ |
| 1040 | void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, |
| 1041 | unsigned int type) |
| 1042 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1043 | bool igroup = false, grpmod = false; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1044 | uintptr_t gicr_base; |
| 1045 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1046 | assert(gicv3_driver_data != NULL); |
| 1047 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1048 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1049 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1050 | |
| 1051 | switch (type) { |
| 1052 | case INTR_GROUP1S: |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1053 | igroup = false; |
| 1054 | grpmod = true; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1055 | break; |
| 1056 | case INTR_GROUP0: |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1057 | igroup = false; |
| 1058 | grpmod = false; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1059 | break; |
| 1060 | case INTR_GROUP1NS: |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1061 | igroup = true; |
| 1062 | grpmod = false; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1063 | break; |
| 1064 | default: |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1065 | assert(false); |
Jonathan Wright | 39b4221 | 2018-03-13 15:24:29 +0000 | [diff] [blame] | 1066 | break; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1067 | } |
| 1068 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1069 | /* Check interrupt ID */ |
| 1070 | if (is_sgi_ppi(id)) { |
| 1071 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1072 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1073 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1074 | igroup ? gicr_set_igroupr(gicr_base, id) : |
| 1075 | gicr_clr_igroupr(gicr_base, id); |
| 1076 | grpmod ? gicr_set_igrpmodr(gicr_base, id) : |
| 1077 | gicr_clr_igrpmodr(gicr_base, id); |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1078 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1079 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
| 1080 | |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1081 | /* Serialize read-modify-write to Distributor registers */ |
| 1082 | spin_lock(&gic_lock); |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1083 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1084 | igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) : |
| 1085 | gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); |
| 1086 | grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) : |
| 1087 | gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); |
| 1088 | |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1089 | spin_unlock(&gic_lock); |
| 1090 | } |
| 1091 | } |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1092 | |
| 1093 | /******************************************************************************* |
| 1094 | * This function raises the specified Secure Group 0 SGI. |
| 1095 | * |
| 1096 | * The target parameter must be a valid MPIDR in the system. |
| 1097 | ******************************************************************************/ |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1098 | void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1099 | { |
| 1100 | unsigned int tgt, aff3, aff2, aff1, aff0; |
| 1101 | uint64_t sgi_val; |
| 1102 | |
| 1103 | /* Verify interrupt number is in the SGI range */ |
| 1104 | assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); |
| 1105 | |
| 1106 | /* Extract affinity fields from target */ |
| 1107 | aff0 = MPIDR_AFFLVL0_VAL(target); |
| 1108 | aff1 = MPIDR_AFFLVL1_VAL(target); |
| 1109 | aff2 = MPIDR_AFFLVL2_VAL(target); |
| 1110 | aff3 = MPIDR_AFFLVL3_VAL(target); |
| 1111 | |
| 1112 | /* |
| 1113 | * Make target list from affinity 0, and ensure GICv3 SGI can target |
| 1114 | * this PE. |
| 1115 | */ |
| 1116 | assert(aff0 < GICV3_MAX_SGI_TARGETS); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1117 | tgt = BIT_32(aff0); |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1118 | |
| 1119 | /* Raise SGI to PE specified by its affinity */ |
| 1120 | sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, |
| 1121 | tgt); |
| 1122 | |
| 1123 | /* |
| 1124 | * Ensure that any shared variable updates depending on out of band |
| 1125 | * interrupt trigger are observed before raising SGI. |
| 1126 | */ |
| 1127 | dsbishst(); |
| 1128 | write_icc_sgi0r_el1(sgi_val); |
| 1129 | isb(); |
| 1130 | } |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1131 | |
| 1132 | /******************************************************************************* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1133 | * This function sets the interrupt routing for the given (E)SPI interrupt id. |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1134 | * The interrupt routing is specified in routing mode and mpidr. |
| 1135 | * |
| 1136 | * The routing mode can be either of: |
| 1137 | * - GICV3_IRM_ANY |
| 1138 | * - GICV3_IRM_PE |
| 1139 | * |
| 1140 | * The mpidr is the affinity of the PE to which the interrupt will be routed, |
| 1141 | * and is ignored for routing mode GICV3_IRM_ANY. |
| 1142 | ******************************************************************************/ |
| 1143 | void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) |
| 1144 | { |
| 1145 | unsigned long long aff; |
| 1146 | uint64_t router; |
| 1147 | |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1148 | assert(gicv3_driver_data != NULL); |
| 1149 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1150 | |
| 1151 | assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1152 | |
| 1153 | assert(IS_SPI(id)); |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1154 | |
| 1155 | aff = gicd_irouter_val_from_mpidr(mpidr, irm); |
| 1156 | gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); |
| 1157 | |
| 1158 | /* |
| 1159 | * In implementations that do not require 1 of N distribution of SPIs, |
| 1160 | * IRM might be RAZ/WI. Read back and verify IRM bit. |
| 1161 | */ |
| 1162 | if (irm == GICV3_IRM_ANY) { |
| 1163 | router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1164 | if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1165 | ERROR("GICv3 implementation doesn't support routing ANY\n"); |
| 1166 | panic(); |
| 1167 | } |
| 1168 | } |
| 1169 | } |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1170 | |
| 1171 | /******************************************************************************* |
| 1172 | * This function clears the pending status of an interrupt identified by id. |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1173 | * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1174 | * corresponding Redistributor interface. |
| 1175 | ******************************************************************************/ |
| 1176 | void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) |
| 1177 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1178 | assert(gicv3_driver_data != NULL); |
| 1179 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1180 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1181 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1182 | |
| 1183 | /* |
| 1184 | * Clear pending interrupt, and ensure that any shared variable updates |
| 1185 | * depending on out of band interrupt trigger are observed afterwards. |
| 1186 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1187 | |
| 1188 | /* Check interrupt ID */ |
| 1189 | if (is_sgi_ppi(id)) { |
| 1190 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
| 1191 | gicr_set_icpendr( |
| 1192 | gicv3_driver_data->rdistif_base_addrs[proc_num], id); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1193 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1194 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1195 | gicd_set_icpendr(gicv3_driver_data->gicd_base, id); |
| 1196 | } |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1197 | |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1198 | dsbishst(); |
| 1199 | } |
| 1200 | |
| 1201 | /******************************************************************************* |
| 1202 | * This function sets the pending status of an interrupt identified by id. |
| 1203 | * The proc_num is used if the interrupt is SGI or PPI and programs the |
| 1204 | * corresponding Redistributor interface. |
| 1205 | ******************************************************************************/ |
| 1206 | void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) |
| 1207 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1208 | assert(gicv3_driver_data != NULL); |
| 1209 | assert(gicv3_driver_data->gicd_base != 0U); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1210 | assert(proc_num < gicv3_driver_data->rdistif_num); |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 1211 | assert(gicv3_driver_data->rdistif_base_addrs != NULL); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1212 | |
| 1213 | /* |
| 1214 | * Ensure that any shared variable updates depending on out of band |
| 1215 | * interrupt trigger are observed before setting interrupt pending. |
| 1216 | */ |
| 1217 | dsbishst(); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1218 | |
| 1219 | /* Check interrupt ID */ |
| 1220 | if (is_sgi_ppi(id)) { |
| 1221 | /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ |
| 1222 | gicr_set_ispendr( |
| 1223 | gicv3_driver_data->rdistif_base_addrs[proc_num], id); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1224 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1225 | /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1226 | gicd_set_ispendr(gicv3_driver_data->gicd_base, id); |
| 1227 | } |
| 1228 | } |
Jeenu Viswambharan | 6250507 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1229 | |
| 1230 | /******************************************************************************* |
| 1231 | * This function sets the PMR register with the supplied value. Returns the |
| 1232 | * original PMR. |
| 1233 | ******************************************************************************/ |
| 1234 | unsigned int gicv3_set_pmr(unsigned int mask) |
| 1235 | { |
| 1236 | unsigned int old_mask; |
| 1237 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1238 | old_mask = (unsigned int)read_icc_pmr_el1(); |
Jeenu Viswambharan | 6250507 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 1239 | |
| 1240 | /* |
| 1241 | * Order memory updates w.r.t. PMR write, and ensure they're visible |
| 1242 | * before potential out of band interrupt trigger because of PMR update. |
| 1243 | * PMR system register writes are self-synchronizing, so no ISB required |
| 1244 | * thereafter. |
| 1245 | */ |
| 1246 | dsbishst(); |
| 1247 | write_icc_pmr_el1(mask); |
| 1248 | |
| 1249 | return old_mask; |
| 1250 | } |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1251 | |
| 1252 | /******************************************************************************* |
| 1253 | * This function delegates the responsibility of discovering the corresponding |
| 1254 | * Redistributor frames to each CPU itself. It is a modified version of |
| 1255 | * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform |
| 1256 | * unlike the previous way in which only the Primary CPU did the discovery of |
| 1257 | * all the Redistributor frames for every CPU. It also handles the scenario in |
| 1258 | * which the frames of various CPUs are not contiguous in physical memory. |
| 1259 | ******************************************************************************/ |
| 1260 | int gicv3_rdistif_probe(const uintptr_t gicr_frame) |
| 1261 | { |
Heyi Guo | 3a579ae | 2020-05-19 11:50:40 +0800 | [diff] [blame] | 1262 | u_register_t mpidr, mpidr_self; |
| 1263 | unsigned int proc_num; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1264 | uint64_t typer_val; |
| 1265 | uintptr_t rdistif_base; |
| 1266 | bool gicr_frame_found = false; |
| 1267 | |
| 1268 | assert(gicv3_driver_data->gicr_base == 0U); |
| 1269 | |
| 1270 | /* Ensure this function is called with Data Cache enabled */ |
| 1271 | #ifndef __aarch64__ |
| 1272 | assert((read_sctlr() & SCTLR_C_BIT) != 0U); |
| 1273 | #else |
| 1274 | assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); |
| 1275 | #endif /* !__aarch64__ */ |
| 1276 | |
Heyi Guo | 3a579ae | 2020-05-19 11:50:40 +0800 | [diff] [blame] | 1277 | mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1278 | rdistif_base = gicr_frame; |
| 1279 | do { |
| 1280 | typer_val = gicr_read_typer(rdistif_base); |
Heyi Guo | 3a579ae | 2020-05-19 11:50:40 +0800 | [diff] [blame] | 1281 | mpidr = mpidr_from_gicr_typer(typer_val); |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1282 | if (gicv3_driver_data->mpidr_to_core_pos != NULL) { |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1283 | proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); |
| 1284 | } else { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1285 | proc_num = (unsigned int)(typer_val >> |
| 1286 | TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1287 | } |
Heyi Guo | 3a579ae | 2020-05-19 11:50:40 +0800 | [diff] [blame] | 1288 | if (mpidr == mpidr_self) { |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1289 | /* The base address doesn't need to be initialized on |
| 1290 | * every warm boot. |
| 1291 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1292 | if (gicv3_driver_data->rdistif_base_addrs[proc_num] |
| 1293 | != 0U) { |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1294 | return 0; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1295 | } |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1296 | gicv3_driver_data->rdistif_base_addrs[proc_num] = |
| 1297 | rdistif_base; |
| 1298 | gicr_frame_found = true; |
| 1299 | break; |
| 1300 | } |
| 1301 | rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); |
| 1302 | } while ((typer_val & TYPER_LAST_BIT) == 0U); |
| 1303 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1304 | if (!gicr_frame_found) { |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1305 | return -1; |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1306 | } |
Madhukar Pappireddy | 5fd1f9d | 2019-05-15 18:25:41 -0500 | [diff] [blame] | 1307 | |
| 1308 | /* |
| 1309 | * Flush the driver data to ensure coherency. This is |
| 1310 | * not required if platform has HW_ASSISTED_COHERENCY |
| 1311 | * enabled. |
| 1312 | */ |
| 1313 | #if !HW_ASSISTED_COHERENCY |
| 1314 | /* |
| 1315 | * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. |
| 1316 | */ |
| 1317 | flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), |
| 1318 | sizeof(*(gicv3_driver_data->rdistif_base_addrs))); |
| 1319 | #endif |
| 1320 | return 0; /* Found matching GICR frame */ |
| 1321 | } |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 1322 | |
| 1323 | /****************************************************************************** |
| 1324 | * This function checks the interrupt ID and returns true for SGIs and (E)PPIs |
| 1325 | * and false for (E)SPIs IDs. |
| 1326 | *****************************************************************************/ |
| 1327 | static bool is_sgi_ppi(unsigned int id) |
| 1328 | { |
| 1329 | /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ |
| 1330 | if (IS_SGI_PPI(id)) { |
| 1331 | return true; |
| 1332 | } |
| 1333 | |
| 1334 | /* SPIs: 32-1019, ESPIs: 4096-5119 */ |
| 1335 | if (IS_SPI(id)) { |
| 1336 | return false; |
| 1337 | } |
| 1338 | |
| 1339 | assert(false); |
| 1340 | panic(); |
| 1341 | } |