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Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Soby Mathew72645132017-02-14 10:11:52 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <debug.h>
11#include <gic_common.h>
12#include <gicv2.h>
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010013#include <interrupt_props.h>
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010014#include <spinlock.h>
Soby Mathew50f6fe42016-02-01 17:59:22 +000015#include "../common/gic_common_private.h"
Soby Mathewe063d3c2015-10-07 09:45:27 +010016#include "gicv2_private.h"
17
18static const gicv2_driver_data_t *driver_data;
19
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010020/*
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
24 */
25spinlock_t gic_lock;
26
Soby Mathewe063d3c2015-10-07 09:45:27 +010027/*******************************************************************************
28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
29 * and set the priority mask register to allow all interrupts to trickle in.
30 ******************************************************************************/
31void gicv2_cpuif_enable(void)
32{
33 unsigned int val;
34
35 assert(driver_data);
36 assert(driver_data->gicc_base);
37
38 /*
39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1
40 * bypass.
41 */
42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0;
43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
44
45 /* Program the idle priority in the PMR */
46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK);
47 gicc_write_ctlr(driver_data->gicc_base, val);
48}
49
50/*******************************************************************************
51 * Place the cpu interface in a state where it can never make a cpu exit wfi as
52 * as result of an asserted interrupt. This is critical for powering down a cpu
53 ******************************************************************************/
54void gicv2_cpuif_disable(void)
55{
56 unsigned int val;
57
58 assert(driver_data);
59 assert(driver_data->gicc_base);
60
61 /* Disable secure, non-secure interrupts and disable their bypass */
62 val = gicc_read_ctlr(driver_data->gicc_base);
63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT);
64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
66 gicc_write_ctlr(driver_data->gicc_base, val);
67}
68
69/*******************************************************************************
70 * Per cpu gic distributor setup which will be done by all cpus after a cold
71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them.
72 ******************************************************************************/
73void gicv2_pcpu_distif_init(void)
74{
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +000075 unsigned int ctlr;
76
Soby Mathewe063d3c2015-10-07 09:45:27 +010077 assert(driver_data);
78 assert(driver_data->gicd_base);
Soby Mathewe063d3c2015-10-07 09:45:27 +010079
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010080#if !ERROR_DEPRECATED
81 if (driver_data->interrupt_props != NULL) {
82#endif
83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
84 driver_data->interrupt_props,
85 driver_data->interrupt_props_num);
86#if !ERROR_DEPRECATED
87 } else {
88 assert(driver_data->g0_interrupt_array);
89 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base,
90 driver_data->g0_interrupt_num,
91 driver_data->g0_interrupt_array);
92 }
93#endif
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +000094
95 /* Enable G0 interrupts if not already */
96 ctlr = gicd_read_ctlr(driver_data->gicd_base);
97 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) {
98 gicd_write_ctlr(driver_data->gicd_base,
99 ctlr | CTLR_ENABLE_G0_BIT);
100 }
Soby Mathewe063d3c2015-10-07 09:45:27 +0100101}
102
103/*******************************************************************************
104 * Global gic distributor init which will be done by the primary cpu after a
105 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
106 * then enables the secure GIC distributor interface.
107 ******************************************************************************/
108void gicv2_distif_init(void)
109{
110 unsigned int ctlr;
111
112 assert(driver_data);
113 assert(driver_data->gicd_base);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100114
115 /* Disable the distributor before going further */
116 ctlr = gicd_read_ctlr(driver_data->gicd_base);
117 gicd_write_ctlr(driver_data->gicd_base,
118 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT));
119
120 /* Set the default attribute of all SPIs */
121 gicv2_spis_configure_defaults(driver_data->gicd_base);
122
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100123#if !ERROR_DEPRECATED
124 if (driver_data->interrupt_props != NULL) {
125#endif
126 gicv2_secure_spis_configure_props(driver_data->gicd_base,
127 driver_data->interrupt_props,
128 driver_data->interrupt_props_num);
129#if !ERROR_DEPRECATED
130 } else {
131 assert(driver_data->g0_interrupt_array);
132
133 /* Configure the G0 SPIs */
134 gicv2_secure_spis_configure(driver_data->gicd_base,
135 driver_data->g0_interrupt_num,
136 driver_data->g0_interrupt_array);
137 }
138#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100139
140 /* Re-enable the secure SPIs now that they have been configured */
141 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
142}
143
144/*******************************************************************************
145 * Initialize the ARM GICv2 driver with the provided platform inputs
146 ******************************************************************************/
147void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
148{
149 unsigned int gic_version;
150 assert(plat_driver_data);
151 assert(plat_driver_data->gicd_base);
152 assert(plat_driver_data->gicc_base);
153
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100154#if !ERROR_DEPRECATED
155 if (plat_driver_data->interrupt_props == NULL) {
156 /* Interrupt properties array size must be 0 */
157 assert(plat_driver_data->interrupt_props_num == 0);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100158
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100159 /* The platform should provide a list of secure interrupts */
160 assert(plat_driver_data->g0_interrupt_array);
161
162 /*
163 * If there are no interrupts of a particular type, then the
164 * number of interrupts of that type should be 0 and vice-versa.
165 */
166 assert(plat_driver_data->g0_interrupt_array ?
167 plat_driver_data->g0_interrupt_num :
168 plat_driver_data->g0_interrupt_num == 0);
169 }
170#else
171 assert(plat_driver_data->interrupt_props != NULL);
172 assert(plat_driver_data->interrupt_props_num > 0);
173#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100174
175 /* Ensure that this is a GICv2 system */
176 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
177 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT)
178 & PIDR2_ARCH_REV_MASK;
Etienne Carriere0a8c3532017-11-05 22:57:38 +0100179
180 /*
181 * GICv1 with security extension complies with trusted firmware
182 * GICv2 driver as far as virtualization and few tricky power
183 * features are not used. GICv2 features that are not supported
184 * by GICv1 with Security Extensions are:
185 * - virtual interrupt support.
186 * - wake up events.
187 * - writeable GIC state register (for power sequences)
188 * - interrupt priority drop.
189 * - interrupt signal bypass.
190 */
191 assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100192
193 driver_data = plat_driver_data;
194
Soby Mathew72645132017-02-14 10:11:52 +0000195 /*
196 * The GIC driver data is initialized by the primary CPU with caches
197 * enabled. When the secondary CPU boots up, it initializes the
198 * GICC/GICR interface with the caches disabled. Hence flush the
199 * driver_data to ensure coherency. This is not required if the
200 * platform has HW_ASSISTED_COHERENCY enabled.
201 */
202#if !HW_ASSISTED_COHERENCY
203 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
204 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
205#endif
Soby Mathewe063d3c2015-10-07 09:45:27 +0100206 INFO("ARM GICv2 driver initialized\n");
207}
208
209/******************************************************************************
210 * This function returns whether FIQ is enabled in the GIC CPU interface.
211 *****************************************************************************/
212unsigned int gicv2_is_fiq_enabled(void)
213{
214 unsigned int gicc_ctlr;
215
216 assert(driver_data);
217 assert(driver_data->gicc_base);
218
219 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
220 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1;
221}
222
223/*******************************************************************************
224 * This function returns the type of the highest priority pending interrupt at
225 * the GIC cpu interface. The return values can be one of the following :
226 * PENDING_G1_INTID : The interrupt type is non secure Group 1.
227 * 0 - 1019 : The interrupt type is secure Group 0.
228 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
229 * sufficient priority to be signaled
230 ******************************************************************************/
231unsigned int gicv2_get_pending_interrupt_type(void)
232{
233 assert(driver_data);
234 assert(driver_data->gicc_base);
235
236 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
237}
238
239/*******************************************************************************
240 * This function returns the id of the highest priority pending interrupt at
241 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no
242 * interrupt pending.
243 ******************************************************************************/
244unsigned int gicv2_get_pending_interrupt_id(void)
245{
246 unsigned int id;
247
248 assert(driver_data);
249 assert(driver_data->gicc_base);
250
251 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
252
253 /*
254 * Find out which non-secure interrupt it is under the assumption that
255 * the GICC_CTLR.AckCtl bit is 0.
256 */
257 if (id == PENDING_G1_INTID)
258 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK;
259
260 return id;
261}
262
263/*******************************************************************************
264 * This functions reads the GIC cpu interface Interrupt Acknowledge register
265 * to start handling the pending secure 0 interrupt. It returns the
266 * contents of the IAR.
267 ******************************************************************************/
268unsigned int gicv2_acknowledge_interrupt(void)
269{
270 assert(driver_data);
271 assert(driver_data->gicc_base);
272
273 return gicc_read_IAR(driver_data->gicc_base);
274}
275
276/*******************************************************************************
277 * This functions writes the GIC cpu interface End Of Interrupt register with
278 * the passed value to finish handling the active secure group 0 interrupt.
279 ******************************************************************************/
280void gicv2_end_of_interrupt(unsigned int id)
281{
282 assert(driver_data);
283 assert(driver_data->gicc_base);
284
285 gicc_write_EOIR(driver_data->gicc_base, id);
286}
287
288/*******************************************************************************
289 * This function returns the type of the interrupt id depending upon the group
290 * this interrupt has been configured under by the interrupt controller i.e.
291 * group0 secure or group1 non secure. It returns zero for Group 0 secure and
292 * one for Group 1 non secure interrupt.
293 ******************************************************************************/
294unsigned int gicv2_get_interrupt_group(unsigned int id)
295{
296 assert(driver_data);
297 assert(driver_data->gicd_base);
298
299 return gicd_get_igroupr(driver_data->gicd_base, id);
300}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100301
302/*******************************************************************************
303 * This function returns the priority of the interrupt the processor is
304 * currently servicing.
305 ******************************************************************************/
306unsigned int gicv2_get_running_priority(void)
307{
308 assert(driver_data);
309 assert(driver_data->gicc_base);
310
311 return gicc_read_rpr(driver_data->gicc_base);
312}
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100313
314/*******************************************************************************
315 * This function sets the GICv2 target mask pattern for the current PE. The PE
316 * target mask is used to translate linear PE index (returned by platform core
317 * position) to a bit mask used when targeting interrupts to a PE, viz. when
318 * raising SGIs and routing SPIs.
319 ******************************************************************************/
320void gicv2_set_pe_target_mask(unsigned int proc_num)
321{
322 assert(driver_data);
323 assert(driver_data->gicd_base);
324 assert(driver_data->target_masks);
325 assert(proc_num < GICV2_MAX_TARGET_PE);
326 assert(proc_num < driver_data->target_masks_num);
327
328 /* Return if the target mask is already populated */
329 if (driver_data->target_masks[proc_num])
330 return;
331
Jeenu Viswambharanfbf5bda2017-11-07 16:10:19 +0000332 /*
333 * Update target register corresponding to this CPU and flush for it to
334 * be visible to other CPUs.
335 */
336 if (driver_data->target_masks[proc_num] == 0) {
337 driver_data->target_masks[proc_num] =
338 gicv2_get_cpuif_id(driver_data->gicd_base);
339#if !HW_ASSISTED_COHERENCY
340 /*
341 * PEs only update their own masks. Primary updates it with
342 * caches on. But because secondaries does it with caches off,
343 * all updates go to memory directly, and there's no danger of
344 * secondaries overwriting each others' mask, despite
345 * target_masks[] not being cache line aligned.
346 */
347 flush_dcache_range((uintptr_t)
348 &driver_data->target_masks[proc_num],
349 sizeof(driver_data->target_masks[proc_num]));
350#endif
351 }
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100352}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100353
354/*******************************************************************************
355 * This function returns the active status of the interrupt (either because the
356 * state is active, or active and pending).
357 ******************************************************************************/
358unsigned int gicv2_get_interrupt_active(unsigned int id)
359{
360 assert(driver_data);
361 assert(driver_data->gicd_base);
362 assert(id <= MAX_SPI_ID);
363
364 return gicd_get_isactiver(driver_data->gicd_base, id);
365}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100366
367/*******************************************************************************
368 * This function enables the interrupt identified by id.
369 ******************************************************************************/
370void gicv2_enable_interrupt(unsigned int id)
371{
372 assert(driver_data);
373 assert(driver_data->gicd_base);
374 assert(id <= MAX_SPI_ID);
375
376 /*
377 * Ensure that any shared variable updates depending on out of band
378 * interrupt trigger are observed before enabling interrupt.
379 */
380 dsbishst();
381 gicd_set_isenabler(driver_data->gicd_base, id);
382}
383
384/*******************************************************************************
385 * This function disables the interrupt identified by id.
386 ******************************************************************************/
387void gicv2_disable_interrupt(unsigned int id)
388{
389 assert(driver_data);
390 assert(driver_data->gicd_base);
391 assert(id <= MAX_SPI_ID);
392
393 /*
394 * Disable interrupt, and ensure that any shared variable updates
395 * depending on out of band interrupt trigger are observed afterwards.
396 */
397 gicd_set_icenabler(driver_data->gicd_base, id);
398 dsbishst();
399}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100400
401/*******************************************************************************
402 * This function sets the interrupt priority as supplied for the given interrupt
403 * id.
404 ******************************************************************************/
405void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
406{
407 assert(driver_data);
408 assert(driver_data->gicd_base);
409 assert(id <= MAX_SPI_ID);
410
411 gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
412}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100413
414/*******************************************************************************
415 * This function assigns group for the interrupt identified by id. The group can
416 * be any of GICV2_INTR_GROUP*
417 ******************************************************************************/
418void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
419{
420 assert(driver_data);
421 assert(driver_data->gicd_base);
422 assert(id <= MAX_SPI_ID);
423
424 /* Serialize read-modify-write to Distributor registers */
425 spin_lock(&gic_lock);
426 switch (type) {
427 case GICV2_INTR_GROUP1:
428 gicd_set_igroupr(driver_data->gicd_base, id);
429 break;
430 case GICV2_INTR_GROUP0:
431 gicd_clr_igroupr(driver_data->gicd_base, id);
432 break;
433 default:
434 assert(0);
435 }
436 spin_unlock(&gic_lock);
437}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100438
439/*******************************************************************************
440 * This function raises the specified SGI to requested targets.
441 *
442 * The proc_num parameter must be the linear index of the target PE in the
443 * system.
444 ******************************************************************************/
445void gicv2_raise_sgi(int sgi_num, int proc_num)
446{
447 unsigned int sgir_val, target;
448
449 assert(driver_data);
450 assert(proc_num < GICV2_MAX_TARGET_PE);
451 assert(driver_data->gicd_base);
452
453 /*
454 * Target masks array must have been supplied, and the core position
455 * should be valid.
456 */
457 assert(driver_data->target_masks);
458 assert(proc_num < driver_data->target_masks_num);
459
460 /* Don't raise SGI if the mask hasn't been populated */
461 target = driver_data->target_masks[proc_num];
462 assert(target != 0);
463
464 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
465
466 /*
467 * Ensure that any shared variable updates depending on out of band
468 * interrupt trigger are observed before raising SGI.
469 */
470 dsbishst();
471 gicd_write_sgir(driver_data->gicd_base, sgir_val);
472}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100473
474/*******************************************************************************
475 * This function sets the interrupt routing for the given SPI interrupt id.
476 * The interrupt routing is specified in routing mode. The proc_num parameter is
477 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target
478 * all PEs.
479 ******************************************************************************/
480void gicv2_set_spi_routing(unsigned int id, int proc_num)
481{
482 int target;
483
484 assert(driver_data);
485 assert(driver_data->gicd_base);
486
487 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
488
489 /*
490 * Target masks array must have been supplied, and the core position
491 * should be valid.
492 */
493 assert(driver_data->target_masks);
494 assert(proc_num < GICV2_MAX_TARGET_PE);
495 assert(proc_num < driver_data->target_masks_num);
496
497 if (proc_num < 0) {
498 /* Target all PEs */
499 target = GIC_TARGET_CPU_MASK;
500 } else {
501 /* Don't route interrupt if the mask hasn't been populated */
502 target = driver_data->target_masks[proc_num];
503 assert(target != 0);
504 }
505
506 gicd_set_itargetsr(driver_data->gicd_base, id, target);
507}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100508
509/*******************************************************************************
510 * This function clears the pending status of an interrupt identified by id.
511 ******************************************************************************/
512void gicv2_clear_interrupt_pending(unsigned int id)
513{
514 assert(driver_data);
515 assert(driver_data->gicd_base);
516
517 /* SGIs can't be cleared pending */
518 assert(id >= MIN_PPI_ID);
519
520 /*
521 * Clear pending interrupt, and ensure that any shared variable updates
522 * depending on out of band interrupt trigger are observed afterwards.
523 */
524 gicd_set_icpendr(driver_data->gicd_base, id);
525 dsbishst();
526}
527
528/*******************************************************************************
529 * This function sets the pending status of an interrupt identified by id.
530 ******************************************************************************/
531void gicv2_set_interrupt_pending(unsigned int id)
532{
533 assert(driver_data);
534 assert(driver_data->gicd_base);
535
536 /* SGIs can't be cleared pending */
537 assert(id >= MIN_PPI_ID);
538
539 /*
540 * Ensure that any shared variable updates depending on out of band
541 * interrupt trigger are observed before setting interrupt pending.
542 */
543 dsbishst();
544 gicd_set_ispendr(driver_data->gicd_base, id);
545}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100546
547/*******************************************************************************
548 * This function sets the PMR register with the supplied value. Returns the
549 * original PMR.
550 ******************************************************************************/
551unsigned int gicv2_set_pmr(unsigned int mask)
552{
553 unsigned int old_mask;
554
555 assert(driver_data);
556 assert(driver_data->gicc_base);
557
558 old_mask = gicc_read_pmr(driver_data->gicc_base);
559
560 /*
561 * Order memory updates w.r.t. PMR write, and ensure they're visible
562 * before potential out of band interrupt trigger because of PMR update.
563 */
564 dmbishst();
565 gicc_write_pmr(driver_data->gicc_base, mask);
566 dsbishst();
567
568 return old_mask;
569}