Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for pin control. |
| 9 | */ |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <platform.h> |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 13 | #include <string.h> |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 14 | #include "pm_api_pinctrl.h" |
| 15 | #include "pm_api_sys.h" |
| 16 | #include "pm_client.h" |
| 17 | #include "pm_common.h" |
| 18 | #include "pm_ipi.h" |
| 19 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 20 | #define PINCTRL_FUNCTION_MASK U(0xFE) |
| 21 | #define PINCTRL_VOLTAGE_STATUS_MASK U(0x01) |
| 22 | #define NFUNCS_PER_PIN U(13) |
| 23 | #define PINCTRL_NUM_MIOS U(78) |
| 24 | #define MAX_PIN_PER_REG U(26) |
| 25 | #define PINCTRL_BANK_ADDR_STEP U(28) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 26 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 27 | #define PINCTRL_DRVSTRN0_REG_OFFSET U(0) |
| 28 | #define PINCTRL_DRVSTRN1_REG_OFFSET U(4) |
| 29 | #define PINCTRL_SCHCMOS_REG_OFFSET U(8) |
| 30 | #define PINCTRL_PULLCTRL_REG_OFFSET U(12) |
| 31 | #define PINCTRL_PULLSTAT_REG_OFFSET U(16) |
| 32 | #define PINCTRL_SLEWCTRL_REG_OFFSET U(20) |
| 33 | #define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 34 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 35 | #define IOU_SLCR_BANK1_CTRL5 U(0XFF180164) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 36 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 37 | #define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \ |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 38 | ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 39 | ((miopin) / MAX_PIN_PER_REG) + (reg)) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 40 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 41 | #define PINCTRL_PIN_OFFSET(_miopin) \ |
| 42 | ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG))) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 43 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 44 | #define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \ |
| 45 | (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 46 | |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 47 | static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = { |
| 48 | 0x02, 0x04, 0x08, 0x10, 0x18, |
| 49 | 0x00, 0x20, 0x40, 0x60, 0x80, |
| 50 | 0xA0, 0xC0, 0xE0 |
| 51 | }; |
| 52 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 53 | struct pinctrl_function { |
| 54 | char name[FUNCTION_NAME_LEN]; |
| 55 | uint16_t (*groups)[]; |
| 56 | uint8_t regval; |
| 57 | }; |
| 58 | |
| 59 | /* Max groups for one pin */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 60 | #define MAX_PIN_GROUPS U(13) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 61 | |
| 62 | struct zynqmp_pin_group { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 63 | uint16_t (*groups)[]; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { |
| 67 | [PINCTRL_FUNC_CAN0] = { |
| 68 | .name = "can0", |
| 69 | .regval = 0x20, |
| 70 | .groups = &((uint16_t []) { |
| 71 | PINCTRL_GRP_CAN0_0, |
| 72 | PINCTRL_GRP_CAN0_1, |
| 73 | PINCTRL_GRP_CAN0_2, |
| 74 | PINCTRL_GRP_CAN0_3, |
| 75 | PINCTRL_GRP_CAN0_4, |
| 76 | PINCTRL_GRP_CAN0_5, |
| 77 | PINCTRL_GRP_CAN0_6, |
| 78 | PINCTRL_GRP_CAN0_7, |
| 79 | PINCTRL_GRP_CAN0_8, |
| 80 | PINCTRL_GRP_CAN0_9, |
| 81 | PINCTRL_GRP_CAN0_10, |
| 82 | PINCTRL_GRP_CAN0_11, |
| 83 | PINCTRL_GRP_CAN0_12, |
| 84 | PINCTRL_GRP_CAN0_13, |
| 85 | PINCTRL_GRP_CAN0_14, |
| 86 | PINCTRL_GRP_CAN0_15, |
| 87 | PINCTRL_GRP_CAN0_16, |
| 88 | PINCTRL_GRP_CAN0_17, |
| 89 | PINCTRL_GRP_CAN0_18, |
| 90 | END_OF_GROUPS, |
| 91 | }), |
| 92 | }, |
| 93 | [PINCTRL_FUNC_CAN1] = { |
| 94 | .name = "can1", |
| 95 | .regval = 0x20, |
| 96 | .groups = &((uint16_t []) { |
| 97 | PINCTRL_GRP_CAN1_0, |
| 98 | PINCTRL_GRP_CAN1_1, |
| 99 | PINCTRL_GRP_CAN1_2, |
| 100 | PINCTRL_GRP_CAN1_3, |
| 101 | PINCTRL_GRP_CAN1_4, |
| 102 | PINCTRL_GRP_CAN1_5, |
| 103 | PINCTRL_GRP_CAN1_6, |
| 104 | PINCTRL_GRP_CAN1_7, |
| 105 | PINCTRL_GRP_CAN1_8, |
| 106 | PINCTRL_GRP_CAN1_9, |
| 107 | PINCTRL_GRP_CAN1_10, |
| 108 | PINCTRL_GRP_CAN1_11, |
| 109 | PINCTRL_GRP_CAN1_12, |
| 110 | PINCTRL_GRP_CAN1_13, |
| 111 | PINCTRL_GRP_CAN1_14, |
| 112 | PINCTRL_GRP_CAN1_15, |
| 113 | PINCTRL_GRP_CAN1_16, |
| 114 | PINCTRL_GRP_CAN1_17, |
| 115 | PINCTRL_GRP_CAN1_18, |
| 116 | PINCTRL_GRP_CAN1_19, |
| 117 | END_OF_GROUPS, |
| 118 | }), |
| 119 | }, |
| 120 | [PINCTRL_FUNC_ETHERNET0] = { |
| 121 | .name = "ethernet0", |
| 122 | .regval = 0x02, |
| 123 | .groups = &((uint16_t []) { |
| 124 | PINCTRL_GRP_ETHERNET0_0, |
| 125 | END_OF_GROUPS, |
| 126 | }), |
| 127 | }, |
| 128 | [PINCTRL_FUNC_ETHERNET1] = { |
| 129 | .name = "ethernet1", |
| 130 | .regval = 0x02, |
| 131 | .groups = &((uint16_t []) { |
| 132 | PINCTRL_GRP_ETHERNET1_0, |
| 133 | END_OF_GROUPS, |
| 134 | }), |
| 135 | }, |
| 136 | [PINCTRL_FUNC_ETHERNET2] = { |
| 137 | .name = "ethernet2", |
| 138 | .regval = 0x02, |
| 139 | .groups = &((uint16_t []) { |
| 140 | PINCTRL_GRP_ETHERNET2_0, |
| 141 | END_OF_GROUPS, |
| 142 | }), |
| 143 | }, |
| 144 | [PINCTRL_FUNC_ETHERNET3] = { |
| 145 | .name = "ethernet3", |
| 146 | .regval = 0x02, |
| 147 | .groups = &((uint16_t []) { |
| 148 | PINCTRL_GRP_ETHERNET3_0, |
| 149 | END_OF_GROUPS, |
| 150 | }), |
| 151 | }, |
| 152 | [PINCTRL_FUNC_GEMTSU0] = { |
| 153 | .name = "gemtsu0", |
| 154 | .regval = 0x02, |
| 155 | .groups = &((uint16_t []) { |
| 156 | PINCTRL_GRP_GEMTSU0_0, |
| 157 | PINCTRL_GRP_GEMTSU0_1, |
| 158 | PINCTRL_GRP_GEMTSU0_2, |
| 159 | END_OF_GROUPS, |
| 160 | }), |
| 161 | }, |
| 162 | [PINCTRL_FUNC_GPIO0] = { |
| 163 | .name = "gpio0", |
| 164 | .regval = 0x00, |
| 165 | .groups = &((uint16_t []) { |
| 166 | PINCTRL_GRP_GPIO0_0, |
| 167 | PINCTRL_GRP_GPIO0_1, |
| 168 | PINCTRL_GRP_GPIO0_2, |
| 169 | PINCTRL_GRP_GPIO0_3, |
| 170 | PINCTRL_GRP_GPIO0_4, |
| 171 | PINCTRL_GRP_GPIO0_5, |
| 172 | PINCTRL_GRP_GPIO0_6, |
| 173 | PINCTRL_GRP_GPIO0_7, |
| 174 | PINCTRL_GRP_GPIO0_8, |
| 175 | PINCTRL_GRP_GPIO0_9, |
| 176 | PINCTRL_GRP_GPIO0_10, |
| 177 | PINCTRL_GRP_GPIO0_11, |
| 178 | PINCTRL_GRP_GPIO0_12, |
| 179 | PINCTRL_GRP_GPIO0_13, |
| 180 | PINCTRL_GRP_GPIO0_14, |
| 181 | PINCTRL_GRP_GPIO0_15, |
| 182 | PINCTRL_GRP_GPIO0_16, |
| 183 | PINCTRL_GRP_GPIO0_17, |
| 184 | PINCTRL_GRP_GPIO0_18, |
| 185 | PINCTRL_GRP_GPIO0_19, |
| 186 | PINCTRL_GRP_GPIO0_20, |
| 187 | PINCTRL_GRP_GPIO0_21, |
| 188 | PINCTRL_GRP_GPIO0_22, |
| 189 | PINCTRL_GRP_GPIO0_23, |
| 190 | PINCTRL_GRP_GPIO0_24, |
| 191 | PINCTRL_GRP_GPIO0_25, |
| 192 | PINCTRL_GRP_GPIO0_26, |
| 193 | PINCTRL_GRP_GPIO0_27, |
| 194 | PINCTRL_GRP_GPIO0_28, |
| 195 | PINCTRL_GRP_GPIO0_29, |
| 196 | PINCTRL_GRP_GPIO0_30, |
| 197 | PINCTRL_GRP_GPIO0_31, |
| 198 | PINCTRL_GRP_GPIO0_32, |
| 199 | PINCTRL_GRP_GPIO0_33, |
| 200 | PINCTRL_GRP_GPIO0_34, |
| 201 | PINCTRL_GRP_GPIO0_35, |
| 202 | PINCTRL_GRP_GPIO0_36, |
| 203 | PINCTRL_GRP_GPIO0_37, |
| 204 | PINCTRL_GRP_GPIO0_38, |
| 205 | PINCTRL_GRP_GPIO0_39, |
| 206 | PINCTRL_GRP_GPIO0_40, |
| 207 | PINCTRL_GRP_GPIO0_41, |
| 208 | PINCTRL_GRP_GPIO0_42, |
| 209 | PINCTRL_GRP_GPIO0_43, |
| 210 | PINCTRL_GRP_GPIO0_44, |
| 211 | PINCTRL_GRP_GPIO0_45, |
| 212 | PINCTRL_GRP_GPIO0_46, |
| 213 | PINCTRL_GRP_GPIO0_47, |
| 214 | PINCTRL_GRP_GPIO0_48, |
| 215 | PINCTRL_GRP_GPIO0_49, |
| 216 | PINCTRL_GRP_GPIO0_50, |
| 217 | PINCTRL_GRP_GPIO0_51, |
| 218 | PINCTRL_GRP_GPIO0_52, |
| 219 | PINCTRL_GRP_GPIO0_53, |
| 220 | PINCTRL_GRP_GPIO0_54, |
| 221 | PINCTRL_GRP_GPIO0_55, |
| 222 | PINCTRL_GRP_GPIO0_56, |
| 223 | PINCTRL_GRP_GPIO0_57, |
| 224 | PINCTRL_GRP_GPIO0_58, |
| 225 | PINCTRL_GRP_GPIO0_59, |
| 226 | PINCTRL_GRP_GPIO0_60, |
| 227 | PINCTRL_GRP_GPIO0_61, |
| 228 | PINCTRL_GRP_GPIO0_62, |
| 229 | PINCTRL_GRP_GPIO0_63, |
| 230 | PINCTRL_GRP_GPIO0_64, |
| 231 | PINCTRL_GRP_GPIO0_65, |
| 232 | PINCTRL_GRP_GPIO0_66, |
| 233 | PINCTRL_GRP_GPIO0_67, |
| 234 | PINCTRL_GRP_GPIO0_68, |
| 235 | PINCTRL_GRP_GPIO0_69, |
| 236 | PINCTRL_GRP_GPIO0_70, |
| 237 | PINCTRL_GRP_GPIO0_71, |
| 238 | PINCTRL_GRP_GPIO0_72, |
| 239 | PINCTRL_GRP_GPIO0_73, |
| 240 | PINCTRL_GRP_GPIO0_74, |
| 241 | PINCTRL_GRP_GPIO0_75, |
| 242 | PINCTRL_GRP_GPIO0_76, |
| 243 | PINCTRL_GRP_GPIO0_77, |
| 244 | END_OF_GROUPS, |
| 245 | }), |
| 246 | }, |
| 247 | [PINCTRL_FUNC_I2C0] = { |
| 248 | .name = "i2c0", |
| 249 | .regval = 0x40, |
| 250 | .groups = &((uint16_t []) { |
| 251 | PINCTRL_GRP_I2C0_0, |
| 252 | PINCTRL_GRP_I2C0_1, |
| 253 | PINCTRL_GRP_I2C0_2, |
| 254 | PINCTRL_GRP_I2C0_3, |
| 255 | PINCTRL_GRP_I2C0_4, |
| 256 | PINCTRL_GRP_I2C0_5, |
| 257 | PINCTRL_GRP_I2C0_6, |
| 258 | PINCTRL_GRP_I2C0_7, |
| 259 | PINCTRL_GRP_I2C0_8, |
| 260 | PINCTRL_GRP_I2C0_9, |
| 261 | PINCTRL_GRP_I2C0_10, |
| 262 | PINCTRL_GRP_I2C0_11, |
| 263 | PINCTRL_GRP_I2C0_12, |
| 264 | PINCTRL_GRP_I2C0_13, |
| 265 | PINCTRL_GRP_I2C0_14, |
| 266 | PINCTRL_GRP_I2C0_15, |
| 267 | PINCTRL_GRP_I2C0_16, |
| 268 | PINCTRL_GRP_I2C0_17, |
| 269 | PINCTRL_GRP_I2C0_18, |
| 270 | END_OF_GROUPS, |
| 271 | }), |
| 272 | }, |
| 273 | [PINCTRL_FUNC_I2C1] = { |
| 274 | .name = "i2c1", |
| 275 | .regval = 0x40, |
| 276 | .groups = &((uint16_t []) { |
| 277 | PINCTRL_GRP_I2C1_0, |
| 278 | PINCTRL_GRP_I2C1_1, |
| 279 | PINCTRL_GRP_I2C1_2, |
| 280 | PINCTRL_GRP_I2C1_3, |
| 281 | PINCTRL_GRP_I2C1_4, |
| 282 | PINCTRL_GRP_I2C1_5, |
| 283 | PINCTRL_GRP_I2C1_6, |
| 284 | PINCTRL_GRP_I2C1_7, |
| 285 | PINCTRL_GRP_I2C1_8, |
| 286 | PINCTRL_GRP_I2C1_9, |
| 287 | PINCTRL_GRP_I2C1_10, |
| 288 | PINCTRL_GRP_I2C1_11, |
| 289 | PINCTRL_GRP_I2C1_12, |
| 290 | PINCTRL_GRP_I2C1_13, |
| 291 | PINCTRL_GRP_I2C1_14, |
| 292 | PINCTRL_GRP_I2C1_15, |
| 293 | PINCTRL_GRP_I2C1_16, |
| 294 | PINCTRL_GRP_I2C1_17, |
| 295 | PINCTRL_GRP_I2C1_18, |
| 296 | PINCTRL_GRP_I2C1_19, |
| 297 | END_OF_GROUPS, |
| 298 | }), |
| 299 | }, |
| 300 | [PINCTRL_FUNC_MDIO0] = { |
| 301 | .name = "mdio0", |
| 302 | .regval = 0x60, |
| 303 | .groups = &((uint16_t []) { |
| 304 | PINCTRL_GRP_MDIO0_0, |
| 305 | END_OF_GROUPS, |
| 306 | }), |
| 307 | }, |
| 308 | [PINCTRL_FUNC_MDIO1] = { |
| 309 | .name = "mdio1", |
| 310 | .regval = 0x80, |
| 311 | .groups = &((uint16_t []) { |
| 312 | PINCTRL_GRP_MDIO1_0, |
| 313 | PINCTRL_GRP_MDIO1_1, |
| 314 | END_OF_GROUPS, |
| 315 | }), |
| 316 | }, |
| 317 | [PINCTRL_FUNC_MDIO2] = { |
| 318 | .name = "mdio2", |
| 319 | .regval = 0xa0, |
| 320 | .groups = &((uint16_t []) { |
| 321 | PINCTRL_GRP_MDIO2_0, |
| 322 | END_OF_GROUPS, |
| 323 | }), |
| 324 | }, |
| 325 | [PINCTRL_FUNC_MDIO3] = { |
| 326 | .name = "mdio3", |
| 327 | .regval = 0xc0, |
| 328 | .groups = &((uint16_t []) { |
| 329 | PINCTRL_GRP_MDIO3_0, |
| 330 | END_OF_GROUPS, |
| 331 | }), |
| 332 | }, |
| 333 | [PINCTRL_FUNC_QSPI0] = { |
| 334 | .name = "qspi0", |
| 335 | .regval = 0x02, |
| 336 | .groups = &((uint16_t []) { |
| 337 | PINCTRL_GRP_QSPI0_0, |
| 338 | END_OF_GROUPS, |
| 339 | }), |
| 340 | }, |
| 341 | [PINCTRL_FUNC_QSPI_FBCLK] = { |
| 342 | .name = "qspi_fbclk", |
| 343 | .regval = 0x02, |
| 344 | .groups = &((uint16_t []) { |
| 345 | PINCTRL_GRP_QSPI_FBCLK, |
| 346 | END_OF_GROUPS, |
| 347 | }), |
| 348 | }, |
| 349 | [PINCTRL_FUNC_QSPI_SS] = { |
| 350 | .name = "qspi_ss", |
| 351 | .regval = 0x02, |
| 352 | .groups = &((uint16_t []) { |
| 353 | PINCTRL_GRP_QSPI_SS, |
| 354 | END_OF_GROUPS, |
| 355 | }), |
| 356 | }, |
| 357 | [PINCTRL_FUNC_SPI0] = { |
| 358 | .name = "spi0", |
| 359 | .regval = 0x80, |
| 360 | .groups = &((uint16_t []) { |
| 361 | PINCTRL_GRP_SPI0_0, |
| 362 | PINCTRL_GRP_SPI0_1, |
| 363 | PINCTRL_GRP_SPI0_2, |
| 364 | PINCTRL_GRP_SPI0_3, |
| 365 | PINCTRL_GRP_SPI0_4, |
| 366 | PINCTRL_GRP_SPI0_5, |
| 367 | END_OF_GROUPS, |
| 368 | }), |
| 369 | }, |
| 370 | [PINCTRL_FUNC_SPI1] = { |
| 371 | .name = "spi1", |
| 372 | .regval = 0x80, |
| 373 | .groups = &((uint16_t []) { |
| 374 | PINCTRL_GRP_SPI1_0, |
| 375 | PINCTRL_GRP_SPI1_1, |
| 376 | PINCTRL_GRP_SPI1_2, |
| 377 | PINCTRL_GRP_SPI1_3, |
| 378 | PINCTRL_GRP_SPI1_4, |
| 379 | PINCTRL_GRP_SPI1_5, |
| 380 | END_OF_GROUPS, |
| 381 | }), |
| 382 | }, |
| 383 | [PINCTRL_FUNC_SPI0_SS] = { |
| 384 | .name = "spi0_ss", |
| 385 | .regval = 0x80, |
| 386 | .groups = &((uint16_t []) { |
| 387 | PINCTRL_GRP_SPI0_0_SS0, |
| 388 | PINCTRL_GRP_SPI0_0_SS1, |
| 389 | PINCTRL_GRP_SPI0_0_SS2, |
| 390 | PINCTRL_GRP_SPI0_1_SS0, |
| 391 | PINCTRL_GRP_SPI0_1_SS1, |
| 392 | PINCTRL_GRP_SPI0_1_SS2, |
| 393 | PINCTRL_GRP_SPI0_2_SS0, |
| 394 | PINCTRL_GRP_SPI0_2_SS1, |
| 395 | PINCTRL_GRP_SPI0_2_SS2, |
| 396 | PINCTRL_GRP_SPI0_3_SS0, |
| 397 | PINCTRL_GRP_SPI0_3_SS1, |
| 398 | PINCTRL_GRP_SPI0_3_SS2, |
| 399 | PINCTRL_GRP_SPI0_4_SS0, |
| 400 | PINCTRL_GRP_SPI0_4_SS1, |
| 401 | PINCTRL_GRP_SPI0_4_SS2, |
| 402 | PINCTRL_GRP_SPI0_5_SS0, |
| 403 | PINCTRL_GRP_SPI0_5_SS1, |
| 404 | PINCTRL_GRP_SPI0_5_SS2, |
| 405 | END_OF_GROUPS, |
| 406 | }), |
| 407 | }, |
| 408 | [PINCTRL_FUNC_SPI1_SS] = { |
| 409 | .name = "spi1_ss", |
| 410 | .regval = 0x80, |
| 411 | .groups = &((uint16_t []) { |
| 412 | PINCTRL_GRP_SPI1_0_SS0, |
| 413 | PINCTRL_GRP_SPI1_0_SS1, |
| 414 | PINCTRL_GRP_SPI1_0_SS2, |
| 415 | PINCTRL_GRP_SPI1_1_SS0, |
| 416 | PINCTRL_GRP_SPI1_1_SS1, |
| 417 | PINCTRL_GRP_SPI1_1_SS2, |
| 418 | PINCTRL_GRP_SPI1_2_SS0, |
| 419 | PINCTRL_GRP_SPI1_2_SS1, |
| 420 | PINCTRL_GRP_SPI1_2_SS2, |
| 421 | PINCTRL_GRP_SPI1_3_SS0, |
| 422 | PINCTRL_GRP_SPI1_3_SS1, |
| 423 | PINCTRL_GRP_SPI1_3_SS2, |
| 424 | PINCTRL_GRP_SPI1_4_SS0, |
| 425 | PINCTRL_GRP_SPI1_4_SS1, |
| 426 | PINCTRL_GRP_SPI1_4_SS2, |
| 427 | PINCTRL_GRP_SPI1_5_SS0, |
| 428 | PINCTRL_GRP_SPI1_5_SS1, |
| 429 | PINCTRL_GRP_SPI1_5_SS2, |
| 430 | END_OF_GROUPS, |
| 431 | }), |
| 432 | }, |
| 433 | [PINCTRL_FUNC_SDIO0] = { |
| 434 | .name = "sdio0", |
| 435 | .regval = 0x08, |
| 436 | .groups = &((uint16_t []) { |
| 437 | PINCTRL_GRP_SDIO0_0, |
| 438 | PINCTRL_GRP_SDIO0_1, |
| 439 | PINCTRL_GRP_SDIO0_2, |
| 440 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 441 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 442 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 443 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 444 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 445 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 446 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 447 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 448 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 449 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 450 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 451 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 452 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 453 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 454 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 455 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 456 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 457 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 458 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 459 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 460 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 461 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 462 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 463 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 464 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 465 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 466 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 467 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 468 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 469 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 470 | END_OF_GROUPS, |
| 471 | }), |
| 472 | }, |
| 473 | [PINCTRL_FUNC_SDIO0_PC] = { |
| 474 | .name = "sdio0_pc", |
| 475 | .regval = 0x08, |
| 476 | .groups = &((uint16_t []) { |
| 477 | PINCTRL_GRP_SDIO0_0_PC, |
| 478 | PINCTRL_GRP_SDIO0_1_PC, |
| 479 | PINCTRL_GRP_SDIO0_2_PC, |
| 480 | END_OF_GROUPS, |
| 481 | }), |
| 482 | }, |
| 483 | [PINCTRL_FUNC_SDIO0_CD] = { |
| 484 | .name = "sdio0_cd", |
| 485 | .regval = 0x08, |
| 486 | .groups = &((uint16_t []) { |
| 487 | PINCTRL_GRP_SDIO0_0_CD, |
| 488 | PINCTRL_GRP_SDIO0_1_CD, |
| 489 | PINCTRL_GRP_SDIO0_2_CD, |
| 490 | END_OF_GROUPS, |
| 491 | }), |
| 492 | }, |
| 493 | [PINCTRL_FUNC_SDIO0_WP] = { |
| 494 | .name = "sdio0_wp", |
| 495 | .regval = 0x08, |
| 496 | .groups = &((uint16_t []) { |
| 497 | PINCTRL_GRP_SDIO0_0_WP, |
| 498 | PINCTRL_GRP_SDIO0_1_WP, |
| 499 | PINCTRL_GRP_SDIO0_2_WP, |
| 500 | END_OF_GROUPS, |
| 501 | }), |
| 502 | }, |
| 503 | [PINCTRL_FUNC_SDIO1] = { |
| 504 | .name = "sdio1", |
| 505 | .regval = 0x10, |
| 506 | .groups = &((uint16_t []) { |
| 507 | PINCTRL_GRP_SDIO1_0, |
| 508 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 509 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 510 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
| 511 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 512 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 513 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 514 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 515 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 516 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 517 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 518 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 519 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 520 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 521 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 522 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 523 | END_OF_GROUPS, |
| 524 | }), |
| 525 | }, |
| 526 | [PINCTRL_FUNC_SDIO1_PC] = { |
| 527 | .name = "sdio1_pc", |
| 528 | .regval = 0x10, |
| 529 | .groups = &((uint16_t []) { |
| 530 | PINCTRL_GRP_SDIO1_0_PC, |
| 531 | PINCTRL_GRP_SDIO1_1_PC, |
| 532 | END_OF_GROUPS, |
| 533 | }), |
| 534 | }, |
| 535 | [PINCTRL_FUNC_SDIO1_CD] = { |
| 536 | .name = "sdio1_cd", |
| 537 | .regval = 0x10, |
| 538 | .groups = &((uint16_t []) { |
| 539 | PINCTRL_GRP_SDIO1_0_CD, |
| 540 | PINCTRL_GRP_SDIO1_1_CD, |
| 541 | END_OF_GROUPS, |
| 542 | }), |
| 543 | }, |
| 544 | [PINCTRL_FUNC_SDIO1_WP] = { |
| 545 | .name = "sdio1_wp", |
| 546 | .regval = 0x10, |
| 547 | .groups = &((uint16_t []) { |
| 548 | PINCTRL_GRP_SDIO1_0_WP, |
| 549 | PINCTRL_GRP_SDIO1_1_WP, |
| 550 | END_OF_GROUPS, |
| 551 | }), |
| 552 | }, |
| 553 | [PINCTRL_FUNC_NAND0] = { |
| 554 | .name = "nand0", |
| 555 | .regval = 0x04, |
| 556 | .groups = &((uint16_t []) { |
| 557 | PINCTRL_GRP_NAND0_0, |
| 558 | END_OF_GROUPS, |
| 559 | }), |
| 560 | }, |
| 561 | [PINCTRL_FUNC_NAND0_CE] = { |
| 562 | .name = "nand0_ce", |
| 563 | .regval = 0x04, |
| 564 | .groups = &((uint16_t []) { |
| 565 | PINCTRL_GRP_NAND0_0_CE, |
| 566 | PINCTRL_GRP_NAND0_1_CE, |
| 567 | END_OF_GROUPS, |
| 568 | }), |
| 569 | }, |
| 570 | [PINCTRL_FUNC_NAND0_RB] = { |
| 571 | .name = "nand0_rb", |
| 572 | .regval = 0x04, |
| 573 | .groups = &((uint16_t []) { |
| 574 | PINCTRL_GRP_NAND0_0_RB, |
| 575 | PINCTRL_GRP_NAND0_1_RB, |
| 576 | END_OF_GROUPS, |
| 577 | }), |
| 578 | }, |
| 579 | [PINCTRL_FUNC_NAND0_DQS] = { |
| 580 | .name = "nand0_dqs", |
| 581 | .regval = 0x04, |
| 582 | .groups = &((uint16_t []) { |
| 583 | PINCTRL_GRP_NAND0_0_DQS, |
| 584 | PINCTRL_GRP_NAND0_1_DQS, |
| 585 | END_OF_GROUPS, |
| 586 | }), |
| 587 | }, |
| 588 | [PINCTRL_FUNC_TTC0_CLK] = { |
| 589 | .name = "ttc0_clk", |
| 590 | .regval = 0xa0, |
| 591 | .groups = &((uint16_t []) { |
| 592 | PINCTRL_GRP_TTC0_0_CLK, |
| 593 | PINCTRL_GRP_TTC0_1_CLK, |
| 594 | PINCTRL_GRP_TTC0_2_CLK, |
| 595 | PINCTRL_GRP_TTC0_3_CLK, |
| 596 | PINCTRL_GRP_TTC0_4_CLK, |
| 597 | PINCTRL_GRP_TTC0_5_CLK, |
| 598 | PINCTRL_GRP_TTC0_6_CLK, |
| 599 | PINCTRL_GRP_TTC0_7_CLK, |
| 600 | PINCTRL_GRP_TTC0_8_CLK, |
| 601 | END_OF_GROUPS, |
| 602 | }), |
| 603 | }, |
| 604 | [PINCTRL_FUNC_TTC0_WAV] = { |
| 605 | .name = "ttc0_wav", |
| 606 | .regval = 0xa0, |
| 607 | .groups = &((uint16_t []) { |
| 608 | PINCTRL_GRP_TTC0_0_WAV, |
| 609 | PINCTRL_GRP_TTC0_1_WAV, |
| 610 | PINCTRL_GRP_TTC0_2_WAV, |
| 611 | PINCTRL_GRP_TTC0_3_WAV, |
| 612 | PINCTRL_GRP_TTC0_4_WAV, |
| 613 | PINCTRL_GRP_TTC0_5_WAV, |
| 614 | PINCTRL_GRP_TTC0_6_WAV, |
| 615 | PINCTRL_GRP_TTC0_7_WAV, |
| 616 | PINCTRL_GRP_TTC0_8_WAV, |
| 617 | END_OF_GROUPS, |
| 618 | }), |
| 619 | }, |
| 620 | [PINCTRL_FUNC_TTC1_CLK] = { |
| 621 | .name = "ttc1_clk", |
| 622 | .regval = 0xa0, |
| 623 | .groups = &((uint16_t []) { |
| 624 | PINCTRL_GRP_TTC1_0_CLK, |
| 625 | PINCTRL_GRP_TTC1_1_CLK, |
| 626 | PINCTRL_GRP_TTC1_2_CLK, |
| 627 | PINCTRL_GRP_TTC1_3_CLK, |
| 628 | PINCTRL_GRP_TTC1_4_CLK, |
| 629 | PINCTRL_GRP_TTC1_5_CLK, |
| 630 | PINCTRL_GRP_TTC1_6_CLK, |
| 631 | PINCTRL_GRP_TTC1_7_CLK, |
| 632 | PINCTRL_GRP_TTC1_8_CLK, |
| 633 | END_OF_GROUPS, |
| 634 | }), |
| 635 | }, |
| 636 | [PINCTRL_FUNC_TTC1_WAV] = { |
| 637 | .name = "ttc1_wav", |
| 638 | .regval = 0xa0, |
| 639 | .groups = &((uint16_t []) { |
| 640 | PINCTRL_GRP_TTC1_0_WAV, |
| 641 | PINCTRL_GRP_TTC1_1_WAV, |
| 642 | PINCTRL_GRP_TTC1_2_WAV, |
| 643 | PINCTRL_GRP_TTC1_3_WAV, |
| 644 | PINCTRL_GRP_TTC1_4_WAV, |
| 645 | PINCTRL_GRP_TTC1_5_WAV, |
| 646 | PINCTRL_GRP_TTC1_6_WAV, |
| 647 | PINCTRL_GRP_TTC1_7_WAV, |
| 648 | PINCTRL_GRP_TTC1_8_WAV, |
| 649 | END_OF_GROUPS, |
| 650 | }), |
| 651 | }, |
| 652 | [PINCTRL_FUNC_TTC2_CLK] = { |
| 653 | .name = "ttc2_clk", |
| 654 | .regval = 0xa0, |
| 655 | .groups = &((uint16_t []) { |
| 656 | PINCTRL_GRP_TTC2_0_CLK, |
| 657 | PINCTRL_GRP_TTC2_1_CLK, |
| 658 | PINCTRL_GRP_TTC2_2_CLK, |
| 659 | PINCTRL_GRP_TTC2_3_CLK, |
| 660 | PINCTRL_GRP_TTC2_4_CLK, |
| 661 | PINCTRL_GRP_TTC2_5_CLK, |
| 662 | PINCTRL_GRP_TTC2_6_CLK, |
| 663 | PINCTRL_GRP_TTC2_7_CLK, |
| 664 | PINCTRL_GRP_TTC2_8_CLK, |
| 665 | END_OF_GROUPS, |
| 666 | }), |
| 667 | }, |
| 668 | [PINCTRL_FUNC_TTC2_WAV] = { |
| 669 | .name = "ttc2_wav", |
| 670 | .regval = 0xa0, |
| 671 | .groups = &((uint16_t []) { |
| 672 | PINCTRL_GRP_TTC2_0_WAV, |
| 673 | PINCTRL_GRP_TTC2_1_WAV, |
| 674 | PINCTRL_GRP_TTC2_2_WAV, |
| 675 | PINCTRL_GRP_TTC2_3_WAV, |
| 676 | PINCTRL_GRP_TTC2_4_WAV, |
| 677 | PINCTRL_GRP_TTC2_5_WAV, |
| 678 | PINCTRL_GRP_TTC2_6_WAV, |
| 679 | PINCTRL_GRP_TTC2_7_WAV, |
| 680 | PINCTRL_GRP_TTC2_8_WAV, |
| 681 | END_OF_GROUPS, |
| 682 | }), |
| 683 | }, |
| 684 | [PINCTRL_FUNC_TTC3_CLK] = { |
| 685 | .name = "ttc3_clk", |
| 686 | .regval = 0xa0, |
| 687 | .groups = &((uint16_t []) { |
| 688 | PINCTRL_GRP_TTC3_0_CLK, |
| 689 | PINCTRL_GRP_TTC3_1_CLK, |
| 690 | PINCTRL_GRP_TTC3_2_CLK, |
| 691 | PINCTRL_GRP_TTC3_3_CLK, |
| 692 | PINCTRL_GRP_TTC3_4_CLK, |
| 693 | PINCTRL_GRP_TTC3_5_CLK, |
| 694 | PINCTRL_GRP_TTC3_6_CLK, |
| 695 | PINCTRL_GRP_TTC3_7_CLK, |
| 696 | PINCTRL_GRP_TTC3_8_CLK, |
| 697 | END_OF_GROUPS, |
| 698 | }), |
| 699 | }, |
| 700 | [PINCTRL_FUNC_TTC3_WAV] = { |
| 701 | .name = "ttc3_wav", |
| 702 | .regval = 0xa0, |
| 703 | .groups = &((uint16_t []) { |
| 704 | PINCTRL_GRP_TTC3_0_WAV, |
| 705 | PINCTRL_GRP_TTC3_1_WAV, |
| 706 | PINCTRL_GRP_TTC3_2_WAV, |
| 707 | PINCTRL_GRP_TTC3_3_WAV, |
| 708 | PINCTRL_GRP_TTC3_4_WAV, |
| 709 | PINCTRL_GRP_TTC3_5_WAV, |
| 710 | PINCTRL_GRP_TTC3_6_WAV, |
| 711 | PINCTRL_GRP_TTC3_7_WAV, |
| 712 | PINCTRL_GRP_TTC3_8_WAV, |
| 713 | END_OF_GROUPS, |
| 714 | }), |
| 715 | }, |
| 716 | [PINCTRL_FUNC_UART0] = { |
| 717 | .name = "uart0", |
| 718 | .regval = 0xc0, |
| 719 | .groups = &((uint16_t []) { |
| 720 | PINCTRL_GRP_UART0_0, |
| 721 | PINCTRL_GRP_UART0_1, |
| 722 | PINCTRL_GRP_UART0_2, |
| 723 | PINCTRL_GRP_UART0_3, |
| 724 | PINCTRL_GRP_UART0_4, |
| 725 | PINCTRL_GRP_UART0_5, |
| 726 | PINCTRL_GRP_UART0_6, |
| 727 | PINCTRL_GRP_UART0_7, |
| 728 | PINCTRL_GRP_UART0_8, |
| 729 | PINCTRL_GRP_UART0_9, |
| 730 | PINCTRL_GRP_UART0_10, |
| 731 | PINCTRL_GRP_UART0_11, |
| 732 | PINCTRL_GRP_UART0_12, |
| 733 | PINCTRL_GRP_UART0_13, |
| 734 | PINCTRL_GRP_UART0_14, |
| 735 | PINCTRL_GRP_UART0_15, |
| 736 | PINCTRL_GRP_UART0_16, |
| 737 | PINCTRL_GRP_UART0_17, |
| 738 | PINCTRL_GRP_UART0_18, |
| 739 | END_OF_GROUPS, |
| 740 | }), |
| 741 | }, |
| 742 | [PINCTRL_FUNC_UART1] = { |
| 743 | .name = "uart1", |
| 744 | .regval = 0xc0, |
| 745 | .groups = &((uint16_t []) { |
| 746 | PINCTRL_GRP_UART1_0, |
| 747 | PINCTRL_GRP_UART1_1, |
| 748 | PINCTRL_GRP_UART1_2, |
| 749 | PINCTRL_GRP_UART1_3, |
| 750 | PINCTRL_GRP_UART1_4, |
| 751 | PINCTRL_GRP_UART1_5, |
| 752 | PINCTRL_GRP_UART1_6, |
| 753 | PINCTRL_GRP_UART1_7, |
| 754 | PINCTRL_GRP_UART1_8, |
| 755 | PINCTRL_GRP_UART1_9, |
| 756 | PINCTRL_GRP_UART1_10, |
| 757 | PINCTRL_GRP_UART1_11, |
| 758 | PINCTRL_GRP_UART1_12, |
| 759 | PINCTRL_GRP_UART1_13, |
| 760 | PINCTRL_GRP_UART1_14, |
| 761 | PINCTRL_GRP_UART1_15, |
| 762 | PINCTRL_GRP_UART1_16, |
| 763 | PINCTRL_GRP_UART1_17, |
| 764 | PINCTRL_GRP_UART1_18, |
| 765 | END_OF_GROUPS, |
| 766 | }), |
| 767 | }, |
| 768 | [PINCTRL_FUNC_USB0] = { |
| 769 | .name = "usb0", |
| 770 | .regval = 0x04, |
| 771 | .groups = &((uint16_t []) { |
| 772 | PINCTRL_GRP_USB0_0, |
| 773 | END_OF_GROUPS, |
| 774 | }), |
| 775 | }, |
| 776 | [PINCTRL_FUNC_USB1] = { |
| 777 | .name = "usb1", |
| 778 | .regval = 0x04, |
| 779 | .groups = &((uint16_t []) { |
| 780 | PINCTRL_GRP_USB1_0, |
| 781 | END_OF_GROUPS, |
| 782 | }), |
| 783 | }, |
| 784 | [PINCTRL_FUNC_SWDT0_CLK] = { |
| 785 | .name = "swdt0_clk", |
| 786 | .regval = 0x60, |
| 787 | .groups = &((uint16_t []) { |
| 788 | PINCTRL_GRP_SWDT0_0_CLK, |
| 789 | PINCTRL_GRP_SWDT0_1_CLK, |
| 790 | PINCTRL_GRP_SWDT0_2_CLK, |
| 791 | PINCTRL_GRP_SWDT0_3_CLK, |
| 792 | PINCTRL_GRP_SWDT0_4_CLK, |
| 793 | PINCTRL_GRP_SWDT0_5_CLK, |
| 794 | PINCTRL_GRP_SWDT0_6_CLK, |
| 795 | PINCTRL_GRP_SWDT0_7_CLK, |
| 796 | PINCTRL_GRP_SWDT0_8_CLK, |
| 797 | PINCTRL_GRP_SWDT0_9_CLK, |
| 798 | PINCTRL_GRP_SWDT0_10_CLK, |
| 799 | PINCTRL_GRP_SWDT0_11_CLK, |
| 800 | PINCTRL_GRP_SWDT0_12_CLK, |
| 801 | END_OF_GROUPS, |
| 802 | }), |
| 803 | }, |
| 804 | [PINCTRL_FUNC_SWDT0_RST] = { |
| 805 | .name = "swdt0_rst", |
| 806 | .regval = 0x60, |
| 807 | .groups = &((uint16_t []) { |
| 808 | PINCTRL_GRP_SWDT0_0_RST, |
| 809 | PINCTRL_GRP_SWDT0_1_RST, |
| 810 | PINCTRL_GRP_SWDT0_2_RST, |
| 811 | PINCTRL_GRP_SWDT0_3_RST, |
| 812 | PINCTRL_GRP_SWDT0_4_RST, |
| 813 | PINCTRL_GRP_SWDT0_5_RST, |
| 814 | PINCTRL_GRP_SWDT0_6_RST, |
| 815 | PINCTRL_GRP_SWDT0_7_RST, |
| 816 | PINCTRL_GRP_SWDT0_8_RST, |
| 817 | PINCTRL_GRP_SWDT0_9_RST, |
| 818 | PINCTRL_GRP_SWDT0_10_RST, |
| 819 | PINCTRL_GRP_SWDT0_11_RST, |
| 820 | PINCTRL_GRP_SWDT0_12_RST, |
| 821 | END_OF_GROUPS, |
| 822 | }), |
| 823 | }, |
| 824 | [PINCTRL_FUNC_SWDT1_CLK] = { |
| 825 | .name = "swdt1_clk", |
| 826 | .regval = 0x60, |
| 827 | .groups = &((uint16_t []) { |
| 828 | PINCTRL_GRP_SWDT1_0_CLK, |
| 829 | PINCTRL_GRP_SWDT1_1_CLK, |
| 830 | PINCTRL_GRP_SWDT1_2_CLK, |
| 831 | PINCTRL_GRP_SWDT1_3_CLK, |
| 832 | PINCTRL_GRP_SWDT1_4_CLK, |
| 833 | PINCTRL_GRP_SWDT1_5_CLK, |
| 834 | PINCTRL_GRP_SWDT1_6_CLK, |
| 835 | PINCTRL_GRP_SWDT1_7_CLK, |
| 836 | PINCTRL_GRP_SWDT1_8_CLK, |
| 837 | PINCTRL_GRP_SWDT1_9_CLK, |
| 838 | PINCTRL_GRP_SWDT1_10_CLK, |
| 839 | PINCTRL_GRP_SWDT1_11_CLK, |
| 840 | PINCTRL_GRP_SWDT1_12_CLK, |
| 841 | END_OF_GROUPS, |
| 842 | }), |
| 843 | }, |
| 844 | [PINCTRL_FUNC_SWDT1_RST] = { |
| 845 | .name = "swdt1_rst", |
| 846 | .regval = 0x60, |
| 847 | .groups = &((uint16_t []) { |
| 848 | PINCTRL_GRP_SWDT1_0_RST, |
| 849 | PINCTRL_GRP_SWDT1_1_RST, |
| 850 | PINCTRL_GRP_SWDT1_2_RST, |
| 851 | PINCTRL_GRP_SWDT1_3_RST, |
| 852 | PINCTRL_GRP_SWDT1_4_RST, |
| 853 | PINCTRL_GRP_SWDT1_5_RST, |
| 854 | PINCTRL_GRP_SWDT1_6_RST, |
| 855 | PINCTRL_GRP_SWDT1_7_RST, |
| 856 | PINCTRL_GRP_SWDT1_8_RST, |
| 857 | PINCTRL_GRP_SWDT1_9_RST, |
| 858 | PINCTRL_GRP_SWDT1_10_RST, |
| 859 | PINCTRL_GRP_SWDT1_11_RST, |
| 860 | PINCTRL_GRP_SWDT1_12_RST, |
| 861 | END_OF_GROUPS, |
| 862 | }), |
| 863 | }, |
| 864 | [PINCTRL_FUNC_PMU0] = { |
| 865 | .name = "pmu0", |
| 866 | .regval = 0x08, |
| 867 | .groups = &((uint16_t []) { |
| 868 | PINCTRL_GRP_PMU0_0, |
| 869 | PINCTRL_GRP_PMU0_1, |
| 870 | PINCTRL_GRP_PMU0_2, |
| 871 | PINCTRL_GRP_PMU0_3, |
| 872 | PINCTRL_GRP_PMU0_4, |
| 873 | PINCTRL_GRP_PMU0_5, |
| 874 | PINCTRL_GRP_PMU0_6, |
| 875 | PINCTRL_GRP_PMU0_7, |
| 876 | PINCTRL_GRP_PMU0_8, |
| 877 | PINCTRL_GRP_PMU0_9, |
| 878 | PINCTRL_GRP_PMU0_10, |
| 879 | PINCTRL_GRP_PMU0_11, |
| 880 | END_OF_GROUPS, |
| 881 | }), |
| 882 | }, |
| 883 | [PINCTRL_FUNC_PCIE0] = { |
| 884 | .name = "pcie0", |
| 885 | .regval = 0x04, |
| 886 | .groups = &((uint16_t []) { |
| 887 | PINCTRL_GRP_PCIE0_0, |
| 888 | PINCTRL_GRP_PCIE0_1, |
| 889 | PINCTRL_GRP_PCIE0_2, |
| 890 | PINCTRL_GRP_PCIE0_3, |
| 891 | PINCTRL_GRP_PCIE0_4, |
| 892 | PINCTRL_GRP_PCIE0_5, |
| 893 | PINCTRL_GRP_PCIE0_6, |
| 894 | PINCTRL_GRP_PCIE0_7, |
| 895 | END_OF_GROUPS, |
| 896 | }), |
| 897 | }, |
| 898 | [PINCTRL_FUNC_CSU0] = { |
| 899 | .name = "csu0", |
| 900 | .regval = 0x18, |
| 901 | .groups = &((uint16_t []) { |
| 902 | PINCTRL_GRP_CSU0_0, |
| 903 | PINCTRL_GRP_CSU0_1, |
| 904 | PINCTRL_GRP_CSU0_2, |
| 905 | PINCTRL_GRP_CSU0_3, |
| 906 | PINCTRL_GRP_CSU0_4, |
| 907 | PINCTRL_GRP_CSU0_5, |
| 908 | PINCTRL_GRP_CSU0_6, |
| 909 | PINCTRL_GRP_CSU0_7, |
| 910 | PINCTRL_GRP_CSU0_8, |
| 911 | PINCTRL_GRP_CSU0_9, |
| 912 | PINCTRL_GRP_CSU0_10, |
| 913 | PINCTRL_GRP_CSU0_11, |
| 914 | END_OF_GROUPS, |
| 915 | }), |
| 916 | }, |
| 917 | [PINCTRL_FUNC_DPAUX0] = { |
| 918 | .name = "dpaux0", |
| 919 | .regval = 0x18, |
| 920 | .groups = &((uint16_t []) { |
| 921 | PINCTRL_GRP_DPAUX0_0, |
| 922 | PINCTRL_GRP_DPAUX0_1, |
| 923 | PINCTRL_GRP_DPAUX0_2, |
| 924 | PINCTRL_GRP_DPAUX0_3, |
| 925 | END_OF_GROUPS, |
| 926 | }), |
| 927 | }, |
| 928 | [PINCTRL_FUNC_PJTAG0] = { |
| 929 | .name = "pjtag0", |
| 930 | .regval = 0x60, |
| 931 | .groups = &((uint16_t []) { |
| 932 | PINCTRL_GRP_PJTAG0_0, |
| 933 | PINCTRL_GRP_PJTAG0_1, |
| 934 | PINCTRL_GRP_PJTAG0_2, |
| 935 | PINCTRL_GRP_PJTAG0_3, |
| 936 | PINCTRL_GRP_PJTAG0_4, |
| 937 | PINCTRL_GRP_PJTAG0_5, |
| 938 | END_OF_GROUPS, |
| 939 | }), |
| 940 | }, |
| 941 | [PINCTRL_FUNC_TRACE0] = { |
| 942 | .name = "trace0", |
| 943 | .regval = 0xe0, |
| 944 | .groups = &((uint16_t []) { |
| 945 | PINCTRL_GRP_TRACE0_0, |
| 946 | PINCTRL_GRP_TRACE0_1, |
| 947 | PINCTRL_GRP_TRACE0_2, |
| 948 | END_OF_GROUPS, |
| 949 | }), |
| 950 | }, |
| 951 | [PINCTRL_FUNC_TRACE0_CLK] = { |
| 952 | .name = "trace0_clk", |
| 953 | .regval = 0xe0, |
| 954 | .groups = &((uint16_t []) { |
| 955 | PINCTRL_GRP_TRACE0_0_CLK, |
| 956 | PINCTRL_GRP_TRACE0_1_CLK, |
| 957 | PINCTRL_GRP_TRACE0_2_CLK, |
| 958 | END_OF_GROUPS, |
| 959 | }), |
| 960 | }, |
| 961 | [PINCTRL_FUNC_TESTSCAN0] = { |
| 962 | .name = "testscan0", |
| 963 | .regval = 0x10, |
| 964 | .groups = &((uint16_t []) { |
| 965 | PINCTRL_GRP_TESTSCAN0_0, |
| 966 | END_OF_GROUPS, |
| 967 | }), |
| 968 | }, |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 969 | }; |
| 970 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 971 | static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { |
| 972 | [PINCTRL_PIN_0] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 973 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 974 | PINCTRL_GRP_QSPI0_0, |
| 975 | PINCTRL_GRP_RESERVED, |
| 976 | PINCTRL_GRP_RESERVED, |
| 977 | PINCTRL_GRP_TESTSCAN0_0, |
| 978 | PINCTRL_GRP_RESERVED, |
| 979 | PINCTRL_GRP_GPIO0_0, |
| 980 | PINCTRL_GRP_CAN1_0, |
| 981 | PINCTRL_GRP_I2C1_0, |
| 982 | PINCTRL_GRP_PJTAG0_0, |
| 983 | PINCTRL_GRP_SPI0_0, |
| 984 | PINCTRL_GRP_TTC3_0_CLK, |
| 985 | PINCTRL_GRP_UART1_0, |
| 986 | PINCTRL_GRP_TRACE0_0_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 987 | END_OF_GROUPS, |
| 988 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 989 | }, |
| 990 | [PINCTRL_PIN_1] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 991 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 992 | PINCTRL_GRP_QSPI0_0, |
| 993 | PINCTRL_GRP_RESERVED, |
| 994 | PINCTRL_GRP_RESERVED, |
| 995 | PINCTRL_GRP_TESTSCAN0_0, |
| 996 | PINCTRL_GRP_RESERVED, |
| 997 | PINCTRL_GRP_GPIO0_1, |
| 998 | PINCTRL_GRP_CAN1_0, |
| 999 | PINCTRL_GRP_I2C1_0, |
| 1000 | PINCTRL_GRP_PJTAG0_0, |
| 1001 | PINCTRL_GRP_SPI0_0_SS2, |
| 1002 | PINCTRL_GRP_TTC3_0_WAV, |
| 1003 | PINCTRL_GRP_UART1_0, |
| 1004 | PINCTRL_GRP_TRACE0_0_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1005 | END_OF_GROUPS, |
| 1006 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1007 | }, |
| 1008 | [PINCTRL_PIN_2] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1009 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1010 | PINCTRL_GRP_QSPI0_0, |
| 1011 | PINCTRL_GRP_RESERVED, |
| 1012 | PINCTRL_GRP_RESERVED, |
| 1013 | PINCTRL_GRP_TESTSCAN0_0, |
| 1014 | PINCTRL_GRP_RESERVED, |
| 1015 | PINCTRL_GRP_GPIO0_2, |
| 1016 | PINCTRL_GRP_CAN0_0, |
| 1017 | PINCTRL_GRP_I2C0_0, |
| 1018 | PINCTRL_GRP_PJTAG0_0, |
| 1019 | PINCTRL_GRP_SPI0_0_SS1, |
| 1020 | PINCTRL_GRP_TTC2_0_CLK, |
| 1021 | PINCTRL_GRP_UART0_0, |
| 1022 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1023 | END_OF_GROUPS, |
| 1024 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1025 | }, |
| 1026 | [PINCTRL_PIN_3] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1027 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1028 | PINCTRL_GRP_QSPI0_0, |
| 1029 | PINCTRL_GRP_RESERVED, |
| 1030 | PINCTRL_GRP_RESERVED, |
| 1031 | PINCTRL_GRP_TESTSCAN0_0, |
| 1032 | PINCTRL_GRP_RESERVED, |
| 1033 | PINCTRL_GRP_GPIO0_3, |
| 1034 | PINCTRL_GRP_CAN0_0, |
| 1035 | PINCTRL_GRP_I2C0_0, |
| 1036 | PINCTRL_GRP_PJTAG0_0, |
| 1037 | PINCTRL_GRP_SPI0_0_SS0, |
| 1038 | PINCTRL_GRP_TTC2_0_WAV, |
| 1039 | PINCTRL_GRP_UART0_0, |
| 1040 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1041 | END_OF_GROUPS, |
| 1042 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1043 | }, |
| 1044 | [PINCTRL_PIN_4] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1045 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1046 | PINCTRL_GRP_QSPI0_0, |
| 1047 | PINCTRL_GRP_RESERVED, |
| 1048 | PINCTRL_GRP_RESERVED, |
| 1049 | PINCTRL_GRP_TESTSCAN0_0, |
| 1050 | PINCTRL_GRP_RESERVED, |
| 1051 | PINCTRL_GRP_GPIO0_4, |
| 1052 | PINCTRL_GRP_CAN1_1, |
| 1053 | PINCTRL_GRP_I2C1_1, |
| 1054 | PINCTRL_GRP_SWDT1_0_CLK, |
| 1055 | PINCTRL_GRP_SPI0_0, |
| 1056 | PINCTRL_GRP_TTC1_0_CLK, |
| 1057 | PINCTRL_GRP_UART1_1, |
| 1058 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1059 | END_OF_GROUPS, |
| 1060 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1061 | }, |
| 1062 | [PINCTRL_PIN_5] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1063 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1064 | PINCTRL_GRP_QSPI_SS, |
| 1065 | PINCTRL_GRP_RESERVED, |
| 1066 | PINCTRL_GRP_RESERVED, |
| 1067 | PINCTRL_GRP_TESTSCAN0_0, |
| 1068 | PINCTRL_GRP_RESERVED, |
| 1069 | PINCTRL_GRP_GPIO0_5, |
| 1070 | PINCTRL_GRP_CAN1_1, |
| 1071 | PINCTRL_GRP_I2C1_1, |
| 1072 | PINCTRL_GRP_SWDT1_0_RST, |
| 1073 | PINCTRL_GRP_SPI0_0, |
| 1074 | PINCTRL_GRP_TTC1_0_WAV, |
| 1075 | PINCTRL_GRP_UART1_1, |
| 1076 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1077 | END_OF_GROUPS, |
| 1078 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1079 | }, |
| 1080 | [PINCTRL_PIN_6] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1081 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1082 | PINCTRL_GRP_QSPI_FBCLK, |
| 1083 | PINCTRL_GRP_RESERVED, |
| 1084 | PINCTRL_GRP_RESERVED, |
| 1085 | PINCTRL_GRP_TESTSCAN0_0, |
| 1086 | PINCTRL_GRP_RESERVED, |
| 1087 | PINCTRL_GRP_GPIO0_6, |
| 1088 | PINCTRL_GRP_CAN0_1, |
| 1089 | PINCTRL_GRP_I2C0_1, |
| 1090 | PINCTRL_GRP_SWDT0_0_CLK, |
| 1091 | PINCTRL_GRP_SPI1_0, |
| 1092 | PINCTRL_GRP_TTC0_0_CLK, |
| 1093 | PINCTRL_GRP_UART0_1, |
| 1094 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1095 | END_OF_GROUPS, |
| 1096 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1097 | }, |
| 1098 | [PINCTRL_PIN_7] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1099 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1100 | PINCTRL_GRP_QSPI_SS, |
| 1101 | PINCTRL_GRP_RESERVED, |
| 1102 | PINCTRL_GRP_RESERVED, |
| 1103 | PINCTRL_GRP_TESTSCAN0_0, |
| 1104 | PINCTRL_GRP_RESERVED, |
| 1105 | PINCTRL_GRP_GPIO0_7, |
| 1106 | PINCTRL_GRP_CAN0_1, |
| 1107 | PINCTRL_GRP_I2C0_1, |
| 1108 | PINCTRL_GRP_SWDT0_0_RST, |
| 1109 | PINCTRL_GRP_SPI1_0_SS2, |
| 1110 | PINCTRL_GRP_TTC0_0_WAV, |
| 1111 | PINCTRL_GRP_UART0_1, |
| 1112 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1113 | END_OF_GROUPS, |
| 1114 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1115 | }, |
| 1116 | [PINCTRL_PIN_8] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1117 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1118 | PINCTRL_GRP_QSPI0_0, |
| 1119 | PINCTRL_GRP_RESERVED, |
| 1120 | PINCTRL_GRP_RESERVED, |
| 1121 | PINCTRL_GRP_TESTSCAN0_0, |
| 1122 | PINCTRL_GRP_RESERVED, |
| 1123 | PINCTRL_GRP_GPIO0_8, |
| 1124 | PINCTRL_GRP_CAN1_2, |
| 1125 | PINCTRL_GRP_I2C1_2, |
| 1126 | PINCTRL_GRP_SWDT1_1_CLK, |
| 1127 | PINCTRL_GRP_SPI1_0_SS1, |
| 1128 | PINCTRL_GRP_TTC3_1_CLK, |
| 1129 | PINCTRL_GRP_UART1_2, |
| 1130 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1131 | END_OF_GROUPS, |
| 1132 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1133 | }, |
| 1134 | [PINCTRL_PIN_9] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1135 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1136 | PINCTRL_GRP_QSPI0_0, |
| 1137 | PINCTRL_GRP_NAND0_0_CE, |
| 1138 | PINCTRL_GRP_RESERVED, |
| 1139 | PINCTRL_GRP_TESTSCAN0_0, |
| 1140 | PINCTRL_GRP_RESERVED, |
| 1141 | PINCTRL_GRP_GPIO0_9, |
| 1142 | PINCTRL_GRP_CAN1_2, |
| 1143 | PINCTRL_GRP_I2C1_2, |
| 1144 | PINCTRL_GRP_SWDT1_1_RST, |
| 1145 | PINCTRL_GRP_SPI1_0_SS0, |
| 1146 | PINCTRL_GRP_TTC3_1_WAV, |
| 1147 | PINCTRL_GRP_UART1_2, |
| 1148 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1149 | END_OF_GROUPS, |
| 1150 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1151 | }, |
| 1152 | [PINCTRL_PIN_10] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1153 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1154 | PINCTRL_GRP_QSPI0_0, |
| 1155 | PINCTRL_GRP_NAND0_0_RB, |
| 1156 | PINCTRL_GRP_RESERVED, |
| 1157 | PINCTRL_GRP_TESTSCAN0_0, |
| 1158 | PINCTRL_GRP_RESERVED, |
| 1159 | PINCTRL_GRP_GPIO0_10, |
| 1160 | PINCTRL_GRP_CAN0_2, |
| 1161 | PINCTRL_GRP_I2C0_2, |
| 1162 | PINCTRL_GRP_SWDT0_1_CLK, |
| 1163 | PINCTRL_GRP_SPI1_0, |
| 1164 | PINCTRL_GRP_TTC2_1_CLK, |
| 1165 | PINCTRL_GRP_UART0_2, |
| 1166 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1167 | END_OF_GROUPS, |
| 1168 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1169 | }, |
| 1170 | [PINCTRL_PIN_11] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1171 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1172 | PINCTRL_GRP_QSPI0_0, |
| 1173 | PINCTRL_GRP_NAND0_0_RB, |
| 1174 | PINCTRL_GRP_RESERVED, |
| 1175 | PINCTRL_GRP_TESTSCAN0_0, |
| 1176 | PINCTRL_GRP_RESERVED, |
| 1177 | PINCTRL_GRP_GPIO0_11, |
| 1178 | PINCTRL_GRP_CAN0_2, |
| 1179 | PINCTRL_GRP_I2C0_2, |
| 1180 | PINCTRL_GRP_SWDT0_1_RST, |
| 1181 | PINCTRL_GRP_SPI1_0, |
| 1182 | PINCTRL_GRP_TTC2_1_WAV, |
| 1183 | PINCTRL_GRP_UART0_2, |
| 1184 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1185 | END_OF_GROUPS, |
| 1186 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1187 | }, |
| 1188 | [PINCTRL_PIN_12] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1189 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1190 | PINCTRL_GRP_QSPI0_0, |
| 1191 | PINCTRL_GRP_NAND0_0_DQS, |
| 1192 | PINCTRL_GRP_RESERVED, |
| 1193 | PINCTRL_GRP_TESTSCAN0_0, |
| 1194 | PINCTRL_GRP_RESERVED, |
| 1195 | PINCTRL_GRP_GPIO0_12, |
| 1196 | PINCTRL_GRP_CAN1_3, |
| 1197 | PINCTRL_GRP_I2C1_3, |
| 1198 | PINCTRL_GRP_PJTAG0_1, |
| 1199 | PINCTRL_GRP_SPI0_1, |
| 1200 | PINCTRL_GRP_TTC1_1_CLK, |
| 1201 | PINCTRL_GRP_UART1_3, |
| 1202 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1203 | END_OF_GROUPS, |
| 1204 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1205 | }, |
| 1206 | [PINCTRL_PIN_13] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1207 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1208 | PINCTRL_GRP_RESERVED, |
| 1209 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1210 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1211 | PINCTRL_GRP_TESTSCAN0_0, |
| 1212 | PINCTRL_GRP_RESERVED, |
| 1213 | PINCTRL_GRP_GPIO0_13, |
| 1214 | PINCTRL_GRP_CAN1_3, |
| 1215 | PINCTRL_GRP_I2C1_3, |
| 1216 | PINCTRL_GRP_PJTAG0_1, |
| 1217 | PINCTRL_GRP_SPI0_1_SS2, |
| 1218 | PINCTRL_GRP_TTC1_1_WAV, |
| 1219 | PINCTRL_GRP_UART1_3, |
| 1220 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1221 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1222 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 1223 | END_OF_GROUPS, |
| 1224 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1225 | }, |
| 1226 | [PINCTRL_PIN_14] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1227 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1228 | PINCTRL_GRP_RESERVED, |
| 1229 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1230 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1231 | PINCTRL_GRP_TESTSCAN0_0, |
| 1232 | PINCTRL_GRP_RESERVED, |
| 1233 | PINCTRL_GRP_GPIO0_14, |
| 1234 | PINCTRL_GRP_CAN0_3, |
| 1235 | PINCTRL_GRP_I2C0_3, |
| 1236 | PINCTRL_GRP_PJTAG0_1, |
| 1237 | PINCTRL_GRP_SPI0_1_SS1, |
| 1238 | PINCTRL_GRP_TTC0_1_CLK, |
| 1239 | PINCTRL_GRP_UART0_3, |
| 1240 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1241 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1242 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 1243 | END_OF_GROUPS, |
| 1244 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1245 | }, |
| 1246 | [PINCTRL_PIN_15] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1247 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1248 | PINCTRL_GRP_RESERVED, |
| 1249 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1250 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1251 | PINCTRL_GRP_TESTSCAN0_0, |
| 1252 | PINCTRL_GRP_RESERVED, |
| 1253 | PINCTRL_GRP_GPIO0_15, |
| 1254 | PINCTRL_GRP_CAN0_3, |
| 1255 | PINCTRL_GRP_I2C0_3, |
| 1256 | PINCTRL_GRP_PJTAG0_1, |
| 1257 | PINCTRL_GRP_SPI0_1_SS0, |
| 1258 | PINCTRL_GRP_TTC0_1_WAV, |
| 1259 | PINCTRL_GRP_UART0_3, |
| 1260 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1261 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1262 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 1263 | END_OF_GROUPS, |
| 1264 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1265 | }, |
| 1266 | [PINCTRL_PIN_16] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1267 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1268 | PINCTRL_GRP_RESERVED, |
| 1269 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1270 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1271 | PINCTRL_GRP_TESTSCAN0_0, |
| 1272 | PINCTRL_GRP_RESERVED, |
| 1273 | PINCTRL_GRP_GPIO0_16, |
| 1274 | PINCTRL_GRP_CAN1_4, |
| 1275 | PINCTRL_GRP_I2C1_4, |
| 1276 | PINCTRL_GRP_SWDT1_2_CLK, |
| 1277 | PINCTRL_GRP_SPI0_1, |
| 1278 | PINCTRL_GRP_TTC3_2_CLK, |
| 1279 | PINCTRL_GRP_UART1_4, |
| 1280 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1281 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1282 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 1283 | END_OF_GROUPS, |
| 1284 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1285 | }, |
| 1286 | [PINCTRL_PIN_17] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1287 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1288 | PINCTRL_GRP_RESERVED, |
| 1289 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1290 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1291 | PINCTRL_GRP_TESTSCAN0_0, |
| 1292 | PINCTRL_GRP_RESERVED, |
| 1293 | PINCTRL_GRP_GPIO0_17, |
| 1294 | PINCTRL_GRP_CAN1_4, |
| 1295 | PINCTRL_GRP_I2C1_4, |
| 1296 | PINCTRL_GRP_SWDT1_2_RST, |
| 1297 | PINCTRL_GRP_SPI0_1, |
| 1298 | PINCTRL_GRP_TTC3_2_WAV, |
| 1299 | PINCTRL_GRP_UART1_4, |
| 1300 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1301 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1302 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 1303 | END_OF_GROUPS, |
| 1304 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1305 | }, |
| 1306 | [PINCTRL_PIN_18] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1307 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1308 | PINCTRL_GRP_RESERVED, |
| 1309 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1310 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1311 | PINCTRL_GRP_TESTSCAN0_0, |
| 1312 | PINCTRL_GRP_CSU0_0, |
| 1313 | PINCTRL_GRP_GPIO0_18, |
| 1314 | PINCTRL_GRP_CAN0_4, |
| 1315 | PINCTRL_GRP_I2C0_4, |
| 1316 | PINCTRL_GRP_SWDT0_2_CLK, |
| 1317 | PINCTRL_GRP_SPI1_1, |
| 1318 | PINCTRL_GRP_TTC2_2_CLK, |
| 1319 | PINCTRL_GRP_UART0_4, |
| 1320 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1321 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1322 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 1323 | END_OF_GROUPS, |
| 1324 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1325 | }, |
| 1326 | [PINCTRL_PIN_19] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1327 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1328 | PINCTRL_GRP_RESERVED, |
| 1329 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1330 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1331 | PINCTRL_GRP_TESTSCAN0_0, |
| 1332 | PINCTRL_GRP_CSU0_1, |
| 1333 | PINCTRL_GRP_GPIO0_19, |
| 1334 | PINCTRL_GRP_CAN0_4, |
| 1335 | PINCTRL_GRP_I2C0_4, |
| 1336 | PINCTRL_GRP_SWDT0_2_RST, |
| 1337 | PINCTRL_GRP_SPI1_1_SS2, |
| 1338 | PINCTRL_GRP_TTC2_2_WAV, |
| 1339 | PINCTRL_GRP_UART0_4, |
| 1340 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1341 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1342 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 1343 | END_OF_GROUPS, |
| 1344 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1345 | }, |
| 1346 | [PINCTRL_PIN_20] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1347 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1348 | PINCTRL_GRP_RESERVED, |
| 1349 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1350 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1351 | PINCTRL_GRP_TESTSCAN0_0, |
| 1352 | PINCTRL_GRP_CSU0_2, |
| 1353 | PINCTRL_GRP_GPIO0_20, |
| 1354 | PINCTRL_GRP_CAN1_5, |
| 1355 | PINCTRL_GRP_I2C1_5, |
| 1356 | PINCTRL_GRP_SWDT1_3_CLK, |
| 1357 | PINCTRL_GRP_SPI1_1_SS1, |
| 1358 | PINCTRL_GRP_TTC1_2_CLK, |
| 1359 | PINCTRL_GRP_UART1_5, |
| 1360 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1361 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1362 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 1363 | END_OF_GROUPS, |
| 1364 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1365 | }, |
| 1366 | [PINCTRL_PIN_21] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1367 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1368 | PINCTRL_GRP_RESERVED, |
| 1369 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1370 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1371 | PINCTRL_GRP_TESTSCAN0_0, |
| 1372 | PINCTRL_GRP_CSU0_3, |
| 1373 | PINCTRL_GRP_GPIO0_21, |
| 1374 | PINCTRL_GRP_CAN1_5, |
| 1375 | PINCTRL_GRP_I2C1_5, |
| 1376 | PINCTRL_GRP_SWDT1_3_RST, |
| 1377 | PINCTRL_GRP_SPI1_1_SS0, |
| 1378 | PINCTRL_GRP_TTC1_2_WAV, |
| 1379 | PINCTRL_GRP_UART1_5, |
| 1380 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1381 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1382 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1383 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 1384 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 1385 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 1386 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 1387 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 1388 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 1389 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 1390 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 1391 | END_OF_GROUPS, |
| 1392 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1393 | }, |
| 1394 | [PINCTRL_PIN_22] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1395 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1396 | PINCTRL_GRP_RESERVED, |
| 1397 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1398 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1399 | PINCTRL_GRP_TESTSCAN0_0, |
| 1400 | PINCTRL_GRP_CSU0_4, |
| 1401 | PINCTRL_GRP_GPIO0_22, |
| 1402 | PINCTRL_GRP_CAN0_5, |
| 1403 | PINCTRL_GRP_I2C0_5, |
| 1404 | PINCTRL_GRP_SWDT0_3_CLK, |
| 1405 | PINCTRL_GRP_SPI1_1, |
| 1406 | PINCTRL_GRP_TTC0_2_CLK, |
| 1407 | PINCTRL_GRP_UART0_5, |
| 1408 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1409 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 1410 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 1411 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 1412 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 1413 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 1414 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 1415 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 1416 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 1417 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 1418 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 1419 | END_OF_GROUPS, |
| 1420 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1421 | }, |
| 1422 | [PINCTRL_PIN_23] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1423 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1424 | PINCTRL_GRP_RESERVED, |
| 1425 | PINCTRL_GRP_NAND0_0, |
| 1426 | PINCTRL_GRP_SDIO0_0_PC, |
| 1427 | PINCTRL_GRP_TESTSCAN0_0, |
| 1428 | PINCTRL_GRP_CSU0_5, |
| 1429 | PINCTRL_GRP_GPIO0_23, |
| 1430 | PINCTRL_GRP_CAN0_5, |
| 1431 | PINCTRL_GRP_I2C0_5, |
| 1432 | PINCTRL_GRP_SWDT0_3_RST, |
| 1433 | PINCTRL_GRP_SPI1_1, |
| 1434 | PINCTRL_GRP_TTC0_2_WAV, |
| 1435 | PINCTRL_GRP_UART0_5, |
| 1436 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1437 | END_OF_GROUPS, |
| 1438 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1439 | }, |
| 1440 | [PINCTRL_PIN_24] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1441 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1442 | PINCTRL_GRP_RESERVED, |
| 1443 | PINCTRL_GRP_NAND0_0, |
| 1444 | PINCTRL_GRP_SDIO0_0_CD, |
| 1445 | PINCTRL_GRP_TESTSCAN0_0, |
| 1446 | PINCTRL_GRP_CSU0_6, |
| 1447 | PINCTRL_GRP_GPIO0_24, |
| 1448 | PINCTRL_GRP_CAN1_6, |
| 1449 | PINCTRL_GRP_I2C1_6, |
| 1450 | PINCTRL_GRP_SWDT1_4_CLK, |
| 1451 | PINCTRL_GRP_RESERVED, |
| 1452 | PINCTRL_GRP_TTC3_3_CLK, |
| 1453 | PINCTRL_GRP_UART1_6, |
| 1454 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1455 | END_OF_GROUPS, |
| 1456 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1457 | }, |
| 1458 | [PINCTRL_PIN_25] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1459 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1460 | PINCTRL_GRP_RESERVED, |
| 1461 | PINCTRL_GRP_NAND0_0, |
| 1462 | PINCTRL_GRP_SDIO0_0_WP, |
| 1463 | PINCTRL_GRP_TESTSCAN0_0, |
| 1464 | PINCTRL_GRP_CSU0_7, |
| 1465 | PINCTRL_GRP_GPIO0_25, |
| 1466 | PINCTRL_GRP_CAN1_6, |
| 1467 | PINCTRL_GRP_I2C1_6, |
| 1468 | PINCTRL_GRP_SWDT1_4_RST, |
| 1469 | PINCTRL_GRP_RESERVED, |
| 1470 | PINCTRL_GRP_TTC3_3_WAV, |
| 1471 | PINCTRL_GRP_UART1_6, |
| 1472 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1473 | END_OF_GROUPS, |
| 1474 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1475 | }, |
| 1476 | [PINCTRL_PIN_26] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1477 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1478 | PINCTRL_GRP_GEMTSU0_0, |
| 1479 | PINCTRL_GRP_NAND0_1_CE, |
| 1480 | PINCTRL_GRP_PMU0_0, |
| 1481 | PINCTRL_GRP_TESTSCAN0_0, |
| 1482 | PINCTRL_GRP_CSU0_8, |
| 1483 | PINCTRL_GRP_GPIO0_26, |
| 1484 | PINCTRL_GRP_CAN0_6, |
| 1485 | PINCTRL_GRP_I2C0_6, |
| 1486 | PINCTRL_GRP_PJTAG0_2, |
| 1487 | PINCTRL_GRP_SPI0_2, |
| 1488 | PINCTRL_GRP_TTC2_3_CLK, |
| 1489 | PINCTRL_GRP_UART0_6, |
| 1490 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1491 | END_OF_GROUPS, |
| 1492 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1493 | }, |
| 1494 | [PINCTRL_PIN_27] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1495 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1496 | PINCTRL_GRP_ETHERNET0_0, |
| 1497 | PINCTRL_GRP_NAND0_1_RB, |
| 1498 | PINCTRL_GRP_PMU0_1, |
| 1499 | PINCTRL_GRP_TESTSCAN0_0, |
| 1500 | PINCTRL_GRP_DPAUX0_0, |
| 1501 | PINCTRL_GRP_GPIO0_27, |
| 1502 | PINCTRL_GRP_CAN0_6, |
| 1503 | PINCTRL_GRP_I2C0_6, |
| 1504 | PINCTRL_GRP_PJTAG0_2, |
| 1505 | PINCTRL_GRP_SPI0_2_SS2, |
| 1506 | PINCTRL_GRP_TTC2_3_WAV, |
| 1507 | PINCTRL_GRP_UART0_6, |
| 1508 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1509 | END_OF_GROUPS, |
| 1510 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1511 | }, |
| 1512 | [PINCTRL_PIN_28] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1513 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1514 | PINCTRL_GRP_ETHERNET0_0, |
| 1515 | PINCTRL_GRP_NAND0_1_RB, |
| 1516 | PINCTRL_GRP_PMU0_2, |
| 1517 | PINCTRL_GRP_TESTSCAN0_0, |
| 1518 | PINCTRL_GRP_DPAUX0_0, |
| 1519 | PINCTRL_GRP_GPIO0_28, |
| 1520 | PINCTRL_GRP_CAN1_7, |
| 1521 | PINCTRL_GRP_I2C1_7, |
| 1522 | PINCTRL_GRP_PJTAG0_2, |
| 1523 | PINCTRL_GRP_SPI0_2_SS1, |
| 1524 | PINCTRL_GRP_TTC1_3_CLK, |
| 1525 | PINCTRL_GRP_UART1_7, |
| 1526 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1527 | END_OF_GROUPS, |
| 1528 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1529 | }, |
| 1530 | [PINCTRL_PIN_29] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1531 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1532 | PINCTRL_GRP_ETHERNET0_0, |
| 1533 | PINCTRL_GRP_PCIE0_0, |
| 1534 | PINCTRL_GRP_PMU0_3, |
| 1535 | PINCTRL_GRP_TESTSCAN0_0, |
| 1536 | PINCTRL_GRP_DPAUX0_1, |
| 1537 | PINCTRL_GRP_GPIO0_29, |
| 1538 | PINCTRL_GRP_CAN1_7, |
| 1539 | PINCTRL_GRP_I2C1_7, |
| 1540 | PINCTRL_GRP_PJTAG0_2, |
| 1541 | PINCTRL_GRP_SPI0_2_SS0, |
| 1542 | PINCTRL_GRP_TTC1_3_WAV, |
| 1543 | PINCTRL_GRP_UART1_7, |
| 1544 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1545 | END_OF_GROUPS, |
| 1546 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1547 | }, |
| 1548 | [PINCTRL_PIN_30] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1549 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1550 | PINCTRL_GRP_ETHERNET0_0, |
| 1551 | PINCTRL_GRP_PCIE0_1, |
| 1552 | PINCTRL_GRP_PMU0_4, |
| 1553 | PINCTRL_GRP_TESTSCAN0_0, |
| 1554 | PINCTRL_GRP_DPAUX0_1, |
| 1555 | PINCTRL_GRP_GPIO0_30, |
| 1556 | PINCTRL_GRP_CAN0_7, |
| 1557 | PINCTRL_GRP_I2C0_7, |
| 1558 | PINCTRL_GRP_SWDT0_4_CLK, |
| 1559 | PINCTRL_GRP_SPI0_2, |
| 1560 | PINCTRL_GRP_TTC0_3_CLK, |
| 1561 | PINCTRL_GRP_UART0_7, |
| 1562 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1563 | END_OF_GROUPS, |
| 1564 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1565 | }, |
| 1566 | [PINCTRL_PIN_31] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1567 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1568 | PINCTRL_GRP_ETHERNET0_0, |
| 1569 | PINCTRL_GRP_PCIE0_2, |
| 1570 | PINCTRL_GRP_PMU0_5, |
| 1571 | PINCTRL_GRP_TESTSCAN0_0, |
| 1572 | PINCTRL_GRP_CSU0_9, |
| 1573 | PINCTRL_GRP_GPIO0_31, |
| 1574 | PINCTRL_GRP_CAN0_7, |
| 1575 | PINCTRL_GRP_I2C0_7, |
| 1576 | PINCTRL_GRP_SWDT0_4_RST, |
| 1577 | PINCTRL_GRP_SPI0_2, |
| 1578 | PINCTRL_GRP_TTC0_3_WAV, |
| 1579 | PINCTRL_GRP_UART0_7, |
| 1580 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1581 | END_OF_GROUPS, |
| 1582 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1583 | }, |
| 1584 | [PINCTRL_PIN_32] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1585 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1586 | PINCTRL_GRP_ETHERNET0_0, |
| 1587 | PINCTRL_GRP_NAND0_1_DQS, |
| 1588 | PINCTRL_GRP_PMU0_6, |
| 1589 | PINCTRL_GRP_TESTSCAN0_0, |
| 1590 | PINCTRL_GRP_CSU0_10, |
| 1591 | PINCTRL_GRP_GPIO0_32, |
| 1592 | PINCTRL_GRP_CAN1_8, |
| 1593 | PINCTRL_GRP_I2C1_8, |
| 1594 | PINCTRL_GRP_SWDT1_5_CLK, |
| 1595 | PINCTRL_GRP_SPI1_2, |
| 1596 | PINCTRL_GRP_TTC3_4_CLK, |
| 1597 | PINCTRL_GRP_UART1_8, |
| 1598 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1599 | END_OF_GROUPS, |
| 1600 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1601 | }, |
| 1602 | [PINCTRL_PIN_33] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1603 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1604 | PINCTRL_GRP_ETHERNET0_0, |
| 1605 | PINCTRL_GRP_PCIE0_3, |
| 1606 | PINCTRL_GRP_PMU0_7, |
| 1607 | PINCTRL_GRP_TESTSCAN0_0, |
| 1608 | PINCTRL_GRP_CSU0_11, |
| 1609 | PINCTRL_GRP_GPIO0_33, |
| 1610 | PINCTRL_GRP_CAN1_8, |
| 1611 | PINCTRL_GRP_I2C1_8, |
| 1612 | PINCTRL_GRP_SWDT1_5_RST, |
| 1613 | PINCTRL_GRP_SPI1_2_SS2, |
| 1614 | PINCTRL_GRP_TTC3_4_WAV, |
| 1615 | PINCTRL_GRP_UART1_8, |
| 1616 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1617 | END_OF_GROUPS, |
| 1618 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1619 | }, |
| 1620 | [PINCTRL_PIN_34] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1621 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1622 | PINCTRL_GRP_ETHERNET0_0, |
| 1623 | PINCTRL_GRP_PCIE0_4, |
| 1624 | PINCTRL_GRP_PMU0_8, |
| 1625 | PINCTRL_GRP_TESTSCAN0_0, |
| 1626 | PINCTRL_GRP_DPAUX0_2, |
| 1627 | PINCTRL_GRP_GPIO0_34, |
| 1628 | PINCTRL_GRP_CAN0_8, |
| 1629 | PINCTRL_GRP_I2C0_8, |
| 1630 | PINCTRL_GRP_SWDT0_5_CLK, |
| 1631 | PINCTRL_GRP_SPI1_2_SS1, |
| 1632 | PINCTRL_GRP_TTC2_4_CLK, |
| 1633 | PINCTRL_GRP_UART0_8, |
| 1634 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1635 | END_OF_GROUPS, |
| 1636 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1637 | }, |
| 1638 | [PINCTRL_PIN_35] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1639 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1640 | PINCTRL_GRP_ETHERNET0_0, |
| 1641 | PINCTRL_GRP_PCIE0_5, |
| 1642 | PINCTRL_GRP_PMU0_9, |
| 1643 | PINCTRL_GRP_TESTSCAN0_0, |
| 1644 | PINCTRL_GRP_DPAUX0_2, |
| 1645 | PINCTRL_GRP_GPIO0_35, |
| 1646 | PINCTRL_GRP_CAN0_8, |
| 1647 | PINCTRL_GRP_I2C0_8, |
| 1648 | PINCTRL_GRP_SWDT0_5_RST, |
| 1649 | PINCTRL_GRP_SPI1_2_SS0, |
| 1650 | PINCTRL_GRP_TTC2_4_WAV, |
| 1651 | PINCTRL_GRP_UART0_8, |
| 1652 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1653 | END_OF_GROUPS, |
| 1654 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1655 | }, |
| 1656 | [PINCTRL_PIN_36] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1657 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1658 | PINCTRL_GRP_ETHERNET0_0, |
| 1659 | PINCTRL_GRP_PCIE0_6, |
| 1660 | PINCTRL_GRP_PMU0_10, |
| 1661 | PINCTRL_GRP_TESTSCAN0_0, |
| 1662 | PINCTRL_GRP_DPAUX0_3, |
| 1663 | PINCTRL_GRP_GPIO0_36, |
| 1664 | PINCTRL_GRP_CAN1_9, |
| 1665 | PINCTRL_GRP_I2C1_9, |
| 1666 | PINCTRL_GRP_SWDT1_6_CLK, |
| 1667 | PINCTRL_GRP_SPI1_2, |
| 1668 | PINCTRL_GRP_TTC1_4_CLK, |
| 1669 | PINCTRL_GRP_UART1_9, |
| 1670 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1671 | END_OF_GROUPS, |
| 1672 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1673 | }, |
| 1674 | [PINCTRL_PIN_37] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1675 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1676 | PINCTRL_GRP_ETHERNET0_0, |
| 1677 | PINCTRL_GRP_PCIE0_7, |
| 1678 | PINCTRL_GRP_PMU0_11, |
| 1679 | PINCTRL_GRP_TESTSCAN0_0, |
| 1680 | PINCTRL_GRP_DPAUX0_3, |
| 1681 | PINCTRL_GRP_GPIO0_37, |
| 1682 | PINCTRL_GRP_CAN1_9, |
| 1683 | PINCTRL_GRP_I2C1_9, |
| 1684 | PINCTRL_GRP_SWDT1_6_RST, |
| 1685 | PINCTRL_GRP_SPI1_2, |
| 1686 | PINCTRL_GRP_TTC1_4_WAV, |
| 1687 | PINCTRL_GRP_UART1_9, |
| 1688 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1689 | END_OF_GROUPS, |
| 1690 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1691 | }, |
| 1692 | [PINCTRL_PIN_38] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1693 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1694 | PINCTRL_GRP_ETHERNET1_0, |
| 1695 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1696 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1697 | PINCTRL_GRP_RESERVED, |
| 1698 | PINCTRL_GRP_RESERVED, |
| 1699 | PINCTRL_GRP_GPIO0_38, |
| 1700 | PINCTRL_GRP_CAN0_9, |
| 1701 | PINCTRL_GRP_I2C0_9, |
| 1702 | PINCTRL_GRP_PJTAG0_3, |
| 1703 | PINCTRL_GRP_SPI0_3, |
| 1704 | PINCTRL_GRP_TTC0_4_CLK, |
| 1705 | PINCTRL_GRP_UART0_9, |
| 1706 | PINCTRL_GRP_TRACE0_1_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1707 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1708 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1709 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1710 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1711 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1712 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1713 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1714 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1715 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1716 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1717 | END_OF_GROUPS, |
| 1718 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1719 | }, |
| 1720 | [PINCTRL_PIN_39] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1721 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1722 | PINCTRL_GRP_ETHERNET1_0, |
| 1723 | PINCTRL_GRP_RESERVED, |
| 1724 | PINCTRL_GRP_SDIO0_1_CD, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1725 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1726 | PINCTRL_GRP_RESERVED, |
| 1727 | PINCTRL_GRP_GPIO0_39, |
| 1728 | PINCTRL_GRP_CAN0_9, |
| 1729 | PINCTRL_GRP_I2C0_9, |
| 1730 | PINCTRL_GRP_PJTAG0_3, |
| 1731 | PINCTRL_GRP_SPI0_3_SS2, |
| 1732 | PINCTRL_GRP_TTC0_4_WAV, |
| 1733 | PINCTRL_GRP_UART0_9, |
| 1734 | PINCTRL_GRP_TRACE0_1_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1735 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1736 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 1737 | END_OF_GROUPS, |
| 1738 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1739 | }, |
| 1740 | [PINCTRL_PIN_40] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1741 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1742 | PINCTRL_GRP_ETHERNET1_0, |
| 1743 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1744 | PINCTRL_GRP_SDIO0_1, |
| 1745 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1746 | PINCTRL_GRP_RESERVED, |
| 1747 | PINCTRL_GRP_GPIO0_40, |
| 1748 | PINCTRL_GRP_CAN1_10, |
| 1749 | PINCTRL_GRP_I2C1_10, |
| 1750 | PINCTRL_GRP_PJTAG0_3, |
| 1751 | PINCTRL_GRP_SPI0_3_SS1, |
| 1752 | PINCTRL_GRP_TTC3_5_CLK, |
| 1753 | PINCTRL_GRP_UART1_10, |
| 1754 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1755 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1756 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1757 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1758 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1759 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1760 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1761 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1762 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1763 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1764 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1765 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1766 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 1767 | END_OF_GROUPS, |
| 1768 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1769 | }, |
| 1770 | [PINCTRL_PIN_41] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1771 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1772 | PINCTRL_GRP_ETHERNET1_0, |
| 1773 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1774 | PINCTRL_GRP_SDIO0_1, |
| 1775 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1776 | PINCTRL_GRP_RESERVED, |
| 1777 | PINCTRL_GRP_GPIO0_41, |
| 1778 | PINCTRL_GRP_CAN1_10, |
| 1779 | PINCTRL_GRP_I2C1_10, |
| 1780 | PINCTRL_GRP_PJTAG0_3, |
| 1781 | PINCTRL_GRP_SPI0_3_SS0, |
| 1782 | PINCTRL_GRP_TTC3_5_WAV, |
| 1783 | PINCTRL_GRP_UART1_10, |
| 1784 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1785 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1786 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1787 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1788 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 1789 | END_OF_GROUPS, |
| 1790 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1791 | }, |
| 1792 | [PINCTRL_PIN_42] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1793 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1794 | PINCTRL_GRP_ETHERNET1_0, |
| 1795 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1796 | PINCTRL_GRP_SDIO0_1, |
| 1797 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1798 | PINCTRL_GRP_RESERVED, |
| 1799 | PINCTRL_GRP_GPIO0_42, |
| 1800 | PINCTRL_GRP_CAN0_10, |
| 1801 | PINCTRL_GRP_I2C0_10, |
| 1802 | PINCTRL_GRP_SWDT0_6_CLK, |
| 1803 | PINCTRL_GRP_SPI0_3, |
| 1804 | PINCTRL_GRP_TTC2_5_CLK, |
| 1805 | PINCTRL_GRP_UART0_10, |
| 1806 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1807 | PINCTRL_GRP_SDIO0_1, |
| 1808 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1809 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1810 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1811 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 1812 | END_OF_GROUPS, |
| 1813 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1814 | }, |
| 1815 | [PINCTRL_PIN_43] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1816 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1817 | PINCTRL_GRP_ETHERNET1_0, |
| 1818 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1819 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1820 | PINCTRL_GRP_SDIO1_0_PC, |
| 1821 | PINCTRL_GRP_RESERVED, |
| 1822 | PINCTRL_GRP_GPIO0_43, |
| 1823 | PINCTRL_GRP_CAN0_10, |
| 1824 | PINCTRL_GRP_I2C0_10, |
| 1825 | PINCTRL_GRP_SWDT0_6_RST, |
| 1826 | PINCTRL_GRP_SPI0_3, |
| 1827 | PINCTRL_GRP_TTC2_5_WAV, |
| 1828 | PINCTRL_GRP_UART0_10, |
| 1829 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1830 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1831 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1832 | END_OF_GROUPS, |
| 1833 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1834 | }, |
| 1835 | [PINCTRL_PIN_44] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1836 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1837 | PINCTRL_GRP_ETHERNET1_0, |
| 1838 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1839 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1840 | PINCTRL_GRP_SDIO1_0_WP, |
| 1841 | PINCTRL_GRP_RESERVED, |
| 1842 | PINCTRL_GRP_GPIO0_44, |
| 1843 | PINCTRL_GRP_CAN1_11, |
| 1844 | PINCTRL_GRP_I2C1_11, |
| 1845 | PINCTRL_GRP_SWDT1_7_CLK, |
| 1846 | PINCTRL_GRP_SPI1_3, |
| 1847 | PINCTRL_GRP_TTC1_5_CLK, |
| 1848 | PINCTRL_GRP_UART1_11, |
| 1849 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1850 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1851 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1852 | END_OF_GROUPS, |
| 1853 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1854 | }, |
| 1855 | [PINCTRL_PIN_45] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1856 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1857 | PINCTRL_GRP_ETHERNET1_0, |
| 1858 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1859 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1860 | PINCTRL_GRP_SDIO1_0_CD, |
| 1861 | PINCTRL_GRP_RESERVED, |
| 1862 | PINCTRL_GRP_GPIO0_45, |
| 1863 | PINCTRL_GRP_CAN1_11, |
| 1864 | PINCTRL_GRP_I2C1_11, |
| 1865 | PINCTRL_GRP_SWDT1_7_RST, |
| 1866 | PINCTRL_GRP_SPI1_3_SS2, |
| 1867 | PINCTRL_GRP_TTC1_5_WAV, |
| 1868 | PINCTRL_GRP_UART1_11, |
| 1869 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1870 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1871 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1872 | END_OF_GROUPS, |
| 1873 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1874 | }, |
| 1875 | [PINCTRL_PIN_46] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1876 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1877 | PINCTRL_GRP_ETHERNET1_0, |
| 1878 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1879 | PINCTRL_GRP_SDIO0_1, |
| 1880 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1881 | PINCTRL_GRP_RESERVED, |
| 1882 | PINCTRL_GRP_GPIO0_46, |
| 1883 | PINCTRL_GRP_CAN0_11, |
| 1884 | PINCTRL_GRP_I2C0_11, |
| 1885 | PINCTRL_GRP_SWDT0_7_CLK, |
| 1886 | PINCTRL_GRP_SPI1_3_SS1, |
| 1887 | PINCTRL_GRP_TTC0_5_CLK, |
| 1888 | PINCTRL_GRP_UART0_11, |
| 1889 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1890 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1891 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1892 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1893 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 1894 | END_OF_GROUPS, |
| 1895 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1896 | }, |
| 1897 | [PINCTRL_PIN_47] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1898 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1899 | PINCTRL_GRP_ETHERNET1_0, |
| 1900 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1901 | PINCTRL_GRP_SDIO0_1, |
| 1902 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1903 | PINCTRL_GRP_RESERVED, |
| 1904 | PINCTRL_GRP_GPIO0_47, |
| 1905 | PINCTRL_GRP_CAN0_11, |
| 1906 | PINCTRL_GRP_I2C0_11, |
| 1907 | PINCTRL_GRP_SWDT0_7_RST, |
| 1908 | PINCTRL_GRP_SPI1_3_SS0, |
| 1909 | PINCTRL_GRP_TTC0_5_WAV, |
| 1910 | PINCTRL_GRP_UART0_11, |
| 1911 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1912 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1913 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1914 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1915 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 1916 | END_OF_GROUPS, |
| 1917 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1918 | }, |
| 1919 | [PINCTRL_PIN_48] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1920 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1921 | PINCTRL_GRP_ETHERNET1_0, |
| 1922 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1923 | PINCTRL_GRP_SDIO0_1, |
| 1924 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1925 | PINCTRL_GRP_RESERVED, |
| 1926 | PINCTRL_GRP_GPIO0_48, |
| 1927 | PINCTRL_GRP_CAN1_12, |
| 1928 | PINCTRL_GRP_I2C1_12, |
| 1929 | PINCTRL_GRP_SWDT1_8_CLK, |
| 1930 | PINCTRL_GRP_SPI1_3, |
| 1931 | PINCTRL_GRP_TTC3_6_CLK, |
| 1932 | PINCTRL_GRP_UART1_12, |
| 1933 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1934 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1935 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1936 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1937 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 1938 | END_OF_GROUPS, |
| 1939 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1940 | }, |
| 1941 | [PINCTRL_PIN_49] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1942 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1943 | PINCTRL_GRP_ETHERNET1_0, |
| 1944 | PINCTRL_GRP_RESERVED, |
| 1945 | PINCTRL_GRP_SDIO0_1_PC, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1946 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1947 | PINCTRL_GRP_RESERVED, |
| 1948 | PINCTRL_GRP_GPIO0_49, |
| 1949 | PINCTRL_GRP_CAN1_12, |
| 1950 | PINCTRL_GRP_I2C1_12, |
| 1951 | PINCTRL_GRP_SWDT1_8_RST, |
| 1952 | PINCTRL_GRP_SPI1_3, |
| 1953 | PINCTRL_GRP_TTC3_6_WAV, |
| 1954 | PINCTRL_GRP_UART1_12, |
| 1955 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1956 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1957 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 1958 | END_OF_GROUPS, |
| 1959 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1960 | }, |
| 1961 | [PINCTRL_PIN_50] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1962 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1963 | PINCTRL_GRP_GEMTSU0_1, |
| 1964 | PINCTRL_GRP_RESERVED, |
| 1965 | PINCTRL_GRP_SDIO0_1_WP, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1966 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1967 | PINCTRL_GRP_RESERVED, |
| 1968 | PINCTRL_GRP_GPIO0_50, |
| 1969 | PINCTRL_GRP_CAN0_12, |
| 1970 | PINCTRL_GRP_I2C0_12, |
| 1971 | PINCTRL_GRP_SWDT0_8_CLK, |
| 1972 | PINCTRL_GRP_MDIO1_0, |
| 1973 | PINCTRL_GRP_TTC2_6_CLK, |
| 1974 | PINCTRL_GRP_UART0_12, |
| 1975 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1976 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1977 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1978 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 1979 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 1980 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 1981 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 1982 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 1983 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 1984 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 1985 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 1986 | END_OF_GROUPS, |
| 1987 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1988 | }, |
| 1989 | [PINCTRL_PIN_51] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1990 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1991 | PINCTRL_GRP_GEMTSU0_2, |
| 1992 | PINCTRL_GRP_RESERVED, |
| 1993 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1994 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1995 | PINCTRL_GRP_RESERVED, |
| 1996 | PINCTRL_GRP_GPIO0_51, |
| 1997 | PINCTRL_GRP_CAN0_12, |
| 1998 | PINCTRL_GRP_I2C0_12, |
| 1999 | PINCTRL_GRP_SWDT0_8_RST, |
| 2000 | PINCTRL_GRP_MDIO1_0, |
| 2001 | PINCTRL_GRP_TTC2_6_WAV, |
| 2002 | PINCTRL_GRP_UART0_12, |
| 2003 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2004 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 2005 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 2006 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 2007 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 2008 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 2009 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 2010 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 2011 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 2012 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 2013 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 2014 | END_OF_GROUPS, |
| 2015 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2016 | }, |
| 2017 | [PINCTRL_PIN_52] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2018 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2019 | PINCTRL_GRP_ETHERNET2_0, |
| 2020 | PINCTRL_GRP_USB0_0, |
| 2021 | PINCTRL_GRP_RESERVED, |
| 2022 | PINCTRL_GRP_RESERVED, |
| 2023 | PINCTRL_GRP_RESERVED, |
| 2024 | PINCTRL_GRP_GPIO0_52, |
| 2025 | PINCTRL_GRP_CAN1_13, |
| 2026 | PINCTRL_GRP_I2C1_13, |
| 2027 | PINCTRL_GRP_PJTAG0_4, |
| 2028 | PINCTRL_GRP_SPI0_4, |
| 2029 | PINCTRL_GRP_TTC1_6_CLK, |
| 2030 | PINCTRL_GRP_UART1_13, |
| 2031 | PINCTRL_GRP_TRACE0_2_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2032 | END_OF_GROUPS, |
| 2033 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2034 | }, |
| 2035 | [PINCTRL_PIN_53] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2036 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2037 | PINCTRL_GRP_ETHERNET2_0, |
| 2038 | PINCTRL_GRP_USB0_0, |
| 2039 | PINCTRL_GRP_RESERVED, |
| 2040 | PINCTRL_GRP_RESERVED, |
| 2041 | PINCTRL_GRP_RESERVED, |
| 2042 | PINCTRL_GRP_GPIO0_53, |
| 2043 | PINCTRL_GRP_CAN1_13, |
| 2044 | PINCTRL_GRP_I2C1_13, |
| 2045 | PINCTRL_GRP_PJTAG0_4, |
| 2046 | PINCTRL_GRP_SPI0_4_SS2, |
| 2047 | PINCTRL_GRP_TTC1_6_WAV, |
| 2048 | PINCTRL_GRP_UART1_13, |
| 2049 | PINCTRL_GRP_TRACE0_2_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2050 | END_OF_GROUPS, |
| 2051 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2052 | }, |
| 2053 | [PINCTRL_PIN_54] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2054 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2055 | PINCTRL_GRP_ETHERNET2_0, |
| 2056 | PINCTRL_GRP_USB0_0, |
| 2057 | PINCTRL_GRP_RESERVED, |
| 2058 | PINCTRL_GRP_RESERVED, |
| 2059 | PINCTRL_GRP_RESERVED, |
| 2060 | PINCTRL_GRP_GPIO0_54, |
| 2061 | PINCTRL_GRP_CAN0_13, |
| 2062 | PINCTRL_GRP_I2C0_13, |
| 2063 | PINCTRL_GRP_PJTAG0_4, |
| 2064 | PINCTRL_GRP_SPI0_4_SS1, |
| 2065 | PINCTRL_GRP_TTC0_6_CLK, |
| 2066 | PINCTRL_GRP_UART0_13, |
| 2067 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2068 | END_OF_GROUPS, |
| 2069 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2070 | }, |
| 2071 | [PINCTRL_PIN_55] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2072 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2073 | PINCTRL_GRP_ETHERNET2_0, |
| 2074 | PINCTRL_GRP_USB0_0, |
| 2075 | PINCTRL_GRP_RESERVED, |
| 2076 | PINCTRL_GRP_RESERVED, |
| 2077 | PINCTRL_GRP_RESERVED, |
| 2078 | PINCTRL_GRP_GPIO0_55, |
| 2079 | PINCTRL_GRP_CAN0_13, |
| 2080 | PINCTRL_GRP_I2C0_13, |
| 2081 | PINCTRL_GRP_PJTAG0_4, |
| 2082 | PINCTRL_GRP_SPI0_4_SS0, |
| 2083 | PINCTRL_GRP_TTC0_6_WAV, |
| 2084 | PINCTRL_GRP_UART0_13, |
| 2085 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2086 | END_OF_GROUPS, |
| 2087 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2088 | }, |
| 2089 | [PINCTRL_PIN_56] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2090 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2091 | PINCTRL_GRP_ETHERNET2_0, |
| 2092 | PINCTRL_GRP_USB0_0, |
| 2093 | PINCTRL_GRP_RESERVED, |
| 2094 | PINCTRL_GRP_RESERVED, |
| 2095 | PINCTRL_GRP_RESERVED, |
| 2096 | PINCTRL_GRP_GPIO0_56, |
| 2097 | PINCTRL_GRP_CAN1_14, |
| 2098 | PINCTRL_GRP_I2C1_14, |
| 2099 | PINCTRL_GRP_SWDT1_9_CLK, |
| 2100 | PINCTRL_GRP_SPI0_4, |
| 2101 | PINCTRL_GRP_TTC3_7_CLK, |
| 2102 | PINCTRL_GRP_UART1_14, |
| 2103 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2104 | END_OF_GROUPS, |
| 2105 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2106 | }, |
| 2107 | [PINCTRL_PIN_57] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2108 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2109 | PINCTRL_GRP_ETHERNET2_0, |
| 2110 | PINCTRL_GRP_USB0_0, |
| 2111 | PINCTRL_GRP_RESERVED, |
| 2112 | PINCTRL_GRP_RESERVED, |
| 2113 | PINCTRL_GRP_RESERVED, |
| 2114 | PINCTRL_GRP_GPIO0_57, |
| 2115 | PINCTRL_GRP_CAN1_14, |
| 2116 | PINCTRL_GRP_I2C1_14, |
| 2117 | PINCTRL_GRP_SWDT1_9_RST, |
| 2118 | PINCTRL_GRP_SPI0_4, |
| 2119 | PINCTRL_GRP_TTC3_7_WAV, |
| 2120 | PINCTRL_GRP_UART1_14, |
| 2121 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2122 | END_OF_GROUPS, |
| 2123 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2124 | }, |
| 2125 | [PINCTRL_PIN_58] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2126 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2127 | PINCTRL_GRP_ETHERNET2_0, |
| 2128 | PINCTRL_GRP_USB0_0, |
| 2129 | PINCTRL_GRP_RESERVED, |
| 2130 | PINCTRL_GRP_RESERVED, |
| 2131 | PINCTRL_GRP_RESERVED, |
| 2132 | PINCTRL_GRP_GPIO0_58, |
| 2133 | PINCTRL_GRP_CAN0_14, |
| 2134 | PINCTRL_GRP_I2C0_14, |
| 2135 | PINCTRL_GRP_PJTAG0_5, |
| 2136 | PINCTRL_GRP_SPI1_4, |
| 2137 | PINCTRL_GRP_TTC2_7_CLK, |
| 2138 | PINCTRL_GRP_UART0_14, |
| 2139 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2140 | END_OF_GROUPS, |
| 2141 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2142 | }, |
| 2143 | [PINCTRL_PIN_59] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2144 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2145 | PINCTRL_GRP_ETHERNET2_0, |
| 2146 | PINCTRL_GRP_USB0_0, |
| 2147 | PINCTRL_GRP_RESERVED, |
| 2148 | PINCTRL_GRP_RESERVED, |
| 2149 | PINCTRL_GRP_RESERVED, |
| 2150 | PINCTRL_GRP_GPIO0_59, |
| 2151 | PINCTRL_GRP_CAN0_14, |
| 2152 | PINCTRL_GRP_I2C0_14, |
| 2153 | PINCTRL_GRP_PJTAG0_5, |
| 2154 | PINCTRL_GRP_SPI1_4_SS2, |
| 2155 | PINCTRL_GRP_TTC2_7_WAV, |
| 2156 | PINCTRL_GRP_UART0_14, |
| 2157 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2158 | END_OF_GROUPS, |
| 2159 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2160 | }, |
| 2161 | [PINCTRL_PIN_60] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2162 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2163 | PINCTRL_GRP_ETHERNET2_0, |
| 2164 | PINCTRL_GRP_USB0_0, |
| 2165 | PINCTRL_GRP_RESERVED, |
| 2166 | PINCTRL_GRP_RESERVED, |
| 2167 | PINCTRL_GRP_RESERVED, |
| 2168 | PINCTRL_GRP_GPIO0_60, |
| 2169 | PINCTRL_GRP_CAN1_15, |
| 2170 | PINCTRL_GRP_I2C1_15, |
| 2171 | PINCTRL_GRP_PJTAG0_5, |
| 2172 | PINCTRL_GRP_SPI1_4_SS1, |
| 2173 | PINCTRL_GRP_TTC1_7_CLK, |
| 2174 | PINCTRL_GRP_UART1_15, |
| 2175 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2176 | END_OF_GROUPS, |
| 2177 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2178 | }, |
| 2179 | [PINCTRL_PIN_61] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2180 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2181 | PINCTRL_GRP_ETHERNET2_0, |
| 2182 | PINCTRL_GRP_USB0_0, |
| 2183 | PINCTRL_GRP_RESERVED, |
| 2184 | PINCTRL_GRP_RESERVED, |
| 2185 | PINCTRL_GRP_RESERVED, |
| 2186 | PINCTRL_GRP_GPIO0_61, |
| 2187 | PINCTRL_GRP_CAN1_15, |
| 2188 | PINCTRL_GRP_I2C1_15, |
| 2189 | PINCTRL_GRP_PJTAG0_5, |
| 2190 | PINCTRL_GRP_SPI1_4_SS0, |
| 2191 | PINCTRL_GRP_TTC1_7_WAV, |
| 2192 | PINCTRL_GRP_UART1_15, |
| 2193 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2194 | END_OF_GROUPS, |
| 2195 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2196 | }, |
| 2197 | [PINCTRL_PIN_62] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2198 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2199 | PINCTRL_GRP_ETHERNET2_0, |
| 2200 | PINCTRL_GRP_USB0_0, |
| 2201 | PINCTRL_GRP_RESERVED, |
| 2202 | PINCTRL_GRP_RESERVED, |
| 2203 | PINCTRL_GRP_RESERVED, |
| 2204 | PINCTRL_GRP_GPIO0_62, |
| 2205 | PINCTRL_GRP_CAN0_15, |
| 2206 | PINCTRL_GRP_I2C0_15, |
| 2207 | PINCTRL_GRP_SWDT0_9_CLK, |
| 2208 | PINCTRL_GRP_SPI1_4, |
| 2209 | PINCTRL_GRP_TTC0_7_CLK, |
| 2210 | PINCTRL_GRP_UART0_15, |
| 2211 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2212 | END_OF_GROUPS, |
| 2213 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2214 | }, |
| 2215 | [PINCTRL_PIN_63] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2216 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2217 | PINCTRL_GRP_ETHERNET2_0, |
| 2218 | PINCTRL_GRP_USB0_0, |
| 2219 | PINCTRL_GRP_RESERVED, |
| 2220 | PINCTRL_GRP_RESERVED, |
| 2221 | PINCTRL_GRP_RESERVED, |
| 2222 | PINCTRL_GRP_GPIO0_63, |
| 2223 | PINCTRL_GRP_CAN0_15, |
| 2224 | PINCTRL_GRP_I2C0_15, |
| 2225 | PINCTRL_GRP_SWDT0_9_RST, |
| 2226 | PINCTRL_GRP_SPI1_4, |
| 2227 | PINCTRL_GRP_TTC0_7_WAV, |
| 2228 | PINCTRL_GRP_UART0_15, |
| 2229 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2230 | END_OF_GROUPS, |
| 2231 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2232 | }, |
| 2233 | [PINCTRL_PIN_64] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2234 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2235 | PINCTRL_GRP_ETHERNET3_0, |
| 2236 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2237 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2238 | PINCTRL_GRP_RESERVED, |
| 2239 | PINCTRL_GRP_RESERVED, |
| 2240 | PINCTRL_GRP_GPIO0_64, |
| 2241 | PINCTRL_GRP_CAN1_16, |
| 2242 | PINCTRL_GRP_I2C1_16, |
| 2243 | PINCTRL_GRP_SWDT1_10_CLK, |
| 2244 | PINCTRL_GRP_SPI0_5, |
| 2245 | PINCTRL_GRP_TTC3_8_CLK, |
| 2246 | PINCTRL_GRP_UART1_16, |
| 2247 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2248 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2249 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2250 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 2251 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 2252 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 2253 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 2254 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 2255 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 2256 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 2257 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 2258 | END_OF_GROUPS, |
| 2259 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2260 | }, |
| 2261 | [PINCTRL_PIN_65] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2262 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2263 | PINCTRL_GRP_ETHERNET3_0, |
| 2264 | PINCTRL_GRP_USB1_0, |
| 2265 | PINCTRL_GRP_SDIO0_2_CD, |
| 2266 | PINCTRL_GRP_RESERVED, |
| 2267 | PINCTRL_GRP_RESERVED, |
| 2268 | PINCTRL_GRP_GPIO0_65, |
| 2269 | PINCTRL_GRP_CAN1_16, |
| 2270 | PINCTRL_GRP_I2C1_16, |
| 2271 | PINCTRL_GRP_SWDT1_10_RST, |
| 2272 | PINCTRL_GRP_SPI0_5_SS2, |
| 2273 | PINCTRL_GRP_TTC3_8_WAV, |
| 2274 | PINCTRL_GRP_UART1_16, |
| 2275 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2276 | END_OF_GROUPS, |
| 2277 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2278 | }, |
| 2279 | [PINCTRL_PIN_66] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2280 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2281 | PINCTRL_GRP_ETHERNET3_0, |
| 2282 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2283 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2284 | PINCTRL_GRP_RESERVED, |
| 2285 | PINCTRL_GRP_RESERVED, |
| 2286 | PINCTRL_GRP_GPIO0_66, |
| 2287 | PINCTRL_GRP_CAN0_16, |
| 2288 | PINCTRL_GRP_I2C0_16, |
| 2289 | PINCTRL_GRP_SWDT0_10_CLK, |
| 2290 | PINCTRL_GRP_SPI0_5_SS1, |
| 2291 | PINCTRL_GRP_TTC2_8_CLK, |
| 2292 | PINCTRL_GRP_UART0_16, |
| 2293 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2294 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2295 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2296 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 2297 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 2298 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 2299 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 2300 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 2301 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 2302 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 2303 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 2304 | END_OF_GROUPS, |
| 2305 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2306 | }, |
| 2307 | [PINCTRL_PIN_67] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2308 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2309 | PINCTRL_GRP_ETHERNET3_0, |
| 2310 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2311 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2312 | PINCTRL_GRP_RESERVED, |
| 2313 | PINCTRL_GRP_RESERVED, |
| 2314 | PINCTRL_GRP_GPIO0_67, |
| 2315 | PINCTRL_GRP_CAN0_16, |
| 2316 | PINCTRL_GRP_I2C0_16, |
| 2317 | PINCTRL_GRP_SWDT0_10_RST, |
| 2318 | PINCTRL_GRP_SPI0_5_SS0, |
| 2319 | PINCTRL_GRP_TTC2_8_WAV, |
| 2320 | PINCTRL_GRP_UART0_16, |
| 2321 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2322 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2323 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 2324 | END_OF_GROUPS, |
| 2325 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2326 | }, |
| 2327 | [PINCTRL_PIN_68] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2328 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2329 | PINCTRL_GRP_ETHERNET3_0, |
| 2330 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2331 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2332 | PINCTRL_GRP_RESERVED, |
| 2333 | PINCTRL_GRP_RESERVED, |
| 2334 | PINCTRL_GRP_GPIO0_68, |
| 2335 | PINCTRL_GRP_CAN1_17, |
| 2336 | PINCTRL_GRP_I2C1_17, |
| 2337 | PINCTRL_GRP_SWDT1_11_CLK, |
| 2338 | PINCTRL_GRP_SPI0_5, |
| 2339 | PINCTRL_GRP_TTC1_8_CLK, |
| 2340 | PINCTRL_GRP_UART1_17, |
| 2341 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2342 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2343 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 2344 | END_OF_GROUPS, |
| 2345 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2346 | }, |
| 2347 | [PINCTRL_PIN_69] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2348 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2349 | PINCTRL_GRP_ETHERNET3_0, |
| 2350 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2351 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2352 | PINCTRL_GRP_SDIO1_1_WP, |
| 2353 | PINCTRL_GRP_RESERVED, |
| 2354 | PINCTRL_GRP_GPIO0_69, |
| 2355 | PINCTRL_GRP_CAN1_17, |
| 2356 | PINCTRL_GRP_I2C1_17, |
| 2357 | PINCTRL_GRP_SWDT1_11_RST, |
| 2358 | PINCTRL_GRP_SPI0_5, |
| 2359 | PINCTRL_GRP_TTC1_8_WAV, |
| 2360 | PINCTRL_GRP_UART1_17, |
| 2361 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2362 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2363 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 2364 | END_OF_GROUPS, |
| 2365 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2366 | }, |
| 2367 | [PINCTRL_PIN_70] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2368 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2369 | PINCTRL_GRP_ETHERNET3_0, |
| 2370 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2371 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2372 | PINCTRL_GRP_SDIO1_1_PC, |
| 2373 | PINCTRL_GRP_RESERVED, |
| 2374 | PINCTRL_GRP_GPIO0_70, |
| 2375 | PINCTRL_GRP_CAN0_17, |
| 2376 | PINCTRL_GRP_I2C0_17, |
| 2377 | PINCTRL_GRP_SWDT0_11_CLK, |
| 2378 | PINCTRL_GRP_SPI1_5, |
| 2379 | PINCTRL_GRP_TTC0_8_CLK, |
| 2380 | PINCTRL_GRP_UART0_17, |
| 2381 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2382 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 2383 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 2384 | END_OF_GROUPS, |
| 2385 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2386 | }, |
| 2387 | [PINCTRL_PIN_71] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2388 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2389 | PINCTRL_GRP_ETHERNET3_0, |
| 2390 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2391 | PINCTRL_GRP_SDIO0_2, |
| 2392 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2393 | PINCTRL_GRP_RESERVED, |
| 2394 | PINCTRL_GRP_GPIO0_71, |
| 2395 | PINCTRL_GRP_CAN0_17, |
| 2396 | PINCTRL_GRP_I2C0_17, |
| 2397 | PINCTRL_GRP_SWDT0_11_RST, |
| 2398 | PINCTRL_GRP_SPI1_5_SS2, |
| 2399 | PINCTRL_GRP_TTC0_8_WAV, |
| 2400 | PINCTRL_GRP_UART0_17, |
| 2401 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2402 | PINCTRL_GRP_SDIO0_2, |
| 2403 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2404 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 2405 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 2406 | END_OF_GROUPS, |
| 2407 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2408 | }, |
| 2409 | [PINCTRL_PIN_72] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2410 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2411 | PINCTRL_GRP_ETHERNET3_0, |
| 2412 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2413 | PINCTRL_GRP_SDIO0_2, |
| 2414 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2415 | PINCTRL_GRP_RESERVED, |
| 2416 | PINCTRL_GRP_GPIO0_72, |
| 2417 | PINCTRL_GRP_CAN1_18, |
| 2418 | PINCTRL_GRP_I2C1_18, |
| 2419 | PINCTRL_GRP_SWDT1_12_CLK, |
| 2420 | PINCTRL_GRP_SPI1_5_SS1, |
| 2421 | PINCTRL_GRP_RESERVED, |
| 2422 | PINCTRL_GRP_UART1_18, |
| 2423 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2424 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2425 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 2426 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 2427 | END_OF_GROUPS, |
| 2428 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2429 | }, |
| 2430 | [PINCTRL_PIN_73] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2431 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2432 | PINCTRL_GRP_ETHERNET3_0, |
| 2433 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2434 | PINCTRL_GRP_SDIO0_2, |
| 2435 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2436 | PINCTRL_GRP_RESERVED, |
| 2437 | PINCTRL_GRP_GPIO0_73, |
| 2438 | PINCTRL_GRP_CAN1_18, |
| 2439 | PINCTRL_GRP_I2C1_18, |
| 2440 | PINCTRL_GRP_SWDT1_12_RST, |
| 2441 | PINCTRL_GRP_SPI1_5_SS0, |
| 2442 | PINCTRL_GRP_RESERVED, |
| 2443 | PINCTRL_GRP_UART1_18, |
| 2444 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2445 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2446 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 2447 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 2448 | END_OF_GROUPS, |
| 2449 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2450 | }, |
| 2451 | [PINCTRL_PIN_74] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2452 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2453 | PINCTRL_GRP_ETHERNET3_0, |
| 2454 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2455 | PINCTRL_GRP_SDIO0_2, |
| 2456 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2457 | PINCTRL_GRP_RESERVED, |
| 2458 | PINCTRL_GRP_GPIO0_74, |
| 2459 | PINCTRL_GRP_CAN0_18, |
| 2460 | PINCTRL_GRP_I2C0_18, |
| 2461 | PINCTRL_GRP_SWDT0_12_CLK, |
| 2462 | PINCTRL_GRP_SPI1_5, |
| 2463 | PINCTRL_GRP_RESERVED, |
| 2464 | PINCTRL_GRP_UART0_18, |
| 2465 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2466 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 2467 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 2468 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 2469 | END_OF_GROUPS, |
| 2470 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2471 | }, |
| 2472 | [PINCTRL_PIN_75] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2473 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2474 | PINCTRL_GRP_ETHERNET3_0, |
| 2475 | PINCTRL_GRP_USB1_0, |
| 2476 | PINCTRL_GRP_SDIO0_2_PC, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2477 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2478 | PINCTRL_GRP_RESERVED, |
| 2479 | PINCTRL_GRP_GPIO0_75, |
| 2480 | PINCTRL_GRP_CAN0_18, |
| 2481 | PINCTRL_GRP_I2C0_18, |
| 2482 | PINCTRL_GRP_SWDT0_12_RST, |
| 2483 | PINCTRL_GRP_SPI1_5, |
| 2484 | PINCTRL_GRP_RESERVED, |
| 2485 | PINCTRL_GRP_UART0_18, |
| 2486 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2487 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 2488 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 2489 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 2490 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 2491 | END_OF_GROUPS, |
| 2492 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2493 | }, |
| 2494 | [PINCTRL_PIN_76] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2495 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2496 | PINCTRL_GRP_RESERVED, |
| 2497 | PINCTRL_GRP_RESERVED, |
| 2498 | PINCTRL_GRP_SDIO0_2_WP, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2499 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2500 | PINCTRL_GRP_RESERVED, |
| 2501 | PINCTRL_GRP_GPIO0_76, |
| 2502 | PINCTRL_GRP_CAN1_19, |
| 2503 | PINCTRL_GRP_I2C1_19, |
| 2504 | PINCTRL_GRP_MDIO0_0, |
| 2505 | PINCTRL_GRP_MDIO1_1, |
| 2506 | PINCTRL_GRP_MDIO2_0, |
| 2507 | PINCTRL_GRP_MDIO3_0, |
| 2508 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2509 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 2510 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 2511 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 2512 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 2513 | END_OF_GROUPS, |
| 2514 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2515 | }, |
| 2516 | [PINCTRL_PIN_77] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2517 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2518 | PINCTRL_GRP_RESERVED, |
| 2519 | PINCTRL_GRP_RESERVED, |
| 2520 | PINCTRL_GRP_RESERVED, |
| 2521 | PINCTRL_GRP_SDIO1_1_CD, |
| 2522 | PINCTRL_GRP_RESERVED, |
| 2523 | PINCTRL_GRP_GPIO0_77, |
| 2524 | PINCTRL_GRP_CAN1_19, |
| 2525 | PINCTRL_GRP_I2C1_19, |
| 2526 | PINCTRL_GRP_MDIO0_0, |
| 2527 | PINCTRL_GRP_MDIO1_1, |
| 2528 | PINCTRL_GRP_MDIO2_0, |
| 2529 | PINCTRL_GRP_MDIO3_0, |
| 2530 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2531 | END_OF_GROUPS, |
| 2532 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2533 | }, |
| 2534 | }; |
| 2535 | |
| 2536 | /** |
| 2537 | * pm_api_pinctrl_get_num_pins() - PM call to request number of pins |
| 2538 | * @npins Number of pins |
| 2539 | * |
| 2540 | * This function is used by master to get number of pins |
| 2541 | * |
| 2542 | * @return Returns success. |
| 2543 | */ |
| 2544 | enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) |
| 2545 | { |
| 2546 | *npins = MAX_PIN; |
| 2547 | |
| 2548 | return PM_RET_SUCCESS; |
| 2549 | } |
| 2550 | |
| 2551 | /** |
| 2552 | * pm_api_pinctrl_get_num_functions() - PM call to request number of functions |
| 2553 | * @nfuncs Number of functions |
| 2554 | * |
| 2555 | * This function is used by master to get number of functions |
| 2556 | * |
| 2557 | * @return Returns success. |
| 2558 | */ |
| 2559 | enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) |
| 2560 | { |
| 2561 | *nfuncs = MAX_FUNCTION; |
| 2562 | |
| 2563 | return PM_RET_SUCCESS; |
| 2564 | } |
| 2565 | |
| 2566 | /** |
| 2567 | * pm_api_pinctrl_get_num_func_groups() - PM call to request number of |
| 2568 | * function groups |
| 2569 | * @fid Function Id |
| 2570 | * @ngroups Number of function groups |
| 2571 | * |
| 2572 | * This function is used by master to get number of function groups |
| 2573 | * |
| 2574 | * @return Returns success. |
| 2575 | */ |
| 2576 | enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, |
| 2577 | unsigned int *ngroups) |
| 2578 | { |
| 2579 | int i = 0; |
| 2580 | uint16_t *grps; |
| 2581 | |
| 2582 | if (fid >= MAX_FUNCTION) |
| 2583 | return PM_RET_ERROR_ARGS; |
| 2584 | |
| 2585 | *ngroups = 0; |
| 2586 | |
| 2587 | grps = *pinctrl_functions[fid].groups; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2588 | if (grps == NULL) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2589 | return PM_RET_SUCCESS; |
| 2590 | |
| 2591 | while (grps[i++] != (uint16_t)END_OF_GROUPS) |
| 2592 | (*ngroups)++; |
| 2593 | |
| 2594 | return PM_RET_SUCCESS; |
| 2595 | } |
| 2596 | |
| 2597 | /** |
| 2598 | * pm_api_pinctrl_get_function_name() - PM call to request a function name |
| 2599 | * @fid Function ID |
| 2600 | * @name Name of function (max 16 bytes) |
| 2601 | * |
| 2602 | * This function is used by master to get name of function specified |
| 2603 | * by given function ID. |
| 2604 | * |
| 2605 | * @return Returns success. In case of error, name data is 0. |
| 2606 | */ |
| 2607 | enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid, |
| 2608 | char *name) |
| 2609 | { |
| 2610 | if (fid >= MAX_FUNCTION) |
| 2611 | memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); |
| 2612 | else |
| 2613 | memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); |
| 2614 | |
| 2615 | return PM_RET_SUCCESS; |
| 2616 | } |
| 2617 | |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2618 | /** |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2619 | * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function |
| 2620 | * groups of function Id |
| 2621 | * @fid Function ID |
| 2622 | * @index Index of next function groups |
| 2623 | * @groups Function groups |
| 2624 | * |
| 2625 | * This function is used by master to get function groups specified |
| 2626 | * by given function Id. This API will return 6 function groups with |
| 2627 | * a single response. To get other function groups, master should call |
| 2628 | * same API in loop with new function groups index till error is returned. |
| 2629 | * |
| 2630 | * E.g First call should have index 0 which will return function groups |
| 2631 | * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| 2632 | * function groups 6, 7, 8, 9, 10 and 11 and so on. |
| 2633 | * |
| 2634 | * Return: Returns status, either success or error+reason. |
| 2635 | */ |
| 2636 | enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, |
| 2637 | unsigned int index, |
| 2638 | uint16_t *groups) |
| 2639 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2640 | unsigned int i; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2641 | uint16_t *grps; |
| 2642 | |
| 2643 | if (fid >= MAX_FUNCTION) |
| 2644 | return PM_RET_ERROR_ARGS; |
| 2645 | |
| 2646 | memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| 2647 | |
| 2648 | grps = *pinctrl_functions[fid].groups; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2649 | if (grps == NULL) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2650 | return PM_RET_SUCCESS; |
| 2651 | |
| 2652 | /* Skip groups till index */ |
| 2653 | for (i = 0; i < index; i++) |
| 2654 | if (grps[i] == (uint16_t)END_OF_GROUPS) |
| 2655 | return PM_RET_SUCCESS; |
| 2656 | |
| 2657 | for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { |
| 2658 | groups[i] = grps[index + i]; |
| 2659 | if (groups[i] == (uint16_t)END_OF_GROUPS) |
| 2660 | break; |
| 2661 | } |
| 2662 | |
| 2663 | return PM_RET_SUCCESS; |
| 2664 | } |
| 2665 | |
| 2666 | /** |
| 2667 | * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin |
| 2668 | * groups of pin |
| 2669 | * @pin Pin |
| 2670 | * @index Index of next pin groups |
| 2671 | * @groups pin groups |
| 2672 | * |
| 2673 | * This function is used by master to get pin groups specified |
| 2674 | * by given pin Id. This API will return 6 pin groups with |
| 2675 | * a single response. To get other pin groups, master should call |
| 2676 | * same API in loop with new pin groups index till error is returned. |
| 2677 | * |
| 2678 | * E.g First call should have index 0 which will return pin groups |
| 2679 | * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| 2680 | * pin groups 6, 7, 8, 9, 10 and 11 and so on. |
| 2681 | * |
| 2682 | * Return: Returns status, either success or error+reason. |
| 2683 | */ |
| 2684 | enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, |
| 2685 | unsigned int index, |
| 2686 | uint16_t *groups) |
| 2687 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2688 | unsigned int i; |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2689 | uint16_t *grps; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2690 | |
| 2691 | if (pin >= MAX_PIN) |
| 2692 | return PM_RET_ERROR_ARGS; |
| 2693 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2694 | memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| 2695 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2696 | grps = *zynqmp_pin_groups[pin].groups; |
| 2697 | if (!grps) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2698 | return PM_RET_SUCCESS; |
| 2699 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2700 | /* Skip groups till index */ |
| 2701 | for (i = 0; i < index; i++) |
| 2702 | if (grps[i] == (uint16_t)END_OF_GROUPS) |
| 2703 | return PM_RET_SUCCESS; |
| 2704 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2705 | for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2706 | groups[i] = grps[index + i]; |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2707 | if (groups[i] == (uint16_t)END_OF_GROUPS) |
| 2708 | break; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2709 | } |
| 2710 | |
| 2711 | return PM_RET_SUCCESS; |
| 2712 | } |
| 2713 | |
| 2714 | /** |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2715 | * pm_api_pinctrl_get_function() - Read function id set for the given pin |
| 2716 | * @pin Pin number |
| 2717 | * @nid Node ID of function currently set for given pin |
| 2718 | * |
| 2719 | * This function provides the function currently set for the given pin. |
| 2720 | * |
| 2721 | * @return Returns status, either success or error+reason |
| 2722 | */ |
| 2723 | enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2724 | unsigned int *id) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2725 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2726 | unsigned int i = 0, j = 0; |
| 2727 | enum pm_ret_status ret = PM_RET_SUCCESS; |
| 2728 | unsigned int ctrlreg, val, gid; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2729 | uint16_t *grps; |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2730 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2731 | ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; |
| 2732 | ret = pm_mmio_read(ctrlreg, &val); |
| 2733 | if (ret != PM_RET_SUCCESS) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2734 | return ret; |
| 2735 | |
| 2736 | val &= PINCTRL_FUNCTION_MASK; |
| 2737 | |
| 2738 | for (i = 0; i < NFUNCS_PER_PIN; i++) |
| 2739 | if (val == pm_pinctrl_mux[i]) |
| 2740 | break; |
| 2741 | |
| 2742 | if (i == NFUNCS_PER_PIN) |
| 2743 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2744 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2745 | gid = *(*zynqmp_pin_groups[pin].groups + i); |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2746 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2747 | for (i = 0; i < MAX_FUNCTION; i++) { |
| 2748 | grps = *pinctrl_functions[i].groups; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2749 | if (grps == NULL) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2750 | continue; |
| 2751 | if (val != pinctrl_functions[i].regval) |
| 2752 | continue; |
| 2753 | |
| 2754 | for (j = 0; grps[j] != (uint16_t)END_OF_GROUPS; j++) { |
| 2755 | if (gid == grps[j]) { |
| 2756 | *id = i; |
| 2757 | goto done; |
| 2758 | } |
| 2759 | } |
| 2760 | } |
| 2761 | if (i == MAX_FUNCTION) |
| 2762 | ret = PM_RET_ERROR_ARGS; |
| 2763 | done: |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2764 | return ret; |
| 2765 | } |
| 2766 | |
| 2767 | /** |
| 2768 | * pm_api_pinctrl_set_function() - Set function id set for the given pin |
| 2769 | * @pin Pin number |
| 2770 | * @nid Node ID of function to set for given pin |
| 2771 | * |
| 2772 | * This function provides the function currently set for the given pin. |
| 2773 | * |
| 2774 | * @return Returns status, either success or error+reason |
| 2775 | */ |
| 2776 | enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2777 | unsigned int fid) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2778 | { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2779 | int i, j; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2780 | unsigned int ctrlreg, val; |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2781 | uint16_t *pgrps, *fgrps; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2782 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2783 | ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2784 | val = pinctrl_functions[fid].regval; |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2785 | |
| 2786 | for (i = 0; i < NFUNCS_PER_PIN; i++) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2787 | if (val == pm_pinctrl_mux[i]) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2788 | break; |
| 2789 | |
| 2790 | if (i == NFUNCS_PER_PIN) |
| 2791 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2792 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2793 | pgrps = *zynqmp_pin_groups[pin].groups; |
| 2794 | if (!pgrps) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2795 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2796 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2797 | fgrps = *pinctrl_functions[fid].groups; |
| 2798 | if (!fgrps) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2799 | return PM_RET_ERROR_NOTSUPPORTED; |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2800 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2801 | for (i = 0; fgrps[i] != (uint16_t)END_OF_GROUPS; i++) |
| 2802 | for (j = 0; pgrps[j] != (uint16_t)END_OF_GROUPS; j++) |
| 2803 | if (fgrps[i] == pgrps[j]) |
| 2804 | goto match; |
| 2805 | |
| 2806 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2807 | |
| 2808 | match: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2809 | return pm_mmio_write(ctrlreg, PINCTRL_FUNCTION_MASK, val); |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2810 | } |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2811 | |
| 2812 | /** |
| 2813 | * pm_api_pinctrl_set_config() - Set configuration parameter for given pin |
| 2814 | * @pin: Pin for which configuration is to be set |
| 2815 | * @param: Configuration parameter to be set |
| 2816 | * @value: Value to be set for configuration parameter |
| 2817 | * |
| 2818 | * This function sets value of requested configuration parameter for given pin. |
| 2819 | * |
| 2820 | * @return Returns status, either success or error+reason |
| 2821 | */ |
| 2822 | enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin, |
| 2823 | unsigned int param, |
| 2824 | unsigned int value) |
| 2825 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2826 | enum pm_ret_status ret; |
| 2827 | unsigned int ctrlreg, mask, val, offset; |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2828 | |
| 2829 | if (param >= PINCTRL_CONFIG_MAX) |
| 2830 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2831 | |
| 2832 | if (pin >= PINCTRL_NUM_MIOS) |
| 2833 | return PM_RET_ERROR_ARGS; |
| 2834 | |
| 2835 | mask = 1 << PINCTRL_PIN_OFFSET(pin); |
| 2836 | |
| 2837 | switch (param) { |
| 2838 | case PINCTRL_CONFIG_SLEW_RATE: |
| 2839 | if (value != PINCTRL_SLEW_RATE_FAST && |
| 2840 | value != PINCTRL_SLEW_RATE_SLOW) |
| 2841 | return PM_RET_ERROR_ARGS; |
| 2842 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2843 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2844 | PINCTRL_SLEWCTRL_REG_OFFSET, |
| 2845 | pin); |
| 2846 | val = value << PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2847 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2848 | break; |
| 2849 | case PINCTRL_CONFIG_BIAS_STATUS: |
| 2850 | if (value != PINCTRL_BIAS_ENABLE && |
| 2851 | value != PINCTRL_BIAS_DISABLE) |
| 2852 | return PM_RET_ERROR_ARGS; |
| 2853 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2854 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2855 | PINCTRL_PULLSTAT_REG_OFFSET, |
| 2856 | pin); |
| 2857 | |
| 2858 | offset = PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2859 | if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
| 2860 | offset = (offset < 12U) ? |
| 2861 | (offset + 14U) : (offset - 12U); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2862 | |
| 2863 | val = value << offset; |
| 2864 | mask = 1 << offset; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2865 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2866 | break; |
| 2867 | case PINCTRL_CONFIG_PULL_CTRL: |
| 2868 | |
| 2869 | if (value != PINCTRL_BIAS_PULL_DOWN && |
| 2870 | value != PINCTRL_BIAS_PULL_UP) |
| 2871 | return PM_RET_ERROR_ARGS; |
| 2872 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2873 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2874 | PINCTRL_PULLSTAT_REG_OFFSET, |
| 2875 | pin); |
| 2876 | |
| 2877 | offset = PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2878 | if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
| 2879 | offset = (offset < 12U) ? |
| 2880 | (offset + 14U) : (offset - 12U); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2881 | |
| 2882 | val = PINCTRL_BIAS_ENABLE << offset; |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2883 | ret = pm_mmio_write(ctrlreg, 1 << offset, val); |
| 2884 | if (ret != PM_RET_SUCCESS) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2885 | return ret; |
| 2886 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2887 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2888 | PINCTRL_PULLCTRL_REG_OFFSET, |
| 2889 | pin); |
| 2890 | val = value << PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2891 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2892 | break; |
| 2893 | case PINCTRL_CONFIG_SCHMITT_CMOS: |
| 2894 | if (value != PINCTRL_INPUT_TYPE_CMOS && |
| 2895 | value != PINCTRL_INPUT_TYPE_SCHMITT) |
| 2896 | return PM_RET_ERROR_ARGS; |
| 2897 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2898 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2899 | PINCTRL_SCHCMOS_REG_OFFSET, |
| 2900 | pin); |
| 2901 | |
| 2902 | val = value << PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2903 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2904 | break; |
| 2905 | case PINCTRL_CONFIG_DRIVE_STRENGTH: |
| 2906 | if (value > PINCTRL_DRIVE_STRENGTH_12MA) |
| 2907 | return PM_RET_ERROR_ARGS; |
| 2908 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2909 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2910 | PINCTRL_DRVSTRN0_REG_OFFSET, |
| 2911 | pin); |
| 2912 | val = (value >> 1) << PINCTRL_PIN_OFFSET(pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2913 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2914 | if (ret) |
| 2915 | return ret; |
| 2916 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2917 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2918 | PINCTRL_DRVSTRN1_REG_OFFSET, |
| 2919 | pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2920 | val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin); |
| 2921 | ret = pm_mmio_write(ctrlreg, mask, val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2922 | break; |
| 2923 | default: |
| 2924 | ERROR("Invalid parameter %u\n", param); |
| 2925 | ret = PM_RET_ERROR_NOTSUPPORTED; |
| 2926 | break; |
| 2927 | } |
| 2928 | |
| 2929 | return ret; |
| 2930 | } |
| 2931 | |
| 2932 | /** |
| 2933 | * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin |
| 2934 | * @pin: Pin for which configuration is to be read |
| 2935 | * @param: Configuration parameter to be read |
| 2936 | * @value: buffer to store value of configuration parameter |
| 2937 | * |
| 2938 | * This function reads value of requested configuration parameter for given pin. |
| 2939 | * |
| 2940 | * @return Returns status, either success or error+reason |
| 2941 | */ |
| 2942 | enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin, |
| 2943 | unsigned int param, |
| 2944 | unsigned int *value) |
| 2945 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2946 | enum pm_ret_status ret; |
| 2947 | unsigned int ctrlreg, val; |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2948 | |
| 2949 | if (param >= PINCTRL_CONFIG_MAX) |
| 2950 | return PM_RET_ERROR_NOTSUPPORTED; |
| 2951 | |
| 2952 | if (pin >= PINCTRL_NUM_MIOS) |
| 2953 | return PM_RET_ERROR_ARGS; |
| 2954 | |
| 2955 | switch (param) { |
| 2956 | case PINCTRL_CONFIG_SLEW_RATE: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2957 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2958 | PINCTRL_SLEWCTRL_REG_OFFSET, |
| 2959 | pin); |
| 2960 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2961 | ret = pm_mmio_read(ctrlreg, &val); |
| 2962 | if (ret != PM_RET_SUCCESS) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2963 | return ret; |
| 2964 | |
| 2965 | *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| 2966 | break; |
| 2967 | case PINCTRL_CONFIG_BIAS_STATUS: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2968 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2969 | PINCTRL_PULLSTAT_REG_OFFSET, |
| 2970 | pin); |
| 2971 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2972 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2973 | if (ret) |
| 2974 | return ret; |
| 2975 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2976 | if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2977 | val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF); |
| 2978 | |
| 2979 | *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| 2980 | break; |
| 2981 | case PINCTRL_CONFIG_PULL_CTRL: |
| 2982 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2983 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2984 | PINCTRL_PULLCTRL_REG_OFFSET, |
| 2985 | pin); |
| 2986 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2987 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2988 | if (ret) |
| 2989 | return ret; |
| 2990 | |
| 2991 | *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| 2992 | break; |
| 2993 | case PINCTRL_CONFIG_SCHMITT_CMOS: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2994 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2995 | PINCTRL_SCHCMOS_REG_OFFSET, |
| 2996 | pin); |
| 2997 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 2998 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 2999 | if (ret) |
| 3000 | return ret; |
| 3001 | |
| 3002 | *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| 3003 | break; |
| 3004 | case PINCTRL_CONFIG_DRIVE_STRENGTH: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3005 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3006 | PINCTRL_DRVSTRN0_REG_OFFSET, |
| 3007 | pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3008 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3009 | if (ret) |
| 3010 | return ret; |
| 3011 | |
| 3012 | *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1; |
| 3013 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3014 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3015 | PINCTRL_DRVSTRN1_REG_OFFSET, |
| 3016 | pin); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3017 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3018 | if (ret) |
| 3019 | return ret; |
| 3020 | |
| 3021 | *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| 3022 | break; |
| 3023 | case PINCTRL_CONFIG_VOLTAGE_STATUS: |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3024 | ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3025 | PINCTRL_VOLTAGE_STAT_REG_OFFSET, |
| 3026 | pin); |
| 3027 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3028 | ret = pm_mmio_read(ctrlreg, &val); |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3029 | if (ret) |
| 3030 | return ret; |
| 3031 | |
| 3032 | *value = val & PINCTRL_VOLTAGE_STATUS_MASK; |
| 3033 | break; |
| 3034 | default: |
| 3035 | return PM_RET_ERROR_NOTSUPPORTED; |
| 3036 | } |
| 3037 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 3038 | return PM_RET_SUCCESS; |
Rajan Vaja | 5e139e7 | 2018-01-17 02:39:22 -0800 | [diff] [blame] | 3039 | } |