Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #include <arch.h> |
| 31 | #include <arch_helpers.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 32 | #include <mmio.h> |
| 33 | #include <plat_arm.h> |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 34 | #include <platform_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 35 | #include <xlat_tables.h> |
| 36 | |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 37 | extern const mmap_region_t plat_arm_mmap[]; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 38 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 39 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 40 | #pragma weak plat_get_ns_image_entrypoint |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 41 | #pragma weak plat_arm_get_mmap |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 42 | |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * Macro generating the code for the function setting up the pagetables as per |
| 46 | * the platform memory map & initialize the mmu, for the given exception level |
| 47 | ******************************************************************************/ |
| 48 | #if USE_COHERENT_MEM |
| 49 | #define DEFINE_CONFIGURE_MMU_EL(_el) \ |
| 50 | void arm_configure_mmu_el##_el(unsigned long total_base, \ |
| 51 | unsigned long total_size, \ |
| 52 | unsigned long ro_start, \ |
| 53 | unsigned long ro_limit, \ |
| 54 | unsigned long coh_start, \ |
| 55 | unsigned long coh_limit) \ |
| 56 | { \ |
| 57 | mmap_add_region(total_base, total_base, \ |
| 58 | total_size, \ |
| 59 | MT_MEMORY | MT_RW | MT_SECURE); \ |
| 60 | mmap_add_region(ro_start, ro_start, \ |
| 61 | ro_limit - ro_start, \ |
| 62 | MT_MEMORY | MT_RO | MT_SECURE); \ |
| 63 | mmap_add_region(coh_start, coh_start, \ |
| 64 | coh_limit - coh_start, \ |
| 65 | MT_DEVICE | MT_RW | MT_SECURE); \ |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 66 | mmap_add(plat_arm_get_mmap()); \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 67 | init_xlat_tables(); \ |
| 68 | \ |
| 69 | enable_mmu_el##_el(0); \ |
| 70 | } |
| 71 | #else |
| 72 | #define DEFINE_CONFIGURE_MMU_EL(_el) \ |
| 73 | void arm_configure_mmu_el##_el(unsigned long total_base, \ |
| 74 | unsigned long total_size, \ |
| 75 | unsigned long ro_start, \ |
| 76 | unsigned long ro_limit) \ |
| 77 | { \ |
| 78 | mmap_add_region(total_base, total_base, \ |
| 79 | total_size, \ |
| 80 | MT_MEMORY | MT_RW | MT_SECURE); \ |
| 81 | mmap_add_region(ro_start, ro_start, \ |
| 82 | ro_limit - ro_start, \ |
| 83 | MT_MEMORY | MT_RO | MT_SECURE); \ |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 84 | mmap_add(plat_arm_get_mmap()); \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 85 | init_xlat_tables(); \ |
| 86 | \ |
| 87 | enable_mmu_el##_el(0); \ |
| 88 | } |
| 89 | #endif |
| 90 | |
| 91 | /* Define EL1 and EL3 variants of the function initialising the MMU */ |
| 92 | DEFINE_CONFIGURE_MMU_EL(1) |
| 93 | DEFINE_CONFIGURE_MMU_EL(3) |
| 94 | |
| 95 | |
Soby Mathew | 21f9361 | 2016-03-23 10:11:10 +0000 | [diff] [blame] | 96 | uintptr_t plat_get_ns_image_entrypoint(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 97 | { |
| 98 | return PLAT_ARM_NS_IMAGE_OFFSET; |
| 99 | } |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * Gets SPSR for BL32 entry |
| 103 | ******************************************************************************/ |
| 104 | uint32_t arm_get_spsr_for_bl32_entry(void) |
| 105 | { |
| 106 | /* |
| 107 | * The Secure Payload Dispatcher service is responsible for |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 108 | * setting the SPSR prior to entry into the BL32 image. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 109 | */ |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * Gets SPSR for BL33 entry |
| 115 | ******************************************************************************/ |
| 116 | uint32_t arm_get_spsr_for_bl33_entry(void) |
| 117 | { |
| 118 | unsigned long el_status; |
| 119 | unsigned int mode; |
| 120 | uint32_t spsr; |
| 121 | |
| 122 | /* Figure out what mode we enter the non-secure world in */ |
| 123 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 124 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 125 | |
| 126 | mode = (el_status) ? MODE_EL2 : MODE_EL1; |
| 127 | |
| 128 | /* |
| 129 | * TODO: Consider the possibility of specifying the SPSR in |
| 130 | * the FIP ToC and allowing the platform to have a say as |
| 131 | * well. |
| 132 | */ |
| 133 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 134 | return spsr; |
| 135 | } |
| 136 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 137 | /******************************************************************************* |
| 138 | * Configures access to the system counter timer module. |
| 139 | ******************************************************************************/ |
| 140 | void arm_configure_sys_timer(void) |
| 141 | { |
| 142 | unsigned int reg_val; |
| 143 | |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 144 | #if ARM_CONFIG_CNTACR |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 145 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 146 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 147 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 148 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 149 | #endif /* ARM_CONFIG_CNTACR */ |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 150 | |
| 151 | reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); |
| 152 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 153 | } |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 154 | |
| 155 | /******************************************************************************* |
| 156 | * Returns ARM platform specific memory map regions. |
| 157 | ******************************************************************************/ |
| 158 | const mmap_region_t *plat_arm_get_mmap(void) |
| 159 | { |
| 160 | return plat_arm_mmap; |
| 161 | } |