Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <common/debug.h> |
| 10 | #include <denver.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 11 | #include <errno.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 12 | #include <lib/mmio.h> |
| 13 | #include <mce_private.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 14 | #include <platform_def.h> |
| 15 | #include <t194_nvg.h> |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 16 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 17 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 18 | #define ID_AFR0_EL1_CACHE_OPS_SHIFT 12 |
| 19 | #define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 20 | /* |
| 21 | * Reports the major and minor version of this interface. |
| 22 | * |
| 23 | * NVGDATA[0:31]: SW(R) Minor Version |
| 24 | * NVGDATA[32:63]: SW(R) Major Version |
| 25 | */ |
| 26 | uint64_t nvg_get_version(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 27 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 28 | nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 29 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 30 | return (uint64_t)nvg_get_result(); |
| 31 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 32 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 33 | /* |
| 34 | * Enable the perf per watt mode. |
| 35 | * |
| 36 | * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode |
| 37 | */ |
| 38 | int32_t nvg_enable_power_perf_mode(void) |
| 39 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 40 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 41 | |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | /* |
| 46 | * Disable the perf per watt mode. |
| 47 | * |
| 48 | * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode |
| 49 | */ |
| 50 | int32_t nvg_disable_power_perf_mode(void) |
| 51 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 52 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | /* |
| 58 | * Enable the battery saver mode. |
| 59 | * |
| 60 | * NVGDATA[2]: SW(RW), 1 = enable battery saver mode |
| 61 | */ |
| 62 | int32_t nvg_enable_power_saver_modes(void) |
| 63 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 64 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * Disable the battery saver mode. |
| 71 | * |
| 72 | * NVGDATA[2]: SW(RW), 0 = disable battery saver mode |
| 73 | */ |
| 74 | int32_t nvg_disable_power_saver_modes(void) |
| 75 | { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 76 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 82 | * Set the expected wake time in TSC ticks for the next low-power state the |
| 83 | * core enters. |
| 84 | * |
| 85 | * NVGDATA[0:31]: SW(RW), WAKE_TIME |
| 86 | */ |
| 87 | void nvg_set_wake_time(uint32_t wake_time) |
| 88 | { |
| 89 | /* time (TSC ticks) until the core is expected to get a wake event */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 90 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | /* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 94 | * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and |
| 95 | * SYSTEM_CSTATE values. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 96 | * |
| 97 | * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE |
| 98 | * NVGDATA[7]: SW(W), update cluster flag |
Vignesh Radhakrishnan | 706b9fe | 2017-11-04 16:36:23 -0700 | [diff] [blame] | 99 | * NVGDATA[8:10]: SW(RW), CG_CSTATE |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 100 | * NVGDATA[15]: SW(W), update ccplex flag |
| 101 | * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE |
| 102 | * NVGDATA[23]: SW(W), update system flag |
| 103 | * NVGDATA[31]: SW(W), update wake mask flag |
| 104 | * NVGDATA[32:63]: SW(RW), WAKE_MASK |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 105 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 106 | void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, |
| 107 | uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 108 | { |
| 109 | uint64_t val = 0; |
| 110 | |
| 111 | /* update CLUSTER_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 112 | if (cluster != 0U) { |
| 113 | val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | |
| 114 | CLUSTER_CSTATE_UPDATE_BIT; |
| 115 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 116 | |
| 117 | /* update CCPLEX_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 118 | if (ccplex != 0U) { |
| 119 | val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | |
| 120 | CCPLEX_CSTATE_UPDATE_BIT; |
| 121 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 122 | |
| 123 | /* update SYSTEM_CSTATE? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 124 | if (system != 0U) { |
| 125 | val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | |
| 126 | SYSTEM_CSTATE_UPDATE_BIT; |
| 127 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 128 | |
| 129 | /* update wake mask value? */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 130 | if (update_wake_mask != 0U) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 131 | val |= CSTATE_WAKE_MASK_UPDATE_BIT; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 132 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 133 | |
| 134 | /* set the wake mask */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 135 | val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 136 | |
| 137 | /* set the updated cstate info */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 138 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 141 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 142 | * Return a non-zero value if the CCPLEX is able to enter SC7 |
| 143 | * |
| 144 | * NVGDATA[0]: SW(R), Is allowed result |
| 145 | */ |
| 146 | int32_t nvg_is_sc7_allowed(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 147 | { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 148 | /* issue command to check if SC7 is allowed */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 149 | nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 150 | |
| 151 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 152 | return (int32_t)nvg_get_result(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 153 | } |
| 154 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 155 | /* |
| 156 | * Wake an offlined logical core. Note that a core is offlined by entering |
| 157 | * a C-state where the WAKE_MASK is all 0. |
| 158 | * |
| 159 | * NVGDATA[0:3]: SW(W) logical core to online |
| 160 | */ |
| 161 | int32_t nvg_online_core(uint32_t core) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 162 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 163 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 164 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 165 | /* sanity check the core ID value */ |
| 166 | if (core > (uint32_t)PLATFORM_CORE_COUNT) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 167 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 168 | ret = EINVAL; |
| 169 | } else { |
| 170 | /* get a core online */ |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 171 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, |
| 172 | (uint64_t)core & MCE_CORE_ID_MASK); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 173 | } |
| 174 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 175 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 176 | } |
| 177 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 178 | /* |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 179 | * MC GSC (General Security Carveout) register values are expected to be |
| 180 | * changed by TrustZone ARM code after boot. |
| 181 | * |
| 182 | * NVGDATA[0:15] SW(R) GSC enun |
| 183 | */ |
| 184 | int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) |
| 185 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 186 | int32_t ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 187 | |
| 188 | /* sanity check GSC ID */ |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 189 | if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { |
| 190 | ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 191 | ret = EINVAL; |
| 192 | } else { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 193 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 194 | (uint64_t)gsc_idx); |
| 195 | } |
| 196 | |
| 197 | return ret; |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * Cache clean operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 202 | */ |
| 203 | int32_t nvg_roc_clean_cache(void) |
| 204 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 205 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 206 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 207 | /* check if cache flush through mts is supported */ |
| 208 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 209 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 210 | if (nvg_cache_clean() == 0U) { |
| 211 | ERROR("%s: failed\n", __func__); |
| 212 | ret = EINVAL; |
| 213 | } |
| 214 | } else { |
| 215 | ret = EINVAL; |
| 216 | } |
| 217 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Cache clean and invalidate operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 222 | */ |
| 223 | int32_t nvg_roc_flush_cache(void) |
| 224 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 225 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 226 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 227 | /* check if cache flush through mts is supported */ |
| 228 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 229 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 230 | if (nvg_cache_clean_inval() == 0U) { |
| 231 | ERROR("%s: failed\n", __func__); |
| 232 | ret = EINVAL; |
| 233 | } |
| 234 | } else { |
| 235 | ret = EINVAL; |
| 236 | } |
| 237 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | /* |
| 241 | * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 242 | */ |
| 243 | int32_t nvg_roc_clean_cache_trbits(void) |
| 244 | { |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 245 | int32_t ret = 0; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 246 | |
Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame] | 247 | /* check if cache flush through mts is supported */ |
| 248 | if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & |
| 249 | ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { |
| 250 | if (nvg_cache_inval_all() == 0U) { |
| 251 | ERROR("%s: failed\n", __func__); |
| 252 | ret = EINVAL; |
| 253 | } |
| 254 | } else { |
| 255 | ret = EINVAL; |
| 256 | } |
| 257 | return ret; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | /* |
| 261 | * Set the power state for a core |
| 262 | */ |
| 263 | int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time) |
| 264 | { |
| 265 | int32_t ret = 0; |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 266 | uint64_t val = 0ULL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 267 | |
| 268 | /* check for allowed power state */ |
| 269 | if ((state != (uint32_t)TEGRA_NVG_CORE_C0) && |
| 270 | (state != (uint32_t)TEGRA_NVG_CORE_C1) && |
| 271 | (state != (uint32_t)TEGRA_NVG_CORE_C6) && |
| 272 | (state != (uint32_t)TEGRA_NVG_CORE_C7)) |
| 273 | { |
| 274 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
| 275 | ret = EINVAL; |
| 276 | } else { |
| 277 | /* time (TSC ticks) until the core is expected to get a wake event */ |
| 278 | nvg_set_wake_time(wake_time); |
| 279 | |
| 280 | /* set the core cstate */ |
Steven Kao | 4035902 | 2017-06-22 12:54:06 +0800 | [diff] [blame] | 281 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 282 | write_actlr_el1(val | (uint64_t)state); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | return ret; |
| 286 | } |