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Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
Pankaj Gupta7834b462021-03-25 15:15:52 +05302 * Copyright 2020-2021 NXP
Pankaj Gupta74f7b142020-12-09 14:02:38 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef DCFG_LSCH2_H
9#define DCFG_LSCH2_H
10
11/* dcfg block register offsets and bitfields */
12#define DCFG_PORSR1_OFFSET 0x00
13#define DCFG_DEVDISR1_OFFSET 0x070
Jiafei Pan2f7189b2021-10-21 17:07:18 +080014#define DCFG_DEVDISR2_OFFSET 0x074
15#define DCFG_DEVDISR3_OFFSET 0x078
Pankaj Gupta74f7b142020-12-09 14:02:38 +053016#define DCFG_DEVDISR4_OFFSET 0x07C
17#define DCFG_DEVDISR5_OFFSET 0x080
18#define DCFG_COREDISR_OFFSET 0x094
19#define RCWSR0_OFFSET 0x100
20#define RCWSR5_OFFSET 0x118
21#define DCFG_BOOTLOCPTRL_OFFSET 0x400
22#define DCFG_BOOTLOCPTRH_OFFSET 0x404
23#define DCFG_COREDISABLEDSR_OFFSET 0x990
24#define DCFG_SCRATCH4_OFFSET 0x20C
25#define DCFG_SVR_OFFSET 0x0A4
26#define DCFG_BRR_OFFSET 0x0E4
27
28#define DCFG_RSTCR_OFFSET 0x0B0
29#define RSTCR_RESET_REQ 0x2
30
31#define DCFG_RSTRQSR1_OFFSET 0x0C8
32#define DCFG_RSTRQMR1_OFFSET 0x0C0
33
Jiafei Pan2f7189b2021-10-21 17:07:18 +080034/* PORSR1 bit mask */
35#define PORSR1_RCW_MASK 0xff800000
36#define PORSR1_RCW_SHIFT 23
37
Pankaj Gupta74f7b142020-12-09 14:02:38 +053038/* DCFG DCSR Macros */
39#define DCFG_DCSR_PORCR1_OFFSET 0x0
40
41#define SVR_MFR_ID_MASK 0xF0000000
42#define SVR_MFR_ID_SHIFT 28
Jiafei Panb27ac802021-07-20 17:14:32 +080043#define SVR_DEV_ID_MASK 0xFFF0000
Pankaj Gupta74f7b142020-12-09 14:02:38 +053044#define SVR_DEV_ID_SHIFT 16
Jiafei Panb27ac802021-07-20 17:14:32 +080045#define SVR_PERSONALITY_MASK 0xFF00
46#define SVR_PERSONALITY_SHIFT 8
Pankaj Gupta74f7b142020-12-09 14:02:38 +053047#define SVR_SEC_MASK 0x100
48#define SVR_SEC_SHIFT 8
49#define SVR_MAJ_VER_MASK 0xF0
50#define SVR_MAJ_VER_SHIFT 4
51#define SVR_MIN_VER_MASK 0xF
Jiafei Pan2f7189b2021-10-21 17:07:18 +080052#define SVR_MINOR_VER_0 0x00
53#define SVR_MINOR_VER_1 0x01
Pankaj Gupta74f7b142020-12-09 14:02:38 +053054
55#define DISR5_DDRC1_MASK 0x1
56#define DISR5_OCRAM_MASK 0x40
57
Elyes Haouas2be03c02023-02-13 09:14:48 +010058/* DCFG registers bit masks */
Pankaj Gupta74f7b142020-12-09 14:02:38 +053059#define RCWSR0_SYS_PLL_RAT_SHIFT 25
60#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
61#define RCWSR0_MEM_PLL_RAT_SHIFT 16
62#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
63#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
64#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
65
66#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
67#define RCWSR_SBEN_MASK 0x1
68#define RCWSR_SBEN_SHIFT 21
69
70/* RCW SRC NAND */
71#define RCW_SRC_NAND_MASK (0x100)
72#define RCW_SRC_NAND_VAL (0x100)
73#define NAND_RESERVED_MASK (0xFC)
74#define NAND_RESERVED_1 (0x0)
75#define NAND_RESERVED_2 (0x80)
76
77/* RCW SRC NOR */
78#define RCW_SRC_NOR_MASK (0x1F0)
79#define NOR_8B_VAL (0x10)
80#define NOR_16B_VAL (0x20)
81#define SD_VAL (0x40)
82#define QSPI_VAL1 (0x44)
83#define QSPI_VAL2 (0x45)
84
85#endif /* DCFG_LSCH2_H */