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Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
Pankaj Gupta7834b462021-03-25 15:15:52 +05302 * Copyright 2020-2021 NXP
Pankaj Gupta74f7b142020-12-09 14:02:38 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef DCFG_LSCH2_H
9#define DCFG_LSCH2_H
10
11/* dcfg block register offsets and bitfields */
12#define DCFG_PORSR1_OFFSET 0x00
13#define DCFG_DEVDISR1_OFFSET 0x070
14#define DCFG_DEVDISR4_OFFSET 0x07C
15#define DCFG_DEVDISR5_OFFSET 0x080
16#define DCFG_COREDISR_OFFSET 0x094
17#define RCWSR0_OFFSET 0x100
18#define RCWSR5_OFFSET 0x118
19#define DCFG_BOOTLOCPTRL_OFFSET 0x400
20#define DCFG_BOOTLOCPTRH_OFFSET 0x404
21#define DCFG_COREDISABLEDSR_OFFSET 0x990
22#define DCFG_SCRATCH4_OFFSET 0x20C
23#define DCFG_SVR_OFFSET 0x0A4
24#define DCFG_BRR_OFFSET 0x0E4
25
26#define DCFG_RSTCR_OFFSET 0x0B0
27#define RSTCR_RESET_REQ 0x2
28
29#define DCFG_RSTRQSR1_OFFSET 0x0C8
30#define DCFG_RSTRQMR1_OFFSET 0x0C0
31
32/* DCFG DCSR Macros */
33#define DCFG_DCSR_PORCR1_OFFSET 0x0
34
35#define SVR_MFR_ID_MASK 0xF0000000
36#define SVR_MFR_ID_SHIFT 28
37#define SVR_FAMILY_MASK 0xF000000
38#define SVR_FAMILY_SHIFT 24
39#define SVR_DEV_ID_MASK 0x3F0000
40#define SVR_DEV_ID_SHIFT 16
41#define SVR_PERSONALITY_MASK 0x3E00
42#define SVR_PERSONALITY_SHIFT 9
43#define SVR_SEC_MASK 0x100
44#define SVR_SEC_SHIFT 8
45#define SVR_MAJ_VER_MASK 0xF0
46#define SVR_MAJ_VER_SHIFT 4
47#define SVR_MIN_VER_MASK 0xF
48
49#define DISR5_DDRC1_MASK 0x1
50#define DISR5_OCRAM_MASK 0x40
51
52/* DCFG regsiters bit masks */
53#define RCWSR0_SYS_PLL_RAT_SHIFT 25
54#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
55#define RCWSR0_MEM_PLL_RAT_SHIFT 16
56#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
57#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
58#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
59
60#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
61#define RCWSR_SBEN_MASK 0x1
62#define RCWSR_SBEN_SHIFT 21
63
64/* RCW SRC NAND */
65#define RCW_SRC_NAND_MASK (0x100)
66#define RCW_SRC_NAND_VAL (0x100)
67#define NAND_RESERVED_MASK (0xFC)
68#define NAND_RESERVED_1 (0x0)
69#define NAND_RESERVED_2 (0x80)
70
71/* RCW SRC NOR */
72#define RCW_SRC_NOR_MASK (0x1F0)
73#define NOR_8B_VAL (0x10)
74#define NOR_16B_VAL (0x20)
75#define SD_VAL (0x40)
76#define QSPI_VAL1 (0x44)
77#define QSPI_VAL2 (0x45)
78
79#endif /* DCFG_LSCH2_H */