Yann Gautier | bb836ee | 2018-07-16 17:55:07 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef STPMU1_H |
| 8 | #define STPMU1_H |
Yann Gautier | bb836ee | 2018-07-16 17:55:07 +0200 | [diff] [blame] | 9 | |
| 10 | #include <stm32_i2c.h> |
| 11 | #include <utils_def.h> |
| 12 | |
| 13 | #define TURN_ON_REG 0x1U |
| 14 | #define TURN_OFF_REG 0x2U |
| 15 | #define ICC_LDO_TURN_OFF_REG 0x3U |
| 16 | #define ICC_BUCK_TURN_OFF_REG 0x4U |
| 17 | #define RESET_STATUS_REG 0x5U |
| 18 | #define VERSION_STATUS_REG 0x6U |
| 19 | #define MAIN_CONTROL_REG 0x10U |
| 20 | #define PADS_PULL_REG 0x11U |
| 21 | #define BUCK_PULL_DOWN_REG 0x12U |
| 22 | #define LDO14_PULL_DOWN_REG 0x13U |
| 23 | #define LDO56_PULL_DOWN_REG 0x14U |
| 24 | #define VIN_CONTROL_REG 0x15U |
| 25 | #define PONKEY_TIMER_REG 0x16U |
| 26 | #define MASK_RANK_BUCK_REG 0x17U |
| 27 | #define MASK_RESET_BUCK_REG 0x18U |
| 28 | #define MASK_RANK_LDO_REG 0x19U |
| 29 | #define MASK_RESET_LDO_REG 0x1AU |
| 30 | #define WATCHDOG_CONTROL_REG 0x1BU |
| 31 | #define WATCHDOG_TIMER_REG 0x1CU |
| 32 | #define BUCK_ICC_TURNOFF_REG 0x1DU |
| 33 | #define LDO_ICC_TURNOFF_REG 0x1EU |
| 34 | #define BUCK_APM_CONTROL_REG 0x1FU |
| 35 | #define BUCK1_CONTROL_REG 0x20U |
| 36 | #define BUCK2_CONTROL_REG 0x21U |
| 37 | #define BUCK3_CONTROL_REG 0x22U |
| 38 | #define BUCK4_CONTROL_REG 0x23U |
| 39 | #define VREF_DDR_CONTROL_REG 0x24U |
| 40 | #define LDO1_CONTROL_REG 0x25U |
| 41 | #define LDO2_CONTROL_REG 0x26U |
| 42 | #define LDO3_CONTROL_REG 0x27U |
| 43 | #define LDO4_CONTROL_REG 0x28U |
| 44 | #define LDO5_CONTROL_REG 0x29U |
| 45 | #define LDO6_CONTROL_REG 0x2AU |
| 46 | #define BUCK1_PWRCTRL_REG 0x30U |
| 47 | #define BUCK2_PWRCTRL_REG 0x31U |
| 48 | #define BUCK3_PWRCTRL_REG 0x32U |
| 49 | #define BUCK4_PWRCTRL_REG 0x33U |
| 50 | #define VREF_DDR_PWRCTRL_REG 0x34U |
| 51 | #define LDO1_PWRCTRL_REG 0x35U |
| 52 | #define LDO2_PWRCTRL_REG 0x36U |
| 53 | #define LDO3_PWRCTRL_REG 0x37U |
| 54 | #define LDO4_PWRCTRL_REG 0x38U |
| 55 | #define LDO5_PWRCTRL_REG 0x39U |
| 56 | #define LDO6_PWRCTRL_REG 0x3AU |
| 57 | #define FREQUENCY_SPREADING_REG 0x3BU |
| 58 | #define USB_CONTROL_REG 0x40U |
| 59 | #define ITLATCH1_REG 0x50U |
| 60 | #define ITLATCH2_REG 0x51U |
| 61 | #define ITLATCH3_REG 0x52U |
| 62 | #define ITLATCH4_REG 0x53U |
| 63 | #define ITSETLATCH1_REG 0x60U |
| 64 | #define ITSETLATCH2_REG 0x61U |
| 65 | #define ITSETLATCH3_REG 0x62U |
| 66 | #define ITSETLATCH4_REG 0x63U |
| 67 | #define ITCLEARLATCH1_REG 0x70U |
| 68 | #define ITCLEARLATCH2_REG 0x71U |
| 69 | #define ITCLEARLATCH3_REG 0x72U |
| 70 | #define ITCLEARLATCH4_REG 0x73U |
| 71 | #define ITMASK1_REG 0x80U |
| 72 | #define ITMASK2_REG 0x81U |
| 73 | #define ITMASK3_REG 0x82U |
| 74 | #define ITMASK4_REG 0x83U |
| 75 | #define ITSETMASK1_REG 0x90U |
| 76 | #define ITSETMASK2_REG 0x91U |
| 77 | #define ITSETMASK3_REG 0x92U |
| 78 | #define ITSETMASK4_REG 0x93U |
| 79 | #define ITCLEARMASK1_REG 0xA0U |
| 80 | #define ITCLEARMASK2_REG 0xA1U |
| 81 | #define ITCLEARMASK3_REG 0xA2U |
| 82 | #define ITCLEARMASK4_REG 0xA3U |
| 83 | #define ITSOURCE1_REG 0xB0U |
| 84 | #define ITSOURCE2_REG 0xB1U |
| 85 | #define ITSOURCE3_REG 0xB2U |
| 86 | #define ITSOURCE4_REG 0xB3U |
| 87 | #define LDO_VOLTAGE_MASK 0x7CU |
| 88 | #define BUCK_VOLTAGE_MASK 0xFCU |
| 89 | #define LDO_BUCK_VOLTAGE_SHIFT 2 |
| 90 | #define LDO_ENABLE_MASK 0x01U |
| 91 | #define BUCK_ENABLE_MASK 0x01U |
| 92 | #define BUCK_HPLP_ENABLE_MASK 0x02U |
| 93 | #define LDO_HPLP_ENABLE_MASK 0x02U |
| 94 | #define LDO_BUCK_HPLP_SHIFT 1 |
| 95 | #define LDO_BUCK_RANK_MASK 0x01U |
| 96 | #define LDO_BUCK_RESET_MASK 0x01U |
| 97 | #define LDO_BUCK_PULL_DOWN_MASK 0x03U |
| 98 | |
| 99 | /* Main PMIC Control Register (MAIN_CONTROL_REG) */ |
| 100 | #define ICC_EVENT_ENABLED BIT(4) |
| 101 | #define PWRCTRL_POLARITY_HIGH BIT(3) |
| 102 | #define PWRCTRL_PIN_VALID BIT(2) |
| 103 | #define RESTART_REQUEST_ENABLED BIT(1) |
| 104 | #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) |
| 105 | |
| 106 | /* Main PMIC PADS Control Register (PADS_PULL_REG) */ |
| 107 | #define WAKEUP_DETECTOR_DISABLED BIT(4) |
| 108 | #define PWRCTRL_PD_ACTIVE BIT(3) |
| 109 | #define PWRCTRL_PU_ACTIVE BIT(2) |
| 110 | #define WAKEUP_PD_ACTIVE BIT(1) |
| 111 | #define PONKEY_PU_ACTIVE BIT(0) |
| 112 | |
| 113 | /* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */ |
| 114 | #define SWIN_DETECTOR_ENABLED BIT(7) |
| 115 | #define SWOUT_DETECTOR_ENABLED BIT(6) |
| 116 | #define VINLOW_HYST_MASK 0x3 |
| 117 | #define VINLOW_HYST_SHIFT 4 |
| 118 | #define VINLOW_THRESHOLD_MASK 0x7 |
| 119 | #define VINLOW_THRESHOLD_SHIFT 1 |
| 120 | #define VINLOW_ENABLED 0x01 |
| 121 | #define VINLOW_CTRL_REG_MASK 0xFF |
| 122 | |
| 123 | /* USB Control Register */ |
| 124 | #define BOOST_OVP_DISABLED BIT(7) |
| 125 | #define VBUS_OTG_DETECTION_DISABLED BIT(6) |
| 126 | #define OCP_LIMIT_HIGH BIT(3) |
| 127 | #define SWIN_SWOUT_ENABLED BIT(2) |
| 128 | #define USBSW_OTG_SWITCH_ENABLED BIT(1) |
| 129 | |
| 130 | int stpmu1_switch_off(void); |
| 131 | int stpmu1_register_read(uint8_t register_id, uint8_t *value); |
| 132 | int stpmu1_register_write(uint8_t register_id, uint8_t value); |
| 133 | int stpmu1_register_update(uint8_t register_id, uint8_t value, uint8_t mask); |
| 134 | int stpmu1_regulator_enable(const char *name); |
| 135 | int stpmu1_regulator_disable(const char *name); |
| 136 | uint8_t stpmu1_is_regulator_enabled(const char *name); |
| 137 | int stpmu1_regulator_voltage_set(const char *name, uint16_t millivolts); |
| 138 | void stpmu1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr); |
| 139 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 140 | #endif /* STPMU1_H */ |