Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CPU_DATA_H__ |
| 8 | #define __CPU_DATA_H__ |
| 9 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 10 | #ifdef AARCH32 |
| 11 | |
| 12 | #if CRASH_REPORTING |
| 13 | #error "Crash reporting is not supported in AArch32" |
| 14 | #endif |
| 15 | #define CPU_DATA_CPU_OPS_PTR 0x0 |
| 16 | |
| 17 | #else /* AARCH32 */ |
| 18 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 19 | /* Offsets for the cpu_data structure */ |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 20 | #define CPU_DATA_CRASH_BUF_OFFSET 0x18 |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 21 | /* need enough space in crash buffer to save 8 registers */ |
| 22 | #define CPU_DATA_CRASH_BUF_SIZE 64 |
| 23 | #define CPU_DATA_CPU_OPS_PTR 0x10 |
| 24 | |
| 25 | #endif /* AARCH32 */ |
| 26 | |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 27 | #if CRASH_REPORTING |
| 28 | #define CPU_DATA_LOG2SIZE 7 |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 29 | #define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \ |
| 30 | CPU_DATA_CRASH_BUF_SIZE) |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 31 | #else |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 32 | #define CPU_DATA_LOG2SIZE 6 |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 33 | #define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 34 | #endif |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 35 | |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 36 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 37 | /* Temporary space to store PMF timestamps from assembly code */ |
| 38 | #define CPU_DATA_PMF_TS_COUNT 1 |
| 39 | #define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END |
| 40 | #define CPU_DATA_PMF_TS0_IDX 0 |
| 41 | #endif |
| 42 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 43 | #ifndef __ASSEMBLY__ |
| 44 | |
| 45 | #include <arch_helpers.h> |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 46 | #include <cassert.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 47 | #include <platform_def.h> |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 48 | #include <psci.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 49 | #include <stdint.h> |
| 50 | |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 51 | /* Offsets for the cpu_data structure */ |
| 52 | #define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ |
| 53 | (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info) |
| 54 | |
| 55 | #if PLAT_PCPU_DATA_SIZE |
| 56 | #define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\ |
| 57 | (cpu_data_t, platform_cpu_data) |
| 58 | #endif |
| 59 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 60 | /******************************************************************************* |
| 61 | * Function & variable prototypes |
| 62 | ******************************************************************************/ |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * Cache of frequently used per-cpu data: |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 66 | * Pointers to non-secure and secure security state contexts |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 67 | * Address of the crash stack |
| 68 | * It is aligned to the cache line boundary to allow efficient concurrent |
| 69 | * manipulation of these pointers on different cpus |
| 70 | * |
| 71 | * TODO: Add other commonly used variables to this (tf_issues#90) |
| 72 | * |
| 73 | * The data structure and the _cpu_data accessors should not be used directly |
| 74 | * by components that have per-cpu members. The member access macros should be |
| 75 | * used for this. |
| 76 | ******************************************************************************/ |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 77 | typedef struct cpu_data { |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 78 | #ifndef AARCH32 |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 79 | void *cpu_context[2]; |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 80 | #endif |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 81 | uintptr_t cpu_ops_ptr; |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 82 | #if CRASH_REPORTING |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 83 | u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 84 | #endif |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 85 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 86 | uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; |
| 87 | #endif |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 88 | struct psci_cpu_data psci_svc_cpu_data; |
| 89 | #if PLAT_PCPU_DATA_SIZE |
| 90 | uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; |
| 91 | #endif |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 92 | } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; |
| 93 | |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 94 | #if CRASH_REPORTING |
| 95 | /* verify assembler offsets match data structures */ |
| 96 | CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof |
| 97 | (cpu_data_t, crash_buf), |
| 98 | assert_cpu_data_crash_stack_offset_mismatch); |
| 99 | #endif |
| 100 | |
| 101 | CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t), |
| 102 | assert_cpu_data_log2size_mismatch); |
| 103 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 104 | CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof |
| 105 | (cpu_data_t, cpu_ops_ptr), |
| 106 | assert_cpu_data_cpu_ops_ptr_offset_mismatch); |
| 107 | |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 108 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 109 | CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof |
| 110 | (cpu_data_t, cpu_data_pmf_ts[0]), |
| 111 | assert_cpu_data_pmf_ts0_offset_mismatch); |
| 112 | #endif |
| 113 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 114 | struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 115 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 116 | #ifndef AARCH32 |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 117 | /* Return the cpu_data structure for the current CPU. */ |
| 118 | static inline struct cpu_data *_cpu_data(void) |
| 119 | { |
| 120 | return (cpu_data_t *)read_tpidr_el3(); |
| 121 | } |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 122 | #else |
| 123 | struct cpu_data *_cpu_data(void); |
| 124 | #endif |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 125 | |
| 126 | /************************************************************************** |
| 127 | * APIs for initialising and accessing per-cpu data |
| 128 | *************************************************************************/ |
| 129 | |
| 130 | void init_cpu_data_ptr(void); |
Vikram Kanigiri | 9b38fc8 | 2015-01-29 18:27:38 +0000 | [diff] [blame] | 131 | void init_cpu_ops(void); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 132 | |
| 133 | #define get_cpu_data(_m) _cpu_data()->_m |
| 134 | #define set_cpu_data(_m, _v) _cpu_data()->_m = _v |
| 135 | #define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m |
| 136 | #define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 137 | |
Soby Mathew | 24ab34f | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 138 | #define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \ |
Achin Gupta | e4b9fa4 | 2014-07-25 14:47:05 +0100 | [diff] [blame] | 139 | &(_cpu_data()->_m), \ |
| 140 | sizeof(_cpu_data()->_m)) |
Soby Mathew | 24ab34f | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 141 | #define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 142 | &(_cpu_data()->_m), \ |
| 143 | sizeof(_cpu_data()->_m)) |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 144 | #define flush_cpu_data_by_index(_ix, _m) \ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 145 | flush_dcache_range((uintptr_t) \ |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 146 | &(_cpu_data_by_index(_ix)->_m), \ |
| 147 | sizeof(_cpu_data_by_index(_ix)->_m)) |
Achin Gupta | e4b9fa4 | 2014-07-25 14:47:05 +0100 | [diff] [blame] | 148 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 149 | |
| 150 | #endif /* __ASSEMBLY__ */ |
| 151 | #endif /* __CPU_DATA_H__ */ |