Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef QOS_COMMON_H |
| 8 | #define QOS_COMMON_H |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 9 | |
| 10 | #define RCAR_REF_DEFAULT (0U) |
| 11 | |
Marek Vasut | 48cc693 | 2018-12-12 16:35:00 +0100 | [diff] [blame] | 12 | /* define used for get_refperiod. */ |
| 13 | /* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ |
| 14 | /* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */ |
| 15 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ |
| 16 | #define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */ |
| 17 | #else /* REF option */ |
| 18 | #define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */ |
| 19 | #endif |
| 20 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 21 | #if (RCAR_LSI == RCAR_E3) |
| 22 | /* define used for E3 */ |
| 23 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */ |
| 24 | #define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */ |
| 25 | #else /* REF 7.8usec */ |
| 26 | #define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */ |
| 27 | #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ |
| 28 | |
| 29 | #define OPERATING_FREQ_E3 (266U) /* MHz */ |
| 30 | #define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U) |
Marek Vasut | 48cc693 | 2018-12-12 16:35:00 +0100 | [diff] [blame] | 31 | /* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 32 | #endif |
| 33 | |
| 34 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) |
| 35 | /* define used for M3N */ |
| 36 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 37 | #define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 38 | #else /* REF 3.9usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 39 | #define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 40 | #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ |
| 41 | |
| 42 | #define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U) |
| 43 | #define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 44 | #endif |
| 45 | |
| 46 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) |
| 47 | /* define used for H3 */ |
| 48 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 49 | #define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 50 | #else /* REF 3.9usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 51 | #define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 52 | #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ |
| 53 | |
| 54 | #define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U) |
| 55 | #define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 56 | |
| 57 | /* define used for H3 Cut 30 */ |
| 58 | #define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */ |
| 59 | #define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U) |
| 60 | #define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 61 | |
| 62 | #endif |
| 63 | |
| 64 | #if (RCAR_LSI == RCAR_H3N) |
| 65 | /* define used for H3N */ |
| 66 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 67 | #define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 68 | #else /* REF 3.9usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 69 | #define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 70 | #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ |
| 71 | |
| 72 | #define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U) |
| 73 | #define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 74 | |
| 75 | #endif |
| 76 | |
| 77 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) |
| 78 | /* define used for M3 */ |
| 79 | #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 80 | #define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */ |
| 81 | #define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 82 | #else /* REF 3.9usec */ |
Yoshifumi Hosoya | 2a9e1ac | 2019-03-11 15:15:25 +0900 | [diff] [blame] | 83 | #define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */ |
| 84 | #define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 85 | #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ |
| 86 | |
| 87 | #define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U) |
Marek Vasut | 3af2005 | 2019-02-25 14:57:08 +0100 | [diff] [blame] | 88 | #define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 89 | #define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
Marek Vasut | 3af2005 | 2019-02-25 14:57:08 +0100 | [diff] [blame] | 90 | #define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 91 | #endif |
| 92 | |
| 93 | #define OPERATING_FREQ (400U) /* MHz */ |
| 94 | #define BASE_SUB_SLOT_NUM (0x6U) |
| 95 | #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ |
| 96 | |
| 97 | #define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ |
| 98 | |
| 99 | #define SL_INIT_REFFSSLOT (0x3U << 24U) |
| 100 | #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) |
| 101 | #define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U) |
| 102 | |
| 103 | static inline void io_write_32(uintptr_t addr, uint32_t value) |
| 104 | { |
| 105 | *(volatile uint32_t *)addr = value; |
| 106 | } |
| 107 | |
| 108 | static inline uint32_t io_read_32(uintptr_t addr) |
| 109 | { |
| 110 | return *(volatile uint32_t *)addr; |
| 111 | } |
| 112 | |
| 113 | static inline void io_write_64(uintptr_t addr, uint64_t value) |
| 114 | { |
| 115 | *(volatile uint64_t *)addr = value; |
| 116 | } |
| 117 | |
| 118 | typedef struct { |
| 119 | uintptr_t addr; |
| 120 | uint64_t value; |
| 121 | } mstat_slot_t; |
| 122 | |
| 123 | extern uint32_t qos_init_ddr_ch; |
| 124 | extern uint8_t qos_init_ddr_phyvalid; |
| 125 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 126 | #endif /* QOS_COMMON_H */ |