commit 2a9e1ac7e0753e42281c8729ef3a2ad27d03ce91
author Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Mon Mar 11 15:15:25 2019 +0900
committer Marek Vasut <marek.vasut+renesas@gmail.com> Thu Apr 11 12:57:00 2019 +0200
tree cfba2fcbe1e511ec33d69d80873bbd67533e8921
parent 908b1ca61ae6c243c86b4dd43e36a44d0fe5f122

rcar_gen3: drivers: qos: change subslot cycle

Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.

 [IPL/QoS]
 - Update H3 Ver.2.0 QoS setting rev.0.21.
 - Update H3 Ver.3.0 QoS setting rev.0.11.
 - Update M3 Ver.1.1 QoS setting rev.0.19.
 - Update M3 Ver.3.0 QoS setting rev.0.02.
 - Update M3N Ver.1.1 QoS setting rev.0.09.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5

drivers/staging/renesas/rcar/qos/qos_common.h

diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
index 89dcf06..c3a83ac 100644
--- a/drivers/staging/renesas/rcar/qos/qos_common.h
+++ b/drivers/staging/renesas/rcar/qos/qos_common.h
@@ -34,9 +34,9 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
 /* define used for M3N */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3N		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_M3N		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3N		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_M3N		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_M3N		(SUB_SLOT_CYCLE_M3N -1U)
@@ -46,9 +46,9 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
 /* define used for H3 */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3_20		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_H3_20		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3_20		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_H3_20		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_H3_20		(SUB_SLOT_CYCLE_H3_20 -1U)
@@ -64,9 +64,9 @@
 #if (RCAR_LSI == RCAR_H3N)
 /* define used for H3N */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3N		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_H3N		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3N		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_H3N		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_H3N		(SUB_SLOT_CYCLE_H3N -1U)
@@ -77,11 +77,11 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
 /* define used for M3 */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3_11		(0x84U)	/* 132 */
-#define SUB_SLOT_CYCLE_M3_30		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_M3_11		(0x7EU)	/* 126 */
+#define SUB_SLOT_CYCLE_M3_30		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3_11		(0x108U)	/* 264 */
-#define SUB_SLOT_CYCLE_M3_30		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_M3_11		(0xFCU)	/* 252 */
+#define SUB_SLOT_CYCLE_M3_30		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_M3_11		(SUB_SLOT_CYCLE_M3_11 -1U)