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Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00001/*
Antonio Nino Diaz5f475792018-10-15 14:58:11 +01002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00005 */
6
Antonio Nino Diaz5f475792018-10-15 14:58:11 +01007#ifndef TZC_DMC500_H
8#define TZC_DMC500_H
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +00009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <drivers/arm/tzc_common.h>
11#include <lib/utils_def.h>
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000012
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010013#define SI_STATUS_OFFSET U(0x000)
14#define SI_STATE_CTRL_OFFSET U(0x030)
15#define SI_FLUSH_CTRL_OFFSET U(0x034)
16#define SI_INT_CONTROL_OFFSET U(0x048)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000017
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010018#define SI_INT_STATUS_OFFSET U(0x004)
19#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET U(0x008)
20#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET U(0x00c)
21#define SI_FAIL_CONTROL_OFFSET U(0x010)
22#define SI_FAIL_ID_OFFSET U(0x014)
23#define SI_INT_CLR_OFFSET U(0x04c)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000024
25/*
26 * DMC-500 has 2 system interfaces each having a similar set of regs
27 * to configure each interface.
28 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010029#define SI0_BASE U(0x0000)
30#define SI1_BASE U(0x0200)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000031
32/* Bit positions of SIx_SI_STATUS */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010033#define SI_EMPTY_SHIFT 1
34#define SI_STALL_ACK_SHIFT 0
35#define SI_EMPTY_MASK U(0x01)
36#define SI_STALL_ACK_MASK U(0x01)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000037
38/* Bit positions of SIx_SI_INT_STATUS */
39#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
40#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16
41#define PMU_REQ_INT_STATUS_SHIFT 2
42#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
43#define FAILED_ACCESS_INT_STATUS_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010044#define PMU_REQ_INT_OVERFLOW_STATUS_MASK U(0x1)
45#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK U(0x1)
46#define PMU_REQ_INT_STATUS_MASK U(0x1)
47#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK U(0x1)
48#define FAILED_ACCESS_INT_STATUS_MASK U(0x1)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000049
50/* Bit positions of SIx_TZ_FAIL_CONTROL */
51#define DIRECTION_SHIFT 24
52#define NON_SECURE_SHIFT 21
53#define PRIVILEGED_SHIFT 20
54#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
55#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010056#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 1
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000057#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010058#define DIRECTION_MASK U(0x1)
59#define NON_SECURE_MASK U(0x1)
60#define PRIVILEGED_MASK U(0x1)
61#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK U(0x1)
62#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK U(0x1)
63#define FAILED_ACCESS_INT_TZ_FAIL_MASK U(0x1)
64#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK U(0x1)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000065
66/* Bit positions of SIx_FAIL_STATUS */
67#define FAIL_ID_VNET_SHIFT 24
68#define FAIL_ID_ID_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010069#define FAIL_ID_VNET_MASK U(0xf)
70#define FAIL_ID_ID_MASK U(0xffffff)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000071
72/* Bit positions of SIx_SI_STATE_CONTRL */
73#define SI_STALL_REQ_GO 0x0
74#define SI_STALL_REQ_STALL 0x1
75
76/* Bit positions of SIx_SI_FLUSH_CONTROL */
77#define SI_FLUSH_REQ_INACTIVE 0x0
78#define SI_FLUSH_REQ_ACTIVE 0x1
79#define SI_FLUSH_REQ_MASK 0x1
80
81/* Bit positions of SIx_SI_INT_CONTROL */
82#define PMU_REQ_INT_EN_SHIFT 2
83#define OVERLAP_DETECT_INT_EN_SHIFT 1
84#define FAILED_ACCESS_INT_EN_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010085#define PMU_REQ_INT_EN_MASK U(0x1)
86#define OVERLAP_DETECT_INT_EN_MASK U(0x1)
87#define FAILED_ACCESS_INT_EN_MASK U(0x1)
88#define PMU_REQ_INT_EN U(0x1)
89#define OVERLAP_DETECT_INT_EN U(0x1)
90#define FAILED_ACCESS_INT_EN U(0x1)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +000091
92/* Bit positions of SIx_SI_INT_CLR */
93#define PMU_REQ_OFLOW_CLR_SHIFT 18
94#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
95#define PMU_REQ_INT_CLR_SHIFT 2
96#define FAILED_ACCESS_INT_CLR_SHIFT 0
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010097#define PMU_REQ_OFLOW_CLR_MASK U(0x1)
98#define FAILED_ACCESS_OFLOW_CLR_MASK U(0x1)
99#define PMU_REQ_INT_CLR_MASK U(0x1)
100#define FAILED_ACCESS_INT_CLR_MASK U(0x1)
101#define PMU_REQ_OFLOW_CLR U(0x1)
102#define FAILED_ACCESS_OFLOW_CLR U(0x1)
103#define PMU_REQ_INT_CLR U(0x1)
104#define FAILED_ACCESS_INT_CLR U(0x1)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000105
106/* Macro to get the correct base register for a system interface */
107#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
108
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100109#define MAX_SYS_IF_COUNT U(2)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000110#define MAX_REGION_VAL 8
111
112/* DMC-500 supports striping across a max of 4 DMC instances */
113#define MAX_DMC_COUNT 4
114
115/* Consist of part_number_1 and part_number_0 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100116#define DMC500_PERIPHERAL_ID U(0x0450)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000117
118/* Filter enable bits in a TZC */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100119#define TZC_DMC500_REGION_ATTR_F_EN_MASK U(0x1)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000120
121/* Length of registers for configuring each region */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100122#define TZC_DMC500_REGION_SIZE U(0x018)
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000123
124#ifndef __ASSEMBLY__
125
126#include <stdint.h>
127
128/*
129 * Contains the base addresses of all the DMC instances.
130 */
131typedef struct tzc_dmc500_driver_data {
132 uintptr_t dmc_base[MAX_DMC_COUNT];
133 int dmc_count;
Amit Daniel Kachhap779e4fc2018-04-09 16:53:01 +0530134 unsigned int sys_if_count;
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000135} tzc_dmc500_driver_data_t;
136
137void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100138void tzc_dmc500_configure_region0(unsigned int sec_attr,
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000139 unsigned int nsaid_permissions);
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100140void tzc_dmc500_configure_region(unsigned int region_no,
Yatharth Kocharfc719752016-04-08 14:40:44 +0100141 unsigned long long region_base,
142 unsigned long long region_top,
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100143 unsigned int sec_attr,
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000144 unsigned int nsaid_permissions);
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100145void tzc_dmc500_set_action(unsigned int action);
Vikram Kanigiri411ac8f2016-01-29 11:37:04 +0000146void tzc_dmc500_config_complete(void);
147int tzc_dmc500_verify_complete(void);
148
149
150#endif /* __ASSEMBLY__ */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100151#endif /* TZC_DMC500_H */