tzc: Fix MISRA defects
The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.
The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.
Also, fix some address definitions in arm_def.h.
Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/include/drivers/arm/tzc_dmc500.h b/include/drivers/arm/tzc_dmc500.h
index ff58a27..df6e7f9 100644
--- a/include/drivers/arm/tzc_dmc500.h
+++ b/include/drivers/arm/tzc_dmc500.h
@@ -1,38 +1,39 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TZC_DMC500_H__
-#define __TZC_DMC500_H__
+#ifndef TZC_DMC500_H
+#define TZC_DMC500_H
#include <tzc_common.h>
+#include <utils_def.h>
-#define SI_STATUS_OFFSET 0x000
-#define SI_STATE_CTRL_OFFSET 0x030
-#define SI_FLUSH_CTRL_OFFSET 0x034
-#define SI_INT_CONTROL_OFFSET 0x048
+#define SI_STATUS_OFFSET U(0x000)
+#define SI_STATE_CTRL_OFFSET U(0x030)
+#define SI_FLUSH_CTRL_OFFSET U(0x034)
+#define SI_INT_CONTROL_OFFSET U(0x048)
-#define SI_INT_STATUS_OFFSET 0x004
-#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008
-#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c
-#define SI_FAIL_CONTROL_OFFSET 0x010
-#define SI_FAIL_ID_OFFSET 0x014
-#define SI_INT_CLR_OFFSET 0x04c
+#define SI_INT_STATUS_OFFSET U(0x004)
+#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET U(0x008)
+#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET U(0x00c)
+#define SI_FAIL_CONTROL_OFFSET U(0x010)
+#define SI_FAIL_ID_OFFSET U(0x014)
+#define SI_INT_CLR_OFFSET U(0x04c)
/*
* DMC-500 has 2 system interfaces each having a similar set of regs
* to configure each interface.
*/
-#define SI0_BASE 0x0000
-#define SI1_BASE 0x0200
+#define SI0_BASE U(0x0000)
+#define SI1_BASE U(0x0200)
/* Bit positions of SIx_SI_STATUS */
-#define SI_EMPTY_SHIFT 0x01
-#define SI_STALL_ACK_SHIFT 0x00
-#define SI_EMPTY_MASK 0x01
-#define SI_STALL_ACK_MASK 0x01
+#define SI_EMPTY_SHIFT 1
+#define SI_STALL_ACK_SHIFT 0
+#define SI_EMPTY_MASK U(0x01)
+#define SI_STALL_ACK_MASK U(0x01)
/* Bit positions of SIx_SI_INT_STATUS */
#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
@@ -40,11 +41,11 @@
#define PMU_REQ_INT_STATUS_SHIFT 2
#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
#define FAILED_ACCESS_INT_STATUS_SHIFT 0
-#define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1
-#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1
-#define PMU_REQ_INT_STATUS_MASK 0x1
-#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1
-#define FAILED_ACCESS_INT_STATUS_MASK 0x1
+#define PMU_REQ_INT_OVERFLOW_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK U(0x1)
+#define PMU_REQ_INT_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK U(0x1)
+#define FAILED_ACCESS_INT_STATUS_MASK U(0x1)
/* Bit positions of SIx_TZ_FAIL_CONTROL */
#define DIRECTION_SHIFT 24
@@ -52,21 +53,21 @@
#define PRIVILEGED_SHIFT 20
#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
-#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1
+#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 1
#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
-#define DIRECTION_MASK 0x1
-#define NON_SECURE_MASK 0x1
-#define PRIVILEGED_MASK 0x1
-#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1
-#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1
-#define FAILED_ACCESS_INT_TZ_FAIL_MASK 1
-#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1
+#define DIRECTION_MASK U(0x1)
+#define NON_SECURE_MASK U(0x1)
+#define PRIVILEGED_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK U(0x1)
+#define FAILED_ACCESS_INT_TZ_FAIL_MASK U(0x1)
+#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK U(0x1)
/* Bit positions of SIx_FAIL_STATUS */
#define FAIL_ID_VNET_SHIFT 24
#define FAIL_ID_ID_SHIFT 0
-#define FAIL_ID_VNET_MASK 0xf
-#define FAIL_ID_ID_MASK 0xffffff
+#define FAIL_ID_VNET_MASK U(0xf)
+#define FAIL_ID_ID_MASK U(0xffffff)
/* Bit positions of SIx_SI_STATE_CONTRL */
#define SI_STALL_REQ_GO 0x0
@@ -81,44 +82,44 @@
#define PMU_REQ_INT_EN_SHIFT 2
#define OVERLAP_DETECT_INT_EN_SHIFT 1
#define FAILED_ACCESS_INT_EN_SHIFT 0
-#define PMU_REQ_INT_EN_MASK 0x1
-#define OVERLAP_DETECT_INT_EN_MASK 0x1
-#define FAILED_ACCESS_INT_EN_MASK 0x1
-#define PMU_REQ_INT_EN 0x1
-#define OVERLAP_DETECT_INT_EN 0x1
-#define FAILED_ACCESS_INT_EN 0x1
+#define PMU_REQ_INT_EN_MASK U(0x1)
+#define OVERLAP_DETECT_INT_EN_MASK U(0x1)
+#define FAILED_ACCESS_INT_EN_MASK U(0x1)
+#define PMU_REQ_INT_EN U(0x1)
+#define OVERLAP_DETECT_INT_EN U(0x1)
+#define FAILED_ACCESS_INT_EN U(0x1)
/* Bit positions of SIx_SI_INT_CLR */
#define PMU_REQ_OFLOW_CLR_SHIFT 18
#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
#define PMU_REQ_INT_CLR_SHIFT 2
#define FAILED_ACCESS_INT_CLR_SHIFT 0
-#define PMU_REQ_OFLOW_CLR_MASK 0x1
-#define FAILED_ACCESS_OFLOW_CLR_MASK 0x1
-#define PMU_REQ_INT_CLR_MASK 0x1
-#define FAILED_ACCESS_INT_CLR_MASK 0x1
-#define PMU_REQ_OFLOW_CLR 0x1
-#define FAILED_ACCESS_OFLOW_CLR 0x1
-#define PMU_REQ_INT_CLR 0x1
-#define FAILED_ACCESS_INT_CLR 0x1
+#define PMU_REQ_OFLOW_CLR_MASK U(0x1)
+#define FAILED_ACCESS_OFLOW_CLR_MASK U(0x1)
+#define PMU_REQ_INT_CLR_MASK U(0x1)
+#define FAILED_ACCESS_INT_CLR_MASK U(0x1)
+#define PMU_REQ_OFLOW_CLR U(0x1)
+#define FAILED_ACCESS_OFLOW_CLR U(0x1)
+#define PMU_REQ_INT_CLR U(0x1)
+#define FAILED_ACCESS_INT_CLR U(0x1)
/* Macro to get the correct base register for a system interface */
#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
-#define MAX_SYS_IF_COUNT 2
+#define MAX_SYS_IF_COUNT U(2)
#define MAX_REGION_VAL 8
/* DMC-500 supports striping across a max of 4 DMC instances */
#define MAX_DMC_COUNT 4
/* Consist of part_number_1 and part_number_0 */
-#define DMC500_PERIPHERAL_ID 0x0450
+#define DMC500_PERIPHERAL_ID U(0x0450)
/* Filter enable bits in a TZC */
-#define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1
+#define TZC_DMC500_REGION_ATTR_F_EN_MASK U(0x1)
/* Length of registers for configuring each region */
-#define TZC_DMC500_REGION_SIZE 0x018
+#define TZC_DMC500_REGION_SIZE U(0x018)
#ifndef __ASSEMBLY__
@@ -134,18 +135,17 @@
} tzc_dmc500_driver_data_t;
void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
-void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr,
+void tzc_dmc500_configure_region0(unsigned int sec_attr,
unsigned int nsaid_permissions);
-void tzc_dmc500_configure_region(int region_no,
+void tzc_dmc500_configure_region(unsigned int region_no,
unsigned long long region_base,
unsigned long long region_top,
- tzc_region_attributes_t sec_attr,
+ unsigned int sec_attr,
unsigned int nsaid_permissions);
-void tzc_dmc500_set_action(tzc_action_t action);
+void tzc_dmc500_set_action(unsigned int action);
void tzc_dmc500_config_complete(void);
int tzc_dmc500_verify_complete(void);
#endif /* __ASSEMBLY__ */
-#endif /* __TZC_DMC500_H__ */
-
+#endif /* TZC_DMC500_H */